Basic Interview Questions on DFT.

2.Scan:
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What is the significance of scan-compression/EDT during ATPG?To decrease the TDV and
TAT
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What is the reason for increase in pattern count for compressed mode?Because the chain
lenght is small,more number of chains exist.More number of control bits toidentify faults in
EDT.
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The actual compression achieved will be less than the specified compression
factor.Why?Because of extra cycles(initialization cycles) in EDT.
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Deciding factors of scan design? Number of channels on tester, memory available on
channel and number of scan pins.
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Scan length, Scan chains, hierarchical scan concept?
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How scan chains are handled from a 3
rd
party IP in the chip?By using "add subchain command"
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Use of LOCKUP latch?a) When two clock domains exist , b) When one domain with different
edges trigger the flops,c) When clock skew is more than half cycle of hold time.
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Difference between LOS and LOC?Look for the basic differences in the guide.Other
difference is that in LOS,there is a chance of testing unrequired functional paths because of
last shift is done when SE=1.
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Scan considerations required for At-speed test?a) OCC that supports and generate 2 pulses
for capture cycle. b) Free running functional clocks.
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What are advantages of LOS and disadvantages when compared to LOC?
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How do you avoid limitations of LOS?a) Consider SE as clock, b) Pipeline scan enable.
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How do we manage chain balancing and what is the requirement?
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Timing issues specific to scan chain clock domain mixing?Hold issues.Use lockup latch to
avoid them.Clock skew to be decreased.
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How to avoid hold issues when scan chain is stitched from +ve edge to –ve edge flop?