CSSE4010 – Digital System Design

Prac 2 – Registers and Combinational Logic in VHDL

Note: Things take time. So be prepared with the lab activity, do all the preliminary designs
and as much implementation as you can beforehand.

Design Task
Design and simulate a 4-digit combinational lock. The system has the following inputs and outputs
(not drawn using standard schematic symbols) and the operation is described as bellow.

Digit A (4 bits)
Lock
Digit B (4 bits)
Button 1 Unlock
Button 2 Four seven segment display output
Reset

The 4 hex digits are entered to the system, two digits at a time (using Digit A and Digit B 4-bit inputs,
possibly coming from slide switches) with Button 1 and Button 2 inputs to trigger the input processing.
After reset, two hexadecimal digits are entered into the inputs Digit A and Digit B. The first button
(Button 1) is pressed and the two digits are entered to the system and show up as the first two digits
on the seven segment displays (Digit 1 and Digit 2). The user changes the Digit A and Digit B inputs to
the next two digits of the 4-digit code. The user then presses the 2nd button (Button 2) and the next
two digits are entered to the system and displayed on the remaining two seven segment displays (Digit
3 and Digit 4). If the 4-digit code is correct at this stage, the lock opens, and indicated as the Lock
output being 0 and Unlock output being 1. If the user changes the slide switches for Digit A and Digit
B inputs without pressing the Buttons, once the lock is open, the lock will remain open (i.e., the system
is not responsive to the changes of slide switches unless the values are entered by pressing the two
Buttons). When the reset button is pushed the display is cleared to 'AAAA' and the lock is locked once
again (i.e., Lock is high and Unlock is low). The correct code to open the lock is the last four digits of
your student number.

Complete this specification as you see fit and state any assumptions you make. Your VHDL must use
'data flow' or 'behavioural' description styles to implement the locking/unlocking function. For storing
the inputs, you will need sequential circuit elements. A simple approach would be to clock the 8-bit
input value into Registers using the two push buttons as two separate clocks. An example VHDL
implementation of a register is provided to you and you may modify this file accordingly or use your
own. As there are two clocks this is an asynchronous solution. A fully synchronous solution implies that
all storage elements update on a single global clock edge and in this case the push buttons can be
used as clock-enable signals. You will also need a hex-to-seven-segment decoder to convert the
hexadecimal numbers to display on seven segment display outputs.

VHDL Implementation
Implement both the synchronous and asynchronous solutions of the combinational lock as VHDL
designs. Create a source files for both implementations: locktop_sync.vhd and locktop_async.vhd file

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and test them for correct functionality using simulation. The locktop_sync/async files must use a
structural design approach to connect various modules you need. Create a source file lock_sync.vhd
or lock_async.vhd that implements the combinational lock functionality for synchronous and
asynchronous designs, respectively. The lock_sync/async file must use dataflow and behavioural
design approaches. You may create other VHDL files, as needed. An example of a register is:
reg_simple.vhd which is provided for you to look at and use (on BB), if you wish to do so (this file will
have added functionality which you might not need). You will also need to create a hex to seven
segment decoder module.

Refer to the textbook Roth: Chapter 1 and Chapter 2, and CSSE4010 lectures. For more detailed
references read the Vivado synthesis guide manual (on blackboard) regarding how to describe
combinational logic and registers you need in your design. Structural (or netlist of components) is not
a valid solution (for lock_sync/async files).

Simulation
Create a test bed to simulate your combinational lock for both synchronous and asynchronous
designs. The testbed should import your locktop_sync/async.vhds file as a component. The testbed
should use the following test pattern as the 8 slide switch inputs, shown below (24 bit pattern).

<8 digit student ID ><8 digit student ID XOR 0x11111111><8 digit student ID XOR 0x22222222 >

The test bed should cycle through all bits of the slide switch test pattern, left shifting the pattern by 2
digits (8bit shift), each cycle.

e.g. Test pattern is 0x12345678032547693016745A for student ID of: 12345678

cycle 0) Test pattern given to the test = 0x12
cycle 1) Test pattern given to the test = 0x34
cycle 2) Test pattern given to the test = 0x56

After each test pattern is set as the inputs, the testbed must generate a signal to simulate the push
button(s) being pressed. Create a self-checking testbed, that should display a message, when the lock
has been opened. Experiment with the waveform viewer to group signals together and display
numeric values, rather than straight binary signals (e.g. for seven segment display). You must be able
to show the waveforms for key functionality, e.g. when unlock occurs. You should be able to run the
entire simulation and then zoom in on the key sections.

Hints
Much like in regular programming, abstraction can be a useful tool in VHDL to simplify design and
production. Writing a single, complex behavioural component that handles all inputs and outputs can
be complex. However, writing a series of smaller components, which you can individually check and
can connect together structurally helps you to break the program down into smaller, more
manageable sub-systems. This is known as a top-down design approach.

This is where a circuit diagram is helpful. By drawing a diagram that divides the top-level circuit up
into distinct sections, you can break down the complexity of the whole design across a number of
simpler sections. If you can design the circuit using standard circuit elements such as a multiplexer, an
adder, a register, etc., and you have circuit that shows the structural layout of these elements, you
need only design the elements in VHDL and then connect them structurally, and you have a testable
circuit.

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Report Content and Format

A typeset PDF report must be submitted by the due date with the following content:
• Introduction stating the problem description, any assumptions, and design objectives
• Design description including a block diagram explaining the complete design. Block diagrams
should be drawn using standard symbols for inputs/outputs, signals and busses as shown
below.

• Detailed simulation results showing the key scenarios to prove that the design is functionally
correct and delivers the expected output.
• Register transfer level (RTL) schematic of the design obtained from Vivado tools (you should
try to back-annotate the RTL schematic and try to identify the basic sub-systems/blocks in
your design)
• Synthesis results including FPGA resource consumption
• Conclusion – a reflection of what you’ve achieved in this exercise, problems (if you had any)
and potential improvements to your design (if any)
• References (if any)
• You must have the marking sheet on the next page as the last page of your report and your
marks will be indicated on this sheet (this has also been uploaded on BB as a single pdf file
so that you can append this to your report as the last page)

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Marking Criteria
The pracs in this course are marked to a specific criteria. This means you must demonstrate sufficient
understanding and functionality and the marking will be done according to the rubric provided below.
You must attempt each prac (i.e., a report must be received by the due date) to pass the course. All
designs VHDL code used must be your own work. You are NOT permitted to use other VHDL code
sources, unless directed to. Plagiarism is unacceptable and please read and understand the School
Statement on Misconduct, available on the ITEE website at: http://www.itee.uq.edu.au/itee-student-
misconduct-including-plagiarism . To avoid problems make sure that your VHDL code is the product
of your work and do not let anybody else 'reuse' your code.

Marks Criteria
Simulation
0 Simulation not attempted or does not work
1 Simulation partially works for one or both designs (waveforms only)
2 Simulation fully works (no self checking) for only one design
3 Simulation fully works (self checking) for only one design
4 Simulation fully works (self checking) for both designs
Report
0 No evidence of content or work
1 Some content, insufficient explanation of circuit
2 Reasonable content, some explanation of circuit
3 Good content, reasonable explanation of circuit
4 Excellent content, good explanation of circuit
Oral assessment
0 No knowledge of the design
1 Very little knowledge of the design
2 Reasonable knowledge of the design
3 Good knowledge of the design.
4 Excellent knowledge of the design.
Total (12): Marker Initials:

Date:

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