CSSE4010 – Digital System Design – Tutorial 5

1. Compare and contrast various adder circuits for N-bit addition taking into account their area and
time complexities.

2. Using a diagram and expressions, describe the operation of an N-bit carry look-ahead (CLA)
adder. Determine the number of gates required to implement this N-bit CLA adder, assuming no
fain-in constraints of the gates. You can assume the use of AND, OR, XOR gates with any number
of inputs.

3. Design a 4-bit serial adder and explain its operation. Employ data path and controller design
methodology.

4. Design a 4-bit (i.e. 4 by 4) multiplier using the concept of 4-bit repeated addition with shifts and
adds and explain its operation. Employ data path and controller design methodology.

5. Design a parallel divider circuit for positive integers that divides an 8-bit dividend by a 4-bit
divisor to obtain a 4-bit quotient. Use repeated subtraction method. Employ data path and
controller design methodology.

Some of the problems are based on the text-book Fundamentals of Logic Design by Charles H. Roth Jr.