CESE 4035 – Computer Arithmetic

Take Home Exam (THE)

• THE counts for 40% of the CESE 4035 final grade.
• The solutions submission deadline is April 20th 2023 (before or at the actual
exam). This is a firm deadline! No extensions will be granted.
• This is an individual assignment and you should treat it as such. In case of
detected collaboration all the involved parts will be equally penalized.
• THE consists of 10 questions, each of them counting for 10 points. The total
point amount one may get is 100, which corresponds to a 10.
• Try to be concise and to the point in presenting your solutions, but do not just
write down the result without explaining how did you arrived to it.
• If you decide to go for handwritten solutions, be sure that your handwriting is
“decipherable”.
• Do not forget to write your name and study number on the answers.

Good luck!

1. (10 p) Consider a number system with r = 6 and the digit set [-3, 5]. Find the
relevant parameters for a carry-free addition in this system. For such a system,
assuming that the digits in position i are xi and yi, the position sum is pi = xi +yi,
and the interim sum wi = pi – 6ti+1.

a. Deduce the logic equations for the circuit that produces the transfer digit
ti+1.
b. Sketch a possible implementation (you may use Full Adders and basic
Boolean gates) for the circuit that computes the interim sum wi = pi – 6ti+1
and the final sum si = wi + ti, while trying to minimize its cost and latency.

2. (10 p) Consider the Residue Number System RNS(16|15|13).

a. Which is the dynamic range for this system and the representational
efficiency?
b. Represent the numbers x = 60 and y = - 35 in this system.
c. Compute x + y, x – y, and x * y in this system.
d. Using standard Boolean Gates and Full Adders, design an adder for the
given RNS. Compare this design with an equivalent ripple carry adder for
2’s complement numbers covering the same dynamic range, in terms of
area and delay. Is this RNS system more effective from the addition point
of view than the equivalent standard 2’s complement counterpart?
e. Is (3|4|5)RNS(16|15|13) larger or smaller than (0|2|4)RNS(16|15|13)? Justify your
answer.
3. (10 p) Assume that basic Boolean gates, Full/Half adders, 2:1 Multiplexers, and 4-
bit Carry Look-Ahead circuits are available and you have to design a significand
adder to be utilized into an IEEE single precision Floating Point Unit (FPU). Your
possible options are to implement the adder by pursuing one of following
strategies: (i) Carry Look-Ahead, (ii) Two-Level Carry Select, or (iii) Optimal
Variable-Block Carry-Skip.

a. Draw the organization of your adder corresponding to each of the previously

mentioned strategy.
b. Make you own (plausible) assumptions about the delay and area of each
available basic building block and compare the 3 adder implementations in
terms of area and delay. Given that your selection criterion is cost-
effectiveness, i.e., area-delay product, which design will you choose for the
FPU implementation?

4. (10 p) Draw the prefix graph for a 25-bit hybrid carry network built with two
levels of the Brent-Kung scheme at each end and the rest with Kogge-Stone.
Report the area and the delay of your 25-bit adder implementation.

5. (10 p) Design a (5,5;4)-counter using Full Adders and Half Adders as building
blocks, with the least possible delay. Use such counters to reduce eleven 8-bit
numbers to two rows while minimizing the cost and delay.

6. (10 p) Design a Functional Unit to compute z = 2a×b – 3c + 5d, where a, b, c, and

d are integers in the range [-4,3] represented in the 2’s complement system.

a. What is the least number of bits required to represent z?

b. Draw the multi-operand addition matrix and optimize it. Hint: In the
optimization you can make use of the following property: (xn-1, …, xn-1,xn-
2, …, x0) = (1,1,….1,0,…0) + (0,…,0,xn-1’, xn-2,…, x1,x0).
c. Implement the reduction of the optimized multi-operand addition matrix to
two operands, while minimizing the delay and the number of Full/Half
Adders in your design.
d. Which is the delay of this Functional Unit if the carry propagate adder that
produces the final results is implemented as a Brent-Kung parallel prefix
adder (sketch its design)?

7. (10p) Design two possible (7:2) counter implementations while making use of
Full/Half Adders only. Compare the two designs in terms of cost and delay.
Which one is more effective?

8. (10p) Design a 5x4 multiplier for 2’s complement signed numbers by using
Baugh-Wooley combined with the Wallace approach. Redo the design while
making use of sign extension instead of Baugh-Wooley. Compare the two designs
in terms of area and delay. Which one is more effective?
9. (10p) Compute the square root q of the following single precision floating point
number z = (01000010001101111000000000000000), using the radix-2
restoring algorithm. Represent q as a single precision floating point number.

10. (10 p) Given the floating-point operands a = 0.29826 x 106, b = -0.29824 x

106, and c = 0.14321 x 102.

a. Compute their sum as (a + b) + c and as a + (b + c) under the assumption

that no guard digits are available.
b. Repeat the computation under the assumption that one guard digit is
available.
c. Comment on the results of parts a, and b. How many guard digits are
necessary in this case for the associative low to hold?