VLSI System Design Lab

EXPERIMENT 3
4-bit Full Adder

Course Instructor :Bhupendra Singh Reniwal

Date : 2nd feb 2022

AKKALA VIKAS
EVD18I004

AIM :
1. Design and implement a 4-bit Full adder using Gate-level,
Dataflow and Behavioral styles of coding.
2. Write a test bench to verify your designs for all the modes of
function.
3. Perform Behavioral simulation, Synthesis, Implementation and
Bit-stream generation for each of the styles.
4. Report the schematics for all three, obtained after RTL analysis,
Synthesis and Implementation.
5. Generate and compare Hardware utilization and Power reports
for the designs. Find which style of coding is more efficient
overall and support your conclusion with a clear comparison table.
Apparatus : Xilinx Vivado
Theory:
● N bit parallel Adder works in different stages
● Each full adder takes the carry-in as input and produces
carry-out and sum bit as output.
● The carry-out produced by a full adder serves as carry-in for
its adjacent most significant full adder.
 ● When carry-in becomes available to the full adder, it activates
the full adder.
● After full adder becomes activated, it comes into operation

Code:
4 bit Full adder(Behavioural):
`timescale 1ns / 1ps
module fourbitfulladder_b(a,b,c_in,sum,c_out);
input [3:0]a,b;
input c_in;
output reg [3:0]sum;
output reg c_out;
always @ (a or b or c_in)
{c_out,sum}= a + b + c_in;
endmodule

4 bit Full adder(Structural):

`timescale 1ns / 1ps
module fourbitfulladder_s(a, b, c_in, sum, c_out);

input [3:0]a;
input [3:0]b;
input c_in;

output [3:0]sum;
output c_out;
wire [2:0]w1;

onebitfulladder_s adder1(a[0], b[0], c_in, sum[0],w1[0]);

onebitfulladder_s adder2(a[1], b[1], w1[0], sum[1],w1[1]);
onebitfulladder_s adder3(a[2], b[2], w1[1], sum[2],w1[2]);
onebitfulladder_s adder4(a[3], b[3], w1[2], sum[3],c_out);

endmodule

1 bit Full adder(Structural):

`timescale 1ns / 1ps
module onebitfulladder_s(a, b, c_in, sum, c_out);
input a, b, c_in;
output sum,c_out;
wire [2:0]w;
xor (w[0],a,b);
xor (sum,w[0],c_in);
and (w[1],w[0],c_in);
and (w[2],a,b);
or (c_out,w[1],w[2]);
endmodule

4 bit Full adder(Dataflow):

`timescale 1ns / 1ps
module fourbitfulladder_d(a,b,c_in,sum,c_out);

input [3:0]a;
input [3:0]b;
input c_in;

output [3:0]sum;
output c_out;

wire [2:0]w1;

onebitfulladder_d adder5(a[0], b[0], c_in, sum[0],w1[0]);

onebitfulladder_d adder6(a[1], b[1], w1[0], sum[1],w1[1]);
onebitfulladder_d adder7(a[2], b[2], w1[1], sum[2],w1[2]);
onebitfulladder_d adder8(a[3], b[3], w1[2], sum[3],c_out);

endmodule

1 bit Full adder(Dataflow):

`timescale 1ns / 1ps
module onebitfulladder_d(a, b, c_in, sum, c_out);
input a, b, c_in;
output wire sum,c_out;
wire [2:0]w;
assign sum = a^b^c_in;
assign c_out = (a&b)|(b&c_in)|(c_in&a);
endmodule

Testbench:
`timescale 1ns / 1ps
module tb();
reg [3:0]a;
reg [3:0]b;
reg c_in;

wire [3:0]sum_b;
wire c_out_b;
wire [3:0]sum_d;
wire c_out_d;
wire [3:0]sum_s;
wire c_out_s;

integer i,j;
fourbitfulladder_b cut1(a,b,c_in,sum_b,c_out_b);
fourbitfulladder_d cut2(a,b,c_in,sum_d,c_out_d);
fourbitfulladder_s cut3(a,b,c_in,sum_s,c_out_s);
initial
begin
a= 0;b=0;c_in=0;
for(i=0;i <=15;i = i+1)
for(j=0;j <=15;j = j+1)
begin
c_in <=0;
a <= i;
b <= j;
#1;
c_in <=1;
#1;
end
$finish;
end
endmodule

Simulation:

Simulation for all possible inputs

 Simulation

Simulation

Rtl schematic:
Behavioural:

RTL of 4-bit full adder

Structural:
 RTL of 4-bit full adder

RTL of 1-bit full adder

Dataflow:

RTL of 4-bit full adder

 RTL of 1-bit full adder
Synthesis:
Behavioural:

Synthesized schematic
 Package and device layout
Structural:

Synthesized schematic
 Package and device layout
Dataflow:

Synthesized schematic
 Package and device layout
I/0 Ports:

I/o ports
Implementation:
Power report:

Behavioural
 Structural

Dataflow

Onchip power behavioural

Onchip power Structural

 Onchip power dataflow
Utilization report:

Behavioural modeling

Structural modeling

Dataflow modeling
Bitstream generation:
 Bitstream
Observations:
● In this case of a 4 bit full adder we see that the behavioral
model has least number of lines in code and has the best
readability than that of gate level and data flow model
● Simulation Outputs from each style are observed and
compared
● The Register transfer level schematic of the behavioral
model is much smaller in area than of the structural and
dataflow ,the schematic of structural and data flow are
similar
● All the models here have used similar number of Lut’s
● Since there are similar number of hardware entities the
power consumption is also similar in all the three cases
● For this kind of a circuit the three modeling styles are
equally efficient

Behavioural Dataflow Structural

Hardware 4 lut’s 4 lut’s 4 lut’s

utilization
Area Same no.of Lut’s Same no.of Lut’s Same no.of Lut’s
so similar area so similar area so similar area

Power Similar range of 3.16W same as 3.156W similar

power to drive other models power
the lut’s 3.156W

Conclusions:
We have implemented 4-bit full adder using behavioral ,structural and data
flow modeling styles and observed the simulation results using behavioral
simulation
We have also synthesized,implemented and generated the bitstreams in each
style and observed the power and utilization reports
Applications:
● Adders are used as a part of many large circuits
● Some commonly used adders are ripple carry adder,carry look ahead
adder,carry save adder
● Are used in AlU’s
● Used in Multipliers for addition purpose