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Dr. Maged Aldhaeebi
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Ripple carry adder logic circuit
:Outline
1. Introduction
2. Design Methodology
3. Results and discussion
4. Conclusion
Introduction
A ripple carry adder is a digital circuit that produces the
arithmetic sum of two binary numbers. It can be constructed
with full adders connected in cascaded.
It is a logic circuit in which the carry-out of each full adder
is the carry in of the succeeding next most significant full
adder. It is called a ripple carry adder because each carry bit
gets rippled into the next stage.
One of the main uses for the Binary Adder is in arithmetic
and counting circuits.
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Ripple carry adder logic circuit
Design Methodology
We will start by explaining the operation of one-bit full adder which will be the basis for
constructing ripple carry.
Basic Binary Adder circuit can be made from standard AND and XOR gates allowing us to
“ADD” together two single bit binary numbers A and B
Full adder is a logic circuit that adds two input operand bits plus a Carry in bit and outputs a Carry
out bit and a sum bit. The Sum out (SOUT) of a full adder is the XOR of input operand bits A, B and
the Carry in (CIN) bit. Truth table and schematic of a single bit Full adder is shown below.
Design Methodology
Multiple full adder circuits can be cascaded in parallel to add an N-bit number. For an N- bit
parallel adder, there must be N number of full adder circuits.
with the carry output from each full adder connected to the carry input of the next full adder in
the chain. Figure 3 shows the interconnection of four full adder (FA) circuits to provide a 4-bit
ripple carry adder. Notice from Figure 3 that the input is from the right side because the first cell
traditionally represents the least significant bit (LSB). Bits A0 and B0 in the figure represent the
least significant bits of the numbers to be added. The sum output is represented by the bits S0—
S3.
Design Methodology
Design Methodology
Design Methodology
Conclusion
Conclusion
References
1. Rawwat K., Darwish T. and Bayoumi M., A low power carry select adder with reduces area, Symposium
on Circuits and Systems
2. 2. Tyagi A., A reduced area scheme for carry IEEE Trans. on Computer,
3. 3. Jeong W. and Roy K., Robust high power adder, Proc. of the Asia and South Pacific Design
Automation Conference
4. 4. Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply and Peter A. Beerel, Specu of high-
performance asynchronous dynamic adders. In Proceedings of the 3rd International Symposium on
Advanced Research in Asynchronous Circuits and Systems, page 210, IEEE Computer Society,
5. 5. Safi Seyyed Mohammad, Ras Kaboli Mina and Safi Fatemeh Sadat, An Efficient Residue to Binary
Converter for the New Two Moduli Set, Research Journal of Recent Sciences, 83-86, (2012)
6. Kang Sung-Mo (Steve) and Leblebici, Yusuf. CMOS Digital Integrated Circuits Analysis and Design,
Third Edition, McGraw-Hill, (2002)
7. Tocci, Ronald J. and S. Neal Widmer, Digital Systems: Principles and Applications, 8th Edition, Prentice
Hall, (2001)
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Ripple carry adder logic circuit
Acknowledgments
I would like to thank Dr. Maged Aldhaeebi for their suggestions and
advice for working on this project.