CSSE4010 - Digital System Design - Semester 2 2023

Week Lecture - Tue 4-6pm Tutorial - Thu 2-3pm Practical Assessment Due
1 1 Introduction/Logic Minimisation (25 Jul) 1 Revision on Number Representations (27 Jul) 1 Introduction to HDL+Tools
2 2 Combinational Logic and VHDL (1 Aug) 2 Logic Minimasation (3 Aug) Prac 1 continues
Prac 1 report
3 3 Sequential Circuits and VHDL (8 Aug) 3 Combinational Logic (10 Aug) 2 Combinational circuits
(Mon 7 Aug 4pm AEST)
Prac 2 continues
4 4 Arithmetic Circuits and VHDL (15 Aug) 4 Sequential circuits (17 Aug) Wed 16 Aug prac sessions will be
rescheduled due to holiday
Prac 2 report
Finite State Machines (FSMs) and VHDL
5 5 5 Arithmetic circuits (24 Aug) 3 Arithmetic circuits (Mon 21 Aug 4pm AEST)
(22 Aug)
Prac 2 oral assessments*
6 6 More on FSMs (29 Aug) 6 State Machines (31 Aug) Prac 3 continues
Prac 3 report
Controller-Datapath Design and Programable
7 7 7 State Machines (7 Sep) 4 Sequential circuits (Mon 4 Sep 4pm AEST)
Logic (5 Sep)
Prac 3 oral assessments*
8 8 DSP Impementation Aspects - part 1 (12 Sep) 8 Controller-Datapath Design (14 Sep) Prac 4 continues
Prac 4 report
9 9 DSP Impementation Aspects - part 2 (19 Sep) 9 DSP Implementation (21 Sep) 5 DSP Implementation (Mon 18 Sep 4pm AEST)
Prac 4 oral assessments*
Semester Break
10 10 DSP Impementation Aspects - part 3 (3 Oct) 10 DSP Implementation (5 Oct) Prac 5 continues
Prac 5 report
CMOS Logic Families and Timing Aspects
11 11 11 Design Examples (12 Oct) (Mon 9 Oct 4pm AEST)
(10 Oct)
Prac 5 oral assessments*
Project
12 12 Guest Lecture (TBC, 17 Oct) 12 Design Examples (19 Oct)
Project Report
13 13 Exam Revision Session (24 Oct) No Tutorial Fri 27 Oct 4pm AEST
Revision Period
Final Exam Period
* During individual lab sessions