Agenda

• Introduction
• Test Strategy
– Logic
– Memory
– IP
• System Test Offering
• MIDAS Architecture and Flow
– SSTM: Web DFT flow
– Core Level DFT
– Top Level DFT
Introduction to TI ASIC DFT
• What TI ASIC DFT is responsible for:
– DFT planning and customer interaction
– DFT architecture for entire design (subchips, IPs and
top-level)
– Generation, integration and verification of test
structures
– STA constraints for test modes
– Test Vector generation (TI-TDL format) and handoff to
TI Product Engineering (PE)
– Silicon debug support to TI PE team
Logic Test
Logic Test Architecture
• Approach – Scan and ATPG Based
• Architecture – Hierarchical divide-and-conquer strategy

• Need – 100% Mux- D full scan – all exceptions must be reviewed

• Fault Models
– Mandatory
• Stuck-at faults
• Transition faults
– Including Ram Sequential Testing
• IDDQ
– Under Evaluation
• Targeted Path Delay
• Bridge Defects
• Small Delay Defects
Hierarchical Scan Architecture Scan Enable
(t2c_se)
Scan In
(t2c_si)

• Hierarchical Scan Architecture Scan Enable

Block
Scan Pipelines

– I/O Bounding Chains De-compressor

• Synopsys DFTCompiler
integrated shared bounding
solution

O/P Bounding Chains

I/P Bounding Chains
– Dedicated wrapper cell
Core Chains
– Shared wrapper cell
• Scan Test Modes
– INTEST
• Compression
• Bypass
– Non-hierarchical (Bounding transparent) Compactor

• Compression Scan Pipelines

• Bypass
– EXTEST Bypass Logic
(Distributed Scan)

Sub-chip Select
(t2c_subchip_sel)
Scan Out
(t2c_so)
Scan Mode Clocking
• Scan Shift:
– Single shift clock (TI_TEST_CLK) for all flops inside design

• Scan capture:
– Capture enables for all clock domains for individual control
– Stuck-at:
• Separate capture enables used
• Single or multiple set of patterns using named capture procedure in
ATPG tools
• Separate mode where TI_TEST_CLK can be used for capture on
cross-domain logic – hold violations on true paths must be fixed
– Transition fault:
• Separate capture enables used
• Multiple set of patterns (1 for each clock domain)
Scan Clocking Examples
SCAN_ENABLE

STUCK-AT
TI_TEST_CLK (shift clock) Capture

Scan-in
Scan-out
SCAN_ENABLE

TI_TEST_CLK (shift clock) TF Launch-off-Capture

Launch Capture

Scan-in Scan-out

Period = {1/functional frequency} = Dead-cycle

SCAN_ENABLE

N Captures
Sequencial Patterns
TI_TEST_CLK (shift clock)
…

Scan-in Scan-out
Period = {1/functional frequency}
Memory Test -PBIST
Need for PBIST
• Hard memory defects have always been around
• Subtle defects are on the rise for 40nm and 28 nm
– Could be dependent on varying operational constraints
like PVT
– Could be dependent on test algorithm
– Could be dependent on test modes

• Pre-programmed (compile-time) algorithms in a BIST

controller are no longer sufficient – we do not know what
defects could show up on first silicon

• Solution: Run-time programmable BIST (PBIST)

Memory Test – Programmable BIST
• Run-time programmable BIST (PBIST)
– What can be changed at run-time on the tester?
• Algorithm
• Background
• Read/write sequence
• Row/column march
• Interleaving
• Margin modes
• Serial/parallel mode
• Noise in other memories

• PBIST Components
– PBIST controller
• Controller is a limited capability CPU
• Two 32 bit data interfaces
• Dual address and data generators and comparators
• TI-VLCT compliant datalogger interface

– Memory Data Path connecting PBIST controller to memories

• Pipelines and return data muxes

– An interface to load algorithms and memory information to the controller Instruction Registers
• VLCT interface
• On-chip RAM/ROM interface
Production Algorithms available for PBIST
• BIG6 • IDDQ
– March13N – Zeros
– Down1A – Ones
– Mapcolumn – Row-stripe/Inv Row-Stripe
– Precharge – Powerup/Inv Powerup
– DTXN2
– PMOS Open

• ROM • RETENTION
– Triple Read Fast – Zeros
– Triple Read Slow – Ones
– Triple Read XOR – Row-stripe/Inv Row-Stripe
– Powerup/Inv Powerup
PBIST Block Diagram
ROM I/F VLCT I/F CFG I/F

ROM EXT CFG

Data Logger PBIST Controller

PBIST MDP (FDP + RDP)

To/From Memories
 Memory Data Path
• Forward Path

ddress and Data bits are broadcast to all memories

ithin a group -- without any gating logic
PBIST Interfaces
• ATE Interface
– Pin requirements
• Pins can be shared with other functional or test
• Input configuration bits: 8 (pbist_vlct_interface)
• Output configuration bits: 8 (pbist_rdata) (Optional – debug only)
– Can be used for production test, diagnosis and repair.

• ROM Interface
– On-chip ROM can be programmed with memory and algorithm information
– Simple interface
– Two bits that can be controlled via JTAG/CPU
– PASS/FAIL and DONE signals available at end of test
PBIST Summary

• TI believes it is imperative to have a programmable

memory test solution for 65 nm and beyond
• Hard defects have always been around. Subtle defects
are on the rise.
• pBIST is a powerful run-time programmable BIST
solution
• Main components are:
– pBIST controller
– Memory data-path (MDP)
• Demonstrated performance at 900 MHz+.
IP Test method: 1500 Access
1500 interface:

• Use for test access to Serdes, Hoover PLL, DDR,

AVS, and efuse controller
• Instructions:
– Diagnostic instructions
– Atpg instructions
• Canned patterned made at the IP level can be
ported to the top level
1500 Interface: structure
i With i+j ≤ 18 j
WPI_XXX WPO_XXX
<10 <8
WPI_SCAN_INTEST WPO_SCAN_INTEST

WBR
[n:0] [n:2]

WPI_SCAN_EXTEST WPO_SCAN_EXTEST

FI FO
W W
B CORE B
R R
FO FI

CDRs

WBY
WSI WSO
WIR

7
WRSTN, WRCK, SelectWIR, CaptureWR,
WSC ShiftWR, UpdateWR, AUXCK0, AUXCK1
 1500 interface: from ip to chip pins

JTAG
tap jtag
control
jtag21500

IP IP IP IP
1500 PMT

• Serial chain of all IP 1500 Interfaces

• Accessible from JTAG21500 bridge, for in-system test
• Accessible from shared parallel pins for manufacturing test
JTAG to IEEE 1500 Protocol Converter
jtag2_1500_dr_instr
jtag2_1500_en
jtag2_1500_ir_instr

tck wrck

selectWR
select (0=select DR states)

JTAG WSP
shiftDR-state shiftWR

captureWR
captureDR-state

updateDR-state updateWR

combined reset WRSTN

SERDES DFT
Serdes Test Strategy for Serdes
• Manufacturing tests
– Slow Functional Parametric test
– At Speed Functional BIST
– Burnin
– Slow stuck-at scan atpg
– At Speed transition fault scan atpg
– At Speed circular BIST (CBIST)
Serdes Test: Main Test Method
Receivers Central Transmitters
4x 4x

parametric &
functional parametric &
bist functional bist
parametric &
functional bist func
cbist
bist

scan scan scan

LEGEND digital analog

Serdes Test Strategy (cont.)
• SERDES testability is based on “canned TDL” and ATPG (stuck-at/tr fault)
• Canned TDL are written at SERDES level by SERDES design team using
extensive knowledge of the design/implementation
• Canned TDL are thoroughly verified on testchip silicon to ensure an
effective/robust test screen is created
– Verified across PVT including using split lots

• Correlation between tester screen and an application screen in TI lab is

performed on testchips
• Same canned TDL are used on customer production parts so customer gets
an effective screen

• TI internal tool used to build chip level TDL from canned TDL
– TDL can run on all macros simultaneously for production or individual macros for
debug
• Canned TDL are simulated at chip level with timing annotation to prove the
scrambling process has been successful
DDR DFT
40nm DDR Macro Overview
IO Ring (TI) (Including Signal and power/ Pads)
• DDR Interface
(IDID) 8-Bit Data PHY (hard) [ Vir ]
8-Bit Data PHY (soft) [ Vir ]
– 8 Bit Data Macro BIST Logic
DLL Master
– 11 Bit Command (hard) [ Vir ]
IEEE1500 (TI) DLL Master
Macro (Soft) [ Vir ]

• 2 Cmd/4 Data IO Ring (TI) (Including Signal and power/Pads)

– 16 bit Address/32
8-Bit Data PHY (hard) [ Vir]
bit data 8-Bit Data PHY (soft) [ Vir]
BIST Logic
DLL Master
(hard) [ Vir ]
IEEE1500 (TI) DLL Master
(Soft) [ Vir ]
40nm DDR Testing Strategy
• Scan/ATPG used for logic test
– At-speed TFT/SA Patterns
– EXTEST is used to test core interface logic
• At-speed BIST loop back testing of IO
– Internal and External Loopback
• 1149.1 JTAG (Boundary scan)
– Used for parametric test
• Canned patterns -IEEE1500 interface
– JTAG2IEEE1500 allow access from the board
• NOTE: Internal and External loopback are not supported in
board environment
DDR internal Loopback
TX logic TX data
Data
Data 0 Comparator pad
RX Looped back
(repeated in logic
data
other data
slices)

TX prbs

Divider

Tx clock
clock
Looped back pad
RX prbs clock

DDR PHY
IOs
DDR External Loopback
TX data
TX logic
Comparator Looped Data
Data 0 RX pad

BOARD
(repeated logic back data
in other
data slices)
TX
Divider prbs
Tx clock
clock
pad
RX
DDR PHY
prbs IOs
instX
instX acts as transmit PHY and instY
Data board trace
acts as receive PHY
TX logic TX data
Comparator Data
Data 0 RX Looped pad
(repeated logic
back data
in other
data slices)
TX
Divider prbs clock board trace

RX Rx clock
DDR PHY prbs
instY IOs
Quality Requirements and DFT Tools
40nm Quality Requirements and Tools
TEST PATTERN SET 40nm Plan of record
Step Tool
DC Parametric (JTAG BSCAN 100% Boundary scan TI ION
+ 1149.6)
JTAG TI TITAN
IDDQ, 8+4 stops 80%+
Hookup Customer or MDI
Memory BIST 100%, Programmable
Memory BIST TI PBIST
Scan Chain Test 100% Scan insertion SNPS DFTCompiler
Scan Stuck-At 99%+
Compression SNPS DFTMAX
Scan Transition At-Speed 85%+ ATPG SNPS TetraMAX

Vmin Memory Test 100% Synthesis SNPS DC-Shell

Simulations NCVerilog
RAM sequential test 85% memory ports
JTAG patterns and
Burn-in Scan; PBIST 70%+; 100%
compliance MT Combat-ADS

IP Test Canned vectors using

IEEE 1500 interface STA constraint validation SNPS PrimeTime
ESTAC
 eSTAC – JTAG based / SA + TF support
Compressed stimuli Compressed response
applied from ATE PLL REFCLK
monitored on ATE
SC with compression and decode IP
CLK/SE control SC core with N internal chains
8 PLL
8
D
E
C D
D C
SI [7:0] O 8 or 1 ESO [7:0]
8Eor 1 O
M C
C M
P O
O P
A D
D R
C E
E E
T
S
O
S
R
O
R
1
1

Common shift clock

Compressed response
(TCK) * SE can be pin or JTAG DR controlled
Compressed stimuli to JTAG
from JTAG (TDO)
(TDI)
JTAG States for Scan Control
tms

tck

Run Test/Idle

Select-DR-Scan

Shift-DR

Pause-DR

Update-DR

scanen

capture_enable

edt_update

• JTAG Shift-DR state is used for Scan-shift operation

• JTAG Pause-DR and Update-DR state are used for Capture Enable and EDT-Update operation
eSTAC (using Synopsys Serializer)
scan_in Serializer Clock Controller
FSM counter
ser_clk Deserializer  Creates “clock enable” signal to
CGC and “strobe” signal to
Serializer
Decompressor
 Driven by one of external clocks
Serializer …
… Clock Gating Cells
Clock
Controller int_clk  Produce internally generated
clocks for internal scan chains
Compressor
Deserializer registers
strobe
 Loads the scan input data
Serializer
serially and supplies it to internal
scan_out chains
Serializer registers
 Captures data from compressor
© Synopsys
outputs and transfers the data to
scan output (like a parallel-to-
serial converter)
 4 external clock pulses
How Serializer Works (cont.) required for loading to
Deserializer
1 serial input *_SCCOMP_DECOMPRESSOR
4bit Deserializer
scan_in si

ser_clk

clkA strobe Decompressor

combinational

*clkgt*
FSM

© Synopsys

*clockcntrl*
Capture
Serializer ClockCtrl

*_SCCOMP_COMPRESSOR
1 serial output
Internal clock Compressor
scan_out
pulses every 1
0
1
0
1
0
1
0
so

4 external
4bit Serializer
clock pulses
System Test Capabilities Summary
• PBIST
– accessible though JTAG
– Simple Go/nogo
– Advance JTAG2VLCT provides ability to program
– Per Memory Pass/Fail information can be provided
• IP
– Accessible though JTAG21500
• IO
– Boundary Scan
• Logic System Test
– JTAG accessible through eSTAC
– eSTAC available on subchips only (there is no compression at the
top level)
Midas Architecture
MIDAS Overview
• MIDAS – TI ASIC DFT Insertion Methodology
 Modular Integrated DFT – ASIC Solution

• Objectives
 Improve Execution Cycle Time
 Remove DFT insertion from critical design execution path
 Support RTL insertion and Gate-level insertion models
 Facilitate non-DFT team usage

 Improve Flow predictability

 Standardize test implementation
MIDAS ASIC Architecture
F-Number

IO TITAN Chipcore SSTM

STAB TAP

CL
CL SSTM logic
eFuse
PADBSR
Subchip 1

pBIST
Combiner
IO SSTM logic

JTAG to
Subchip 2
IEEE1500
BSR DFT DFT DFT
Wrapper Wrapper Wrapper
Scan
IP IP IP
Router
Subchip DFT Architecture (SSTM)
Standard Subchip Test Module
Subchip-level DFT Structure

Subchip
Memory Controlconnections

SSTM Scan chain connections (netlist)

MEM MEM MEM

Clock/Reset
Manager

Memory BIST
Wrapper

Functional Logic

eFuse Hookup

Scan
Scan
Compression

• SSTM contains all Subchip level test logic

SSTM Architecture SC1 SO
SI

SSTM

Clocks, resets and DFTMAX

other signals
BYPASS COMPRESSOR
DECOMPRESSOR So
Si
• DFTMAX-Test Compression
• MDP: Memory Data Path
eFuse Hookup
CLK/RST • FDP: Forward Data Path
• RDP: Reverse Data path
pbist_wrapper

PBIST Controller* • *Optional

PBIST MDP (FDP + RDP)

PBIST ports ROM*

Subchip Functional Logic

• Preference is to have 1 pBIST controller per subchip or share controllers for smaller
subchips
SSTM Clock Control
– Single slow clock (TI test clock ~ 125MHz) controls all functional flops
– Clock domain control per functional clock to enable scan capture

Clock Control Module (CCM)

EN

I
C func_clk_out
func_clk 0 G

io2c_test_clk 1

t2c_testmode
Mux & Gating

t2c_func_clk_domain_sel

t2c_subchip_sel

t2c_func_clk_testclk_sel
t2c_se
Control Logic
 SSTM Clock Control (cont.)
• Sub-chip PBIST clocks (ROM Clock, VLCT TCLK and Diag Clock)
– PBIST functional clocks are controlled using t2c_pbist_clken
– ROM Clock domain control (t2c_pbist_rom_domain_sel)
– VLCT TCLK and Diag Clock (t2c_tclk_domain_sel)

clkrst Module

I PBIST VLCT TCLK

io2c_pbist_tclk io2c_pbist_tclk 0
C
G
pbist_slow_clock

io2c_test_clk 1
PBIST VLCT DIAG CLK
t2c_testmode
(To PBIST)
t2c_tclk_domain_sel

I t2c_subchip_sel
func_clk1 func_clk 0
C
G
func_clk_out

io2c_test_clk 1
io2c_test_clk
t2c_testmode
func_clk2
t2c_func_clk_domain_sel
I
C func_clk_out
t2c_atpgm
t2c_se
func_clk 0 G CCM
io2c_test_clk 1
t2c_subchip_sel
t2c_testmode
I
I C rom_clk_out
func_clkn t2c_func_clk_domain_sel C func_clk_out rom_clk
/4 0 G
func_clk 0 G
fastest func. io2c_test_clk 1
PBIST ROM clock
io2c_test_clk 1
t2c_func_clk_testclk_sel
t2c_subchip_sel
clock t2c_testmode
(To PBIST + MDP)
t2c_se
t2c_testmode CCM
t2c_pbist_rom_domain_sel
t2c_func_clk_domain_sel

t2c_func_clk_testclk_sel t2c_subchip_sel
t2c_subchip_sel
t2c_se
CCM

t2c_atpgm
t2c_func_clk_testclk_sel
t2c_se
t2c_se
CCM CCM
Design Information For SSTM Creation
• TI requires the following information from
customer for the creation of:

– SSTM:
• Memory information
• Clock-for test clock muxing
• Reset-For scan reset conntrol
• Flops and scan architecture information
• Memory Placement information (to optimize BIST architecture)

return
Web-DFT for SSTM Generation
SSTM Create Flow
Customer
Customer

designSpec.xls
designSpec.xls designmem_info
designmem_info

https://midas.ext.ti.com/cgi-bin/midas.cgi

Web-DFT
Web-DFT

SSTM
SSTM RTL
RTL Verif
Verif Logs
Logs
SSTM
SSTM Gates
Gates connection_spec
connection_spec

sstm.tar.gz
sstm.tar.gz

Customer
Customer
Web-DFT (https://midas.ext.ti.com/cgi-bin/midas.cgi)
Web-DFT Screenshot (2)
Web-DFT Screenshot (3)
Web-DFT Screenshot (4)
Web-DFT Screenshot (5)
Web-DFT Screenshot (6)
Web-DFT Screenshot (7)
SSTM Create Flow
Customer
Customer

designSpec.xls
designSpec.xls designmem_info
designmem_info

https://midas.ext.ti.com/cgi-bin/midas.cgi

Web-DFT
Web-DFT

SSTM
SSTM RTL
RTL Verif
Verif Logs
Logs
SSTM
SSTM Gates
Gates Connection_spec
Connection_spec

sstm.tar.gz
sstm.tar.gz

Customer
Customer
SSTM RTL Integration
• Connection Specification Provided by TI
Example:
instantiate, ti_SME_sstm, SME/sstm_inst
createbus, SME/t2c_mem_atpgm, 0:0:input
connect, SME/U_SM_IPE/U_IPE_MEM/U_DPRAM8X512_MASK_2/U_dejh00008128010_2/cscan, SME/sstm_inst/ti_sc_SME_001_cscan

• Highly Recommend Customer uses automated tool for RTL integration

– Translate conspec
– 3rd Party automated hookup solutions are available

• TI’s “MDI” is used extensively in gate level flow

– Reads connection specification as is along with verilog and performs integration
– Is this something Cisco would be interested in?
• Most of our customer’s have own preference integration, so this tool has not been
used significantly with other customers in RTL DFT flows.
• Disclaimer: Generate statements, and some other constructs are not supported.
RTL will have to be re-written if MDI is to be used on any un-supported RTL
constructs
MDI-Module DFT Integration
Connection Specification RTL netlist

MDI

Analyze RTL
(mdiAnalyze)

Connect.info
(internal)

RTL Editor
(mdiEdit) TI DFT IP Blocks
TITAN,SSTM

Resultant RTL Verification TCL

Post SSTM Verification
• Spyglass for DFT rules
• Cadence LEC scripts provided for formal
verification
– Verifies functionality is maintained between pre-
dft and post dft RTL
• MDI outputs .tcl for simulators to check
connections are made as expected
SpyGlass for DFT Checks
• SpyGlass DFT Features and
Requirements
– Checks for Clocks, Sets, and Resets
– Checks for Latches and Tristated Buses
– Checks all things related to Scanability
SpyGlass DFT Requirements
• Source Design sgdc
…….
– RTL or Netlist or RTL+ Netlist Source …….
Designs ……..
• Technology Library (.lib) (Optional)
– Convert it into .sglib using the
SpyGlass Library Compiler
• SpyGlass Constraints(.sgdc)
SpyGlass
SpyGlass
– defines test mode conditions, such as
testclocks, test mode select signals,
and their values
• SpyGlass DFT parameters Tech Libs
(optional) Rules and
– For fine tuning of rule performance Parameters
Spyglass Netlist Rule set
• Pre-scan Spyglass Rule set
Rules Description
Info_coverage Estimate fault and test coverage.
Info_undetectCause Display undetectable fault information.
Info_atSpeedCoverageEvaluate @speed coverage for design.
Info_testmode Display testmode simulation results.
Info_testclock Display test clock propagation.
Async_02_capture Flip-flop set or reset fanin cones must not contain flip-flops latches or black-boxes in capture mode.
Async_02_shift Flip-flop set or reset fanin cones must not contain flip-flops latches or black-boxes in shift mode.
Async_06 Set and reset lines on the same flip-flop should not be simultaneously active.
Async_07 Asynchronous sources should be inactive during shift mode.
Clock_04 Do not use clock signals as data signals.
Clock_07 Do not use data as clocks.
Clock_11 Internally generated clocks must be testclock controlled in shift mode.
Clock_17 Capture clocks must not be gated by flip-flops capturing on the same clock.
Clock_21 Clocks must not drive flip-flop set or reset pins.
Scan_08 All registers and flip-flops should be scannable.
Scan_11 Scan ratio must exceed threshold.
Topology_01 Combinational loops are not allowed.
Topology_02 No asynchronous pin to pin paths.
Tristate_06 Tristate bus enables must be fully decoded so that exactly one driver is active at any time.
Tristate_07_shift All Inout ports are inputs only in shift mode.
Latch_05 Flag latches those are not transparent in the capture mode
Synthesis
• Gate level model of SSTM is provided from TI or
WebDFT
• Recommended Subchip Synthesis flow
– Include SSTM Gates during RTL synthesis
– Don’t touch SSTM during synthesis
– Use provided DFTOff constraints to allow functional
clocks to propagate
Scan/Compression Insertion
• Scan Insertion Flow Executed at TI
• Driven from MIDAS designSpec.xls Inputs
• Inserted during Scan insertion step:
– Scan
– Compression
– Bounding
– eSTAC serializer added in Synopsys flow
• Design must be full scan, all scan rules must be
met
– If all clocks and resets are defined in SSTM generation
this will be the case
Core DFT Architecture: IP Wrappers
and Clock Leakers
MIDAS ASIC Architecture
F-Number

IO TITAN Chipcore SSTM

STAB TAP

CL
CL SSTM logic
eFuse
PADBSR
Subchip 1

pBIST
Combiner
IO SSTM logic

JTAG to
Subchip 2
IEEE1500
BSR DFT DFT DFT
Wrapper Wrapper Wrapper
Scan
IP IP IP
Router
IP DFT Wrapper
• IP DFT wrapper is required to have access to facilitate the
following IP testing:
– Scan based
• ATPG patterns to test IP-internal digital logic & interface logic
• Same fault models and coverage requirements as rest of device

– IEEE 1500 Interface for IP-specific functionality testing

• IEEE 1500 is a standard interface for IP control and observability
• IP tests through 1500 include loopback, PLL control, scan access,
programmability of different bist
• Canned patterns “scrambled” for device level use
IP DFT Wrappers

IP IP

Test Mode
Test Mode
• Most IPs require a DFT wrapper
• PLLs, DLLs, DDRs, SerDes
• Wrapper will have standard control/observe names, e.g. t2c_*, c2t_*
Core PLL DFT Wrapper

clkout

PLL

Test Input Ports

EN c2t_pll_observe
1 ICG

0
Functional Ports

Test Muxes

Note: No Clock Leaker inside Core PLL DFT Wrapper

SerDes DFT wrappers
• DFT wrappers for SerDes

DFT wrapper
MACRO
Func. O/Ps
Func. I/Ps
Func. I/F

t2c_tdi c2t_tdo
t2c_tck
JTAG I/F t2c_extest
t2c_extest_pulse BSCAN I/F
t2c_extest_train Bypass
t2c_actestsignal Mechanism
WPO_EXTEST
WPI_EXTEST
1
t2c_si 1500 I/F 1 c2t_so
0
0
WPI_INTEST
WPO_INTEST
Scan I/F io2c_test_clk
t2c_ip_select
ti_dft_func_clk_in Clock auxck1
Control Signals Leaker
DFT O/Ps
DFT I/Ps
1500 I/F

iDID and TS DFT Wrappers similar to above (minus JTAG i/f and clock leaker)
Clock Leaker Implementation
Test Ports

clkin clkout
Divider
PLL Clock leaker

Test Ports

clkin clkout
PLL Clock leaker
 TI ASIC Clock Leaker

t2c_clk_ctrl [9:0]
EN c2t_cl_observe
ICG
1 1 1 1 1 1 1 1
1’b0 0 0 0 0 0 0 0 0 EN
ICG

0 0
1 1 clk_out
1
EN 0
EN
ICG ICG rcd_test_clk_ctrl
1
0
t2c_pll_bypass
t2c_se
t2c_capture_enable
t2c_transfaultmode
test_func_clk_in
t2c_test_clk
func_clk_in
t2c_atpg_mode
cust_lbist_clk
cust_lbist_mode

Note: 10 stage t2c_clk_ctrl used, not 8 as above

Core Insertion Summary
• SSTM Added if flops are present at the core level
– Scan/Compression insertion also needs to be done if
this is the case
• IP Wrappers are added to most IP
• Clock leakers are added for control of clocks for
transition fault testing
• All test connections need to be brought to the
core ports
– Inputs t2c_<subchip_ID>_<signal_name>
– Outputs c2t_<subchip_ID>_<signal_name>
Top Level DFT Architecture
(TITAN, PADBSR & STAB)
Top Level TI DFT Modules
 TITAN: TI Test Access Node, Top-level test module
 JTAG TAP Controller and Test Data Registers (TDRs)
 eFuse Wrapper, including FuseFarm with eFuse and ODP Controllers
 pBIST Combiner
 Scan Router
 JTAG to IEEE1500 bridge
 Data comes from titanSpec.xls (TI)

 PADBSR: PAD Boundary Scan Register

 IO Pad instances
 Associated Boundary Scan Register (BSR)
 Data comes from MASTER_LOGICAL sheet of ION XLS (Customer)

 STAB: Standard Test Access Bus

 test vs. functional pin muxing
 Data comes from STAB and MISC_CONNECT sheets of ION XLS (TI)
TITAN Architecture
pBIST_IO Tap_IO Fuse_IO

pBIST_Core Fuse_Core
pBIST
Combiner
eFus
e
Tap_pBIST Tap_Fuse
Tap_Core
Tap_Core TAP

Scan JTAG2_1500
Scan_Core Router Tap_Scan Tap_1500
1500_Core

Scan_IO Tap_IO 1500_IO

• TITAN includes
• 1149.1/.6 JTAG Tap Controller
• TAP supports 64 OPCODEs and 54 TDRs
• eFuse Wrapper with FuseFarm
• pBIST Combiner
• Scan Router control module for hierarchical scan control
• JTAG to IEEE 1500 Bridge
eFuse Wrapper

• FuseFarm shown (right)

• eFuse Wrapper
instantiates
– FuseFarm
– Scan Control Logic
– Clock Control Logic
– DieID Registers
– Custom Registers
pBIST Combiner
• pBIST Combiner does the following
• Propagates common JTAG signals to JTAG Subchips
all subchips, e.g. test_tap_tck to
t2c_*_pbist_tclk
• Propagates individual JTAG signals
to subchip, e.g. t2c_*_pbist_id
• Controls signals according to
whether tester pBIST or system test pBIST Combiner
• Reads subchip pBIST done, fail ,
logout signals and sends them to IO
• Has JTAG to VLCT bridge to allow
pBIST Controller programming
through JTAG IO
 (Distributed) Scan Router SO SI

• Typical STAR Scan Architecture

– Broadcast scan-in signals to all the SCs
– Sub-chip Scan out (SO) has to be routed back to TITAN
• Increases routing resources
– Supports top-level compression
– 16 Channels

• Distributed Scan Architecture SO SI SO SI SO SI SO SI SO SI SO SI SO SI SO SI

– Top-level scan chains are daisy-chained together SC150 SC7 SC6 SC5 SC4 SC3 SC2 SC1
– Reduces routing resources significantly at top-level
– Reduced functional power consumption
– Top-level compression is not possible
• EXTEST modes of subchips are leveraged

• Bypass in Each Subchip

SI Subchip
SO

Codec/
Flops

t2c_si F
F
F
ct2_so
F

t2c_subchip_sel
SO SI SO SI SO SI SO SI SO SI SO SI SO SI SO SI

SC150 SC7 SC6 SC5 SC4 SC3 SC2 SC1

JTAG to IEEE 1500
• Used to allow system board access to IEEE 1500
via JTAG interface
– Most customers have JTAG access on their boards, not
many have IEEE 1500
• TI uses native IEEE 1500 access on TI testers,
with shared pin interface in test mode
• Useful to debug issues and program IPs while in
system debug mode
Native IEEE 1500 Connectivity
TITAN CORE
IO jtag2_1500_en
CTMUX

1 t2c_wrck
io2t_wrck
!t2io_1500_mode 0
io2t_tdi
io2t_wsi 1 t2c_wsi WSP1
0

io2t_selectwir JTAG_2_1500 1 t2c_selectwir

0 WSP2
io2t_shiftwr 1 t2c_shiftwr

STAB 0

1 t2c_capturewr
io2t_capturewr
0

io2t_updatewr 1 t2c_updatewr

t2c_wrstn
io2t_wrstn 1
WSPn
t2io_wso 0

c2t_wso
t2io_tdo 1
TDO TDR MUX
0 TCK
TDO Latch

Serial connection of WSPs

PADBSR Module and I/O Connection
Receiver

BSCAN

Driver

BSCAN

Bidi

BSCAN

• PADBSR contains all boundary scan cells and IO pads

• PADBSR does not include BSCs associated with IP
PADBSR – e.g. bc_io_it
TM_GZ
bc_2 MODE3
F/F F/F
SI 1 1
1
0 0
EN EN 0

TCK

SDR CDR UDR TM TM_MODE

PI_GZ
TM_MODE1 SO
PO_GZ
GZ
TM_A F/F F/F 1
1
1 0 1 PO_A A
0 EN EN PAD
0 0

TCK Y
TM_MODE
SDR CDR UDR TM
PAD
PI_A

1
PO_Y
0

BSR bc_7 PI_Y

MODE2
STAB: Standard Test Access Bus
All
All functional
functional
inputs,
inputs
outputs, gz
Core control IO Ring
STAB (buffers
w/DFT
+ BSR)

All muxes in
this block,
common for
every IO in
All core test
each IO
input/output
Test + cell/wrapper
signals
functional
outputs, gz
control

• Interfaces between the IO pad ring and the chipcore

• Provides shared and dedicated test pin access to and from IO ring
• All input, output and enable signals pass through STAB
• Allows easy design updates for shared test pin muxing
• Dedicated test Pins:
• TI_TEST_MODE: master bidi control of shared test pins
• TI_TEST_IFORCE: analog input for on-chip PMC structures
• TI_TEST_VSENSE: analog output for on-chip PMC structures
• 5 JTAG TAP pins: TCK, TMS, TDI, TRSTN, TDO. These pins do not go to STAB
STAB Module: ti_io

Module: ti_stab

{Enable}
s2b_tm_gz_{SIGNAME}
{FromCore}
s2b_tm_a_{SIGNAME}
Module: ti_padbsr
Output
bc_io_it bsc_bc_io_it_{SIGNAME} {cellname} pad_{SIGNAME}
b2p_gz_{SIGNAL}
TM_GZ PO_GZ GZ
TM_A PO_A b2p_a_{SIGNAL}
{ToCore} A PAD
PO_Y p2b_y_{SIGNAL}
{Enable} PI_Y Y
PI_GZ
{FromCore}
PI_A
t2io_shift_dr shift_dr
SDR
t2io_clock_dr clock_dr
t2io_update_dr update_dr
CDR
UDR
test_mode
TM
tm_or_mode1
TM_MODE1
t2io_mode2 mode2
MODE2
t2io_mode3 mode3
MODE3
bsr_so_{n}
bsr_so_{n+1} SI SO
t2io_tck
TCK
Efuse Overview
Fuse ROM
TI’s top-level test
control block (TITAN)

SRAM
fdi fclk
fclrz
fclrz
fclk 1 1
JTAG fdi fdo
Fuse
Controller

Fuse ROM
Autoload

fdi SRAM
fclk

fclrz

fdi 1 1 fdo

Shadow registers for 32-bit trace ID

1 1
1 1 1 1
IPs needing trimming
(ex. Serdes)
JTAG 32-bit bus for
customer CPU
TAP access
available after autoload
Titan/ION
• Early in design Cisco will run ION to create non-DFT Top
Level netlist(“F-number”) netlist
– And map to design core netlist
– Ensures proper population of IO information

• Then TI will Create golden top level netlist

– RTL and Gate F-Number netlist will be provided
– Titan/IO/BSCAN and STAB modules created and instantiated in F-
Number netlist along with the core
• Core Naming Convention is key
– Inputs t2c_<subchip_ID>_<signal_name>
– Outputs c2t_<subchip_ID>_<signal_name>