Ex. No.

5a Date:
IMPLEMENTATION OF RIPPLE COUNTERS
Aim: a) To write a Verilog HDL to model a 4-bit ripple up counter using positive edge
triggered T-Flipflop with asynchronous reset and generate post map and post place
and route simulation result.
b) To write a Verilog HDL to model a 4-bit ripple down counter using positive edge
triggered T-Flipflop with asynchronous reset generate post map and post place and
route simulation result.
Software Requirements:
i) Xilinx ISE 14.7
ii)ISim Simulator

Theory:
Counters can be implemented using the adder/subtractor circuits and registers.
Asynchronous Counters:
The simplest counter circuits can be built using T flip-flops because the toggle feature is
naturally suited for the implementation of the counting operation.
Asynchronous Up-Counter with T Flip-Flops
Figure shows a 3-bit counter capable of counting from 0 to 7. The clock inputs of the three
flip-flops are connected in cascade. The T input of each flip-flop is connected to a constant 1,
which means that the state of the flip-flop will be toggled at each active edge (here, it is
positive edge) of its clock. We assume that the purpose of this circuit is to count the number
of pulses that occur on the primary input called Clock. Thus the clock input of the first flip-
flop is connected to the Clock line. The other two flip-flops have their clock inputs driven by
the Q output of the preceding flip-flop. Therefore, they toggle their states whenever the
preceding flip-flop changes its state from Q =1 to Q = 0, which results in a positive edge of
the Q signal.
 A 3−bit up−counter
Figure shows an example timing diagram for the counter. The value of Q 0 toggles once every
clock cycle. The change takes place shortly after the positive edge of the Clock signal. The
delay is caused by the propagation delay through the flip-flop (in any realistic circuit, there
will always be such a delay). Since the second flip-flop is clocked by Q 0, the value of Q1
changes shortly after the negative edge of the Q0 signal. Similarly, the value of Q2 changes
shortly after the negative edge of the Q1 signal. This circuit is a modulo-8 counter. Because it
counts in the upward direction, we call it an up-counter. The counter in Figure 1 has three
stages, each comprising a single flip-flop. Only the first stage responds directly to the Clock
signal; we say that this stage is synchronized to the clock. The other two stages responds after
an additional delay. For example, when Count = 3, the next clock pulse will cause the Count
to go to 4. As indicated by the arrows in Figure, this change requires the toggling of the states
of all three flip-flops (here the arrows indicate the causal relationship among them). Since
from each stage to the next, the toggling of the states introduces an addition delay, The
overall delay of the circuit will be the sum of all the delays. This behaviour is similar to the
rippling of carries in a ripple-carry adder. The circuit is therefore called an asynchronous
counter, or a ripple counter.
.
 Timing diagram for a 3−bit up−counter.
Asynchronous Down Counter:
Some modifications of the circuit in Figure lead to a down-counter which counts in the
sequence 0, 7, 6, 5, 4, 3, 2, 1, 0, 7, and so on. The modified circuit is shown in Figure. Here
the clock inputs of the second and third flip-flops are driven by the Q outputs of the
preceding stages, rather than by the Q outputs. Figure shows an example timing diagram of
such a down-counter.

A 3−bit down−counter

Timing Diagram for a 3-bit down counter

Program:
Ripple up counter
module ripplecount(
input t,
input clk,
input r,
output [2:0] q
);
tff f1 (clk,r,t,q[0]);
tff f2 (~q[0],r,t,q[1]);
tff f3 (~q[1],r,t,q[2]);
endmodule

Output:

Ripple down counter

module rippledowncount(
input t,
input clk,
input r,
output [2:0] q
);
tff f1(clk,r,t,q[0]);
tff f2(q[0],r,t,q[1]);
tff f3(q[1],r,t,q[2]);
endmodule
Output:

Procedure:
i) Open Xilinx ISE 14.7 Project Navigator
ii) Create a New Project in the desired location with top level source type as HDL
iii)Device Properties window opens
Select Family - Spartan6
Device : XC6SLX9
Package : CSG324
Simulator : ISim (VHDL / Verilog)
Preferred Language : Verilog
iv)Create New Source File
v) Select Verilog module with a preferred file name.
vi)Click Next
vii) Click Finish

Result: Thus a 4-bit ripple up and 4-bit ripple down counter was designed using T-flipflops
and its functionality was verified.
Ex. No. 5b Date:
IMPLEMENTATION OF A SWITCH DEBOUNCER CIRCUIT
Aim: To design a switch debouncer circuit for the activation period of 10ms.
Software Requirements:
i) Xilinx ISE 14.7
ii)ISim Simulator
Theory:
Using mechanical switches for a user interface is a ubiquitous practice.  However, when these
switches are actuated, the contacts often rebound, or bounce, off one another before settling
into a stable state.  The debounce component presented here is a simple digital logic circuit
that addresses this temporary ambiguity (a common task when interfacing FPGAs or CPLDs
with pushbuttons or other switches).  Figure 1 illustrates a typical example of this Debounce
component integrated into a system.  

Figure 1. Debouncer Circuit

Debouncing a switch in software is very simple. The basic idea is to sample the switch signal
at a regular interval and filter out any glitches. There are a couple of approaches to achieving
this listed below. Both approaches assume a switch circuit like that shown in the explanation
of switch bounce: a simple push switch with a pull-up resistor.
Sizing the Counter
The size of the counter and the clock frequency together determine the time period P that
validates the button’s stability. 

  
Program:
module switch_debouncer(
input inswitch,
input clk,
output outswitch
);
reg[17:0] count = 18'b0;
reg state = 1'b0;
always@(posedge clk)
begin
if(inswitch!=state && count<250000)
count<=count+18'b1;
else if(count==250000)
begin
state<=inswitch;
count<=18'b0;
end
else
count<=18'b0;
end
assign outswitch = state;
endmodule

Output:
Procedure:
i) Open Xilinx ISE 14.7 Project Navigator
ii) Create a New Project in the desired location with top level source type as HDL
iii)Device Properties window opens
Select Family - Spartan6
Device : XC6SLX9
Package : CSG324
Simulator : ISim (VHDL / Verilog)
Preferred Language : Verilog
iv)Create New Source File
v) Select Verilog module with a preferred file name.
vi)Click Next
vii) Click Finish

Design Summary:

Result : Thus a switch debouncer circuit was designed for the specified activation period.
Ex. No. 6a Date:
IMPLEMENTATION OF RIPPLE CARRY ADDER
Aim: To write a Verilog HDL to model a 4-bit ripple carry adder using generate statement.
Software Requirements:
i) Xilinx ISE 14.7
ii)ISim Simulator
Theory:
Arithmetic operations like addition, subtraction, multiplication, division are basic operations
to be implemented in digital computers using basic gates like AND, OR, NOR, NAND etc.
Among all the arithmetic operations if we can implement addition then it is easy to perform
multiplication (by repeated addition), subtraction (by negating one operand) or division
(repeated subtraction).
 Half Adders can be used to add two one bit binary numbers. It is also possible to create a
logical circuit using multiple full adders to add N-bit binary numbers. Each full adder inputs a
Cin, which is the Cout of the previous adder. This kind of adder is a Ripple Carry Adder,
since each carry bit "ripples" to the next full adder. The first (and only the first) full adder
may be replaced by a half adder.The block diagram of 4-bit Ripple Carry Adder is shown
here below -
 

 The layout of ripple carry adder is simple, which allows for fast design time; however, the
ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be
calculated from the previous full adder. The gate delay can easily be calculated by inspection
of the full adder circuit. Each full adder requires three levels of logic.In a 32-bit [ripple carry]
adder, there are 32 full adders, so the critical path (worst case) delay is 31 * 2(for carry
propagation) + 3(for sum) = 65 gate delays.
Program:
module rippleca(
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] s,
output cout
);
wire [4:0]c;
genvar i;
assign c[0]=cin;
generate for(i=0;i<=3;i=i+1)
begin:loop
Fulladd f1(a[i],b[i],c[i],s[i],c[i+1]);
end
assign cout = c[4];
endgenerate

endmodule

Output:
Design Summary:

Procedure:
i) Open Xilinx ISE 14.7 Project Navigator
ii) Create a New Project in the desired location with top level source type as HDL
iii)Device Properties window opens
Select Family - Spartan6
Device : XC6SLX9
Package : CSG324
Simulator : ISim (VHDL / Verilog)
Preferred Language : Verilog
iv)Create New Source File
v) Select Verilog module with a preferred file name.
vi)Click Next
vii) Click Finish

Result: Thus a 4-bit ripple carry adder was designed using generate statement and its
functionality was verified.
Ex. No. 6b Date:
IMPLEMENTATION OF ADDER / SUBTRACTOR
Aim: To write a Verilog HDL to model an 8-bit adder/subtractor which switches
dynamically between addition and subtraction based on add/sub control signal.
Software Requirements:
i) Xilinx ISE 14.7
ii)ISim Simulator
Theory:
Parallel Adders
Even the full adder is only adding two single bit binary numbers, but full adders may be
combined to form parallel adders, which will add two multi−bit numbers. Parallel adders can
be built in several forms to add multi−bit binary numbers, each bit of the parallel adder using
a single full adder circuit. As parallel adder circuits would look quite complex if drawn
showing all the individual gates, it is common to replace the full adder schematic diagram
with a simplified block diagram version.
4 Bit Parallel Adder
A number of full adders can be combined to make a parallel adder, also called a ‘Ripple
Carry Adder’ because of the way that any carry appearing at the carry in input (CIN) or
produced when adding any of the 4-bit inputs, ‘ripples’ along the adder stages until a final
carry out appears at the carry out output (COUT) of the final full adder for bit A3+B3.
8 Bit Twos Complement Adder/Subtractor
To carry out arithmetic however, it is also necessary to be able to subtract. A further
development of the parallel adder is shown in Figure. This is a 4-bit parallel adder/subtractor.
This circuit adds in the same way as a ripple carry adder but subtracts using the twos
complement method based on the select line.
An 8-bit parallel adder/subtractor is shown in figure. When subtraction is required, the
control input is set to logic 1, which causes the bit at any particular B input to be
complemented by an XOR gate before being fed to input B of the full adder circuit.
Twos complement subtraction in an 8-bit adder/subtractor requires that the 8-bit number at
input B is complemented (inverted) and has 1 added to it, before being added to the 8-bit
number at input A. The result of this will be an 8-bit number in twos complement format, i.e.
with its value represented by the lower 7 bits (bit 0 to bit 6) and the sign represented by the
most significant bit (bit 7). The logic 1 on the control input is therefore also fed to the first
carry input of the adder to be included in the addition, which for subtraction is therefore:
A+ B́+1. (Here + signifies addition rather than OR)

Alternatively, if addition of A and B is required, then the control input is at logic 0 and
number B is fed to the adder without complementing.
Adder/Subtractor Control

XOR Gate Used as a Data Selector.

An XOR gate is used here to change the adder into a subtractor by inverting the B inputs can
be seen from the truth table of an XOR gate as shown in the above Table. If input A, (used as
the CONTROL input) of the XOR gate is at logic 0, then the XOR gate selects input B, but if
input A is logic 1, then it selects the inverse of input B (i.e. B).

Program:
module addsub(
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] s,
output cout
);
wire [8:0]c;
wire [7:0]x;
genvar i;
assign c[0]=cin;
generate for(i=0;i<=7;i=i+1)
begin:loop
xor(x[i],b[i],cin);
Fulladd f1(a[i],x[i],c[i],s[i],c[i+1]);
end
assign cout=c[7];
endgenerate
endmodule
Output:

Design Summary:
Top Level Output File Name : addsub.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 12
# LUT2 :1
# LUT4 :4
# LUT5 :2
# LUT6 :5
# IO Buffers : 26
# IBUF : 17
# OBUF :9
Device utilization summary:
---------------------------
Selected Device : 6slx9csg324-3
Slice Logic Utilization:
Number of Slice LUTs: 12 out of 5720 0%
Number used as Logic: 12 out of 5720 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 12
Number with an unused Flip Flop: 12 out of 12 100%
Number with an unused LUT: 0 out of 12 0%
 Number of fully used LUT-FF pairs: 0 out of 12 0%
Number of unique control sets: 0
IO Utilization:
Number of IOs: 26
Number of bonded IOBs: 26 out of 200 13%
Specific Feature Utilization:
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
==================================================================
=======
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 8.917ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
==================================================================
=======
Timing constraint: Default path analysis
Total number of paths / destination ports: 109 / 9
-------------------------------------------------------------------------
Delay: 8.917ns (Levels of Logic = 6)
Source: cin (PAD)
Destination: s<7> (PAD)
Data Path: cin to s<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.222 1.227 cin_IBUF (cin_IBUF)
LUT5:I0->O 3 0.203 0.755 loop[1].f1/cout1 (c<2>)
LUT6:I4->O 3 0.203 0.755 loop[3].f1/cout1 (c<4>)
LUT6:I4->O 3 0.203 0.995 loop[5].f1/cout1 (c<6>)
LUT6:I1->O 1 0.203 0.579 loop[7].f1/Mxor_s_xo<0>1 (s_7_OBUF)
OBUF:I->O 2.571 s_7_OBUF (s<7>)
----------------------------------------
Total 8.917ns (4.605ns logic, 4.312ns route)
(51.6% logic, 48.4% route)
==================================================================
=======
Cross Clock Domains Report:
-------------------------
==================================================================
=======
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.29 secs
-->
Total memory usage is 4486116 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)
Number of infos : 1 ( 0 filtered)

Procedure:
i) Open Xilinx ISE 14.7 Project Navigator
ii) Create a New Project in the desired location with top level source type as HDL
iii)Device Properties window opens
Select Family - Spartan6
Device : XC6SLX9
Package : CSG324
Simulator : ISim (VHDL / Verilog)
Preferred Language : Verilog
iv)Create New Source File
v) Select Verilog module with a preferred file name.
vi)Click Next
vii) Click Finish

Result:
Thus an 8-bit adder/subtractor was designed using the add/sub control line and its
functionality was verified.