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  • VDNL 9

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    gayathri
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    vdnl 9

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    7 views4 pages

    VDNL 9

    Uploaded by

    gayathri

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    module seqdetetct(

    input clk,
    input reset,
    input x,
    output reg yout,
    reg y
    );
    parameter s0 = 2'b00;
    parameter s1 = 2'b01;
    parameter s2 = 2'b10;
    parameter s3 = 2'b11;
    reg [1:0] p_s;
    reg [1:0] n_s;
    always@(posedge clk,posedge reset)
    begin
    if(reset)
    begin
    p_s<=s0;
    yout<=1'b0;
    end
    else
    begin
    p_s<=n_s;
    yout<=y;
    end
    end
    always@(p_s,x)
    begin
    case(p_s)
    s0:if(x)
    begin
    n_s<=s0;
    y<=1'b0;
    end
    else
    begin
    n_s<=s1;
    y<=1'b0;
    end
    s1:if(x)
    begin
    n_s<=s2;
    y<=1'b0;
    end
    else
    begin
    n_s<=s1;
    y<=1'b0;
    end
    s2:if(x)
    begin
    n_s<=s0;
    y<=1'b0;
    end
    else
    begin
    n_s<=s3;
    y<=1'b0;
    end
    s3:if(x)
    begin
    n_s<=s2;
    y<=1'b1;
    end
    else
    begin
    n_s<=s1;
    y<=1'b0;
    end
    endcase
    end
    endmodule
    --
    test fixture:
    initial begin
    reset = 1'b1;
    clk = 1'b0;
    #20 reset = 1'b0;
    #20 x=1'b0;
    #20 x=1'b1;
    #20 x=1'b0;
    #20 x=1'b1;
    #20 x=1'b0;
    #20 x=1'b0;
    #20 x=1'b1;
    #20 x=1'b0;
    #20 x=1'b1;
    #20 x=1'b0;
    #20 x=1'b1;
    #20 x=1'b0;
    end
    always
    begin
    #10 clk = ~clk;
    end
    endmodule
    ---------------
    vending machine:

    module vending(
    input clk,
    input reset,
    input x,
    output reg yout,
    reg y
    );
    parameter s0 = 2'b00;
    parameter s1 = 2'b01;
    parameter s2 = 2'b10;
    parameter s3 = 2'b11;
    reg [1:0] p_s;
    reg [1:0] n_s;
    always@(posedge clk,posedge reset)
    begin
    if(reset)
    begin
    p_s<=s0;
    yout=1'b0;
    end
    else
    begin
    p_s<=n_s;
    yout=y;
    end
    end
    always@(p_s,x)
    begin
    case(p_s)
    s0:if(x)
    begin
    n_s<=s2;
    y=1'b0;
    end
    else if(x==0)
    begin
    n_s<=s1;
    y=1'b0;
    end
    else
    begin
    n_s<=s0;
    y=1'b0;
    end
    s1:if(x)
    begin
    n_s<=s3;
    y=1'b1;
    end
    else if(x==0)
    begin
    n_s<=s2;
    y=1'b0;
    end
    else
    begin
    n_s<=s1;
    y=1'b0;
    end
    s2:if(x)
    begin
    n_s<=s3;
    y=1'b1;
    end
    else if(x==0)
    begin
    n_s<=s3;
    y=1'b1;
    end
    else
    begin
    n_s<=s2;
    y=1'b0;
    end
    s3:n_s<=s0;
    endcase
    end
    endmodule
    ---
    test fixture:
    initial begin
    // Initialize Inputs

    reset = 1'b1;
    clk = 1'b0;
    #20 reset = 1'b0;
    #40 x=1'b0;
    #40 x=1'b1;
    #40 x=1'b0;
    #40 x=1'b0;
    #40 x=1'b0;
    #40 x=1'b1;

    end
    always
    begin
    #10 clk = ~clk;
    end
    endmodule

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