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CPS213
Computer Organization I
Winter 2021
© Ali Miri

The course slides will contain materials and figures from the textbook and slide sets by Dr.
Sadeghian. They are used with permission. We also have used figures from the web that
were ``labeled for reuse with modification'' copyright permissions. When copyright status
have been unclear, best attempts have been made to include the source.
Electronic devices:
• Process information
• Store, retain, and retrieve information

• Need memory components

Sequential Circuits:
Act as storage elements and have memory
Figure 5.1
Block diagram of sequential circuit.

State: Binary information stored in memory elements at any given time

Types of Sequential Circuits

Synchronous sequential circuit:

• Signals affect storage elements at only discrete instants of time
• Typically need a clock

Asynchronous sequential circuit:

• Behavior depends upon the input signals at any instant of time
and the order in which the inputs change
Figure 5.2
Synchronous clocked sequential circuit.
Synchronous Sequential Circuits

• Signals affect storage elements at only discrete instants of time

• Achieved by a timing device: clock generator
• Clock pulses (periodic sequence)

Two types of inputs:

• CLK : when
• Inputs: What

Too fast of a clock?

• Need a minimum interval between clock pules
Types of Storage Elements

When to change the value in a storage element?

When a different value When the next clock

arrives, i.e. signal level pulse arrives

Latches Flip-Flops

Suitable for asynchronous Suitable for synchronous

Understanding NOR - reminder

X Y F X Y F
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 0 1 1 0

When one of the inputs is 1 When one of the inputs is 0

The output is 0 The output is
the complement of the
other input
Figure 5.3
S R Q t+1 Q’t+1 Description
SR latch with NOR gates
Active High SR 0 0 Qt Q’t No Change
0 1 0 1 Reset
1 0 1 0 Set
1 1 0 0 Not Defined

S=0, R=0 à no change

[no set & no reset à No change]
S=0, R=1 à Reset
[no set & reset à Reset]
S=1, R=0 à Set
[set & no reset à Set]
S=1, R=1 à Not defined
[set & reset à Not defined]

Use definition of NOR to understand the table

Qt è Present Q
Q t+1 è Next Q
Figure 5.3
SR latch with NOR gates.

INPUTS CURRENT NEXT

STATE STATE

S R Qt Q t+1
0 0 0 0
No
0 0 1 1 change

0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 0
Not
1 1 1 0 defined
Understanding NAND

X Y F X Y F
0 0 1 0 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 1 1 0
When one of the inputs is 1 When one of the inputs is 0
the output is The output is 1
the complement of
the other input
Figure 5.4
S R Q t+1 Q’t+1 Description
SR latch with NAND gates
Active Low SR 0 0 1 1 Not Defined
0 1 1 0 Set
1 0 0 1 Reset
1 1 Qt Q’t No Change

S=0, R=0 à Not defined

[set & reset à Not defined]
S=0, R=1 à Set
[set & no reset à Set]
S=1, R=0 à Reset
[no set & reset à Reset]
S=1, R=1 à No change
[no set & no reset à No change]
Use definition of NAND to understand the table
Qt è Present Q
Qt+1 è Next Q
Figure 5.4
SR latch with NAND gates.

INPUTS CURRENT NEXT

STATE STATE

S R Qt Q t+1
0 0 0 1
Not
Defined 0 0 1 1
0 1 0 1
Set
0 1 1 1
1 0 0 0
Reset
1 0 1 0
1 1 0 0
No
Change 1 1 1 1
SR latch with NOR gates

INPUTS CURRENT NEXT

STATE STATE In order to decide what
the next states (Q t+1) are
we need to know:

- the inputs (S, R) and

- the current state (Q t)
Figure 5.5
SR latch with control input.

❶
❸

❷ ❹

How does NAND work?

One of the inputs is Zero à Output is 1
One of the inputs is One à Output is the complement of the 2nd input
Figure 5.5
SR latch with control input.
One of the inputs is Zero à NAND output is 1
One of the inputs is One à NAND output is the complement of the 2nd input

❶
❸

❷ ❹

En is 0, S= X, R= X à output of the 1st NAND is 1

output of the 2nd NAND is 1

NAND 3 and 4 are working as Active Low SR Latch.

Therefore, both having both inputs as 1, that is, No Change.
Figure 5.5
SR latch with control input.
One of the inputs is Zero à NAND output is 1
One of the inputs is One à NAND output is the complement of the 2nd input

❶
❸

❷ ❹

En is 1, S=0, R=0 à output of the 1st NAND is S’, ie, 1

output of the 2nd NAND is R’, ie, 1

NAND 3 and 4 are working as Active Low SR Latch.

Therefore, both having both inputs as 1, that is, No Change.
Figure 5.5
SR latch with control input.
One of the inputs is Zero à NAND output is 1
One of the inputs is One à NAND output is the complement of the 2nd input

❶
❸

❷ ❹

En is 1, S=0, R=1 à output of the 1st NAND is S’, ie, 1

output of the 2nd NAND is R’, ie, 0

NAND 3 and 4 are working as Active Low SR Latch.

Therefore, Reset.
Figure 5.5
SR latch with control input.
One of the inputs is Zero à NAND output is 1
One of the inputs is One à NAND output is the complement of the 2nd input

❶
❸

❷ ❹

En is 1, S=1, R=0 à output of the 1st NAND is S’, ie, 0

output of the 2nd NAND is R’, ie, 1

NAND 3 and 4 are working as Active Low SR Latch.

Therefore, Set.
Figure 5.5
SR latch with control input.
One of the inputs is Zero à NAND output is 1
One of the inputs is One à NAND output is the complement of the 2nd input

❶
❸

❷ ❹

En is 1, S=1, R=1 à output of the 1st NAND is S’, ie, 0

output of the 2nd NAND is R’, ie, 0

NAND 3 and 4 are working as Active Low SR Latch.

Therefore, Not Defined.
Figure 5.7
Graphic symbols for latches.

Active High SR Active Low SR D Latch

Latch Latch
Figure 5.6
D latch.

S
❶
❸

❹
❷
R

How does NAND work?

One of the inputs is Zero à Output is 1
One of the inputs is One à Output is the complement of the 2nd input
DFF – Data Flip Flop

D Qt Q t+1
0 0 0
0 1 0
1 0 1
1 1 1

After the clock, D will go D Q t+1

through and Q becomes D 0 0
1 1