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CPS213
Computer Organization I
Winter 2021
© Ali Miri

The course slides will contain materials and figures from the textbook and slide sets by Dr.
Sadeghian. They are used with permission. We also have used figures from the web that
were ``labeled for reuse with modification'' copyright permissions. When copyright status
have been unclear, best attempts have been made to include the source.
SR Latches
SR Latches with control input
D Latches (Transparent Latches)
Clock Response in Latches and Flip-Flops
Building Flip-Flops Using D-Latches

Q. Can we simply replace the control input with a clock?

- May result in an unpredictable situation

Two possible solutions:

1. Use two latches in a configuration that isolates the output of
the flip-flop and prevents it from being affected while the input to
the flip-flop is changing

2. Trigger only during a clock signal transition (0 to 1, or 1 to 0), but

Otherwise disable the flip-flop during the rest of the clock pulse.
Negative Edge-Triggered D Flip-Flop
Positive Edge-Triggered D Flip-Flop
Graphic symbols for edge-triggered D flip-flops
Operations of flip-flops

• Set the output to 1

• Reset the output to 0
• Complement the output value
Figure 5.12
JK flip-flop.

jJ K Qt Q t+1
0 0 Qt Qt
0 1 Qt 0
1 0 Qt 1
1 1 Qt Q’t
JKFF
J K Q t+1
0 0 Qt No change/Hold
0 1 0 Reset
1 0 1 Set
1 1 Q’ t Toggle
TFF – Toggle Flip Flop

T Q t+1
0 Qt No Change/Hold
1 Q’ t Toggle
Figure 5.13
T flip-flop.

Building a TFF using Building a TFF using

a JKFF a DFF
Table 5.1
Flip-Flop Characteristic Tables.
Direct Inputs Flip-Flops
Direct Inputs Flip-Flops
State Equations

State equations: expressing the behaviour of a clocked sequential circuit

State Equations - example
State Table
State Diagram
Example 1
Example 2
Example 2
Example 2
Example 2