Unit 5

Sequential & Combinational

Logic

Flip-Flops & Latches

ADDERS
 Inputs Outputs
Combina
 A Sequential -tional
circuit contains: Storage
Logic
◦ Storage elements: Elements
Latches or Flip-Flops Next
◦ Combinational Logic: State State
 Implements a multiple-output
switching function
 Inputs are signals from the outside.
 Outputs are signals to the outside.
 Other inputs, State or Present State, are
signals from storage elements.
 The remaining outputs, Next State are
inputs to storage elements.
 Inputs Outputs
Combina
-tional
Storage
Logic
Elements
 Combinatorial Logic Next
◦ Next state function State State
Next State = f(Inputs, State)
◦ Output function (Mealy)
Outputs = g(Inputs, State)
◦ Output function (Moore)
Outputs = h(State)
 Output function type depends on specification and affects
the design significantly

Chapter 6 - Part 1 3
Inputs .
Combinational
. Outputs
. .
Logic Gates

Memory
Elements
(Flip-Flops)
Clock
 Memory storage elements
◦ Latches
◦ Flip-flops
  The two most popular varieties of storage cells
used to build sequential circuits are: latches
and flip-flops.

◦ Latch: level sensitive storage element

◦ Flip-Flop: edge triggered storage element

 In a conventional “Digital Logic” flip-flop

designs using “cross-coupled” logic
gates
 The primary difference between a flip-flop
and latch is the EN/CLOCK input.
 The flip-flop’s CLOCK input is edge
sensitive, meaning the flip-flop’s output
changes on the edge (rising or falling) of
the CLOCK input.
 The latch’s EN input is level sensitive,
meaning the latch’s output changes on the
level (high or low) of the EN input.
 Common examples of latches:
S-R latch, D latch

 Common examples of flip-flops:

R-S FF,
D-FF
JK-FF
T-FF
 Can be constructed from 2 NAND gates or 2
NOR gates

 Cross coupled connection from o/p of one

gate to the i/p of other gate constitutes a
Feedback path

 Each FF has 2 o/ps: Q & Q’; 2 i/ps set & reset

 Cross-coupled NOR gates
◦ Can set (S=1, R=0) or reset (R=1, S=0) the output

S R Q
R Q 0 0 hold
Reset R Q 0 1 0
Set S Q 1 0 1
S Q' 1 1 disallow

10
The o/p of NOR gate is 0, if any
i/p is 1 & o/p is 1, only when all R
Q
i/ps are 0.

In the RS FF
Q
 At starting point, set i/p is 1 &
S

reset is 0
 When a 1 is applied to both set S R Q Q’
& reset i/ps, both Q & Q’ o/ps 1 0 1 0

leads to 0 0 0 1 0
0 1 0 1
0 0 0 1
1 1 0 0
NAND basic FF circuit
operates with both i/ps at 1
S
Q

unless the state of FF has to

be changed Q
R
 0 to the set i/p causes
o/p Q to 1 & Q’to 0, FF in
set state S R
1 0
Q Q’
0 1

 set i/p returns to 1, 0 to

1 1 0 1
0 1 1 0
reset i/p cause to the 1 1 1 0
1 1
clear state
0 0
 S
Q

CLK

Q
R

CLK SR Q
0 XX No change
1 00 No change
1 01 0
1 10 1
1 11 Undefined
 D CLK Q Q
D Q 0  0 1

1  1 0
CLK Q
 : Rising Edge of Clock

15
D Flip-Flop Circuit
D
Q

CLK

 It is the modification of the clocked RS

FF.
 The basic FF NAND gates modified into a
clocked RS FF & D i/p is complimented.
 J Q

CLK

Q
It is the refinement of RS FF.
K


 The i/ps J & K behaves like i/ps S & R

respectively.

 o/p Q is ANDed with K and clock i/ps,

cleared only if Q was previously 1.

 |||ly Q’ is ANDed with J and clock, FF set

with clock pulse only if Q’was previously
1.
 JK Flip-Flop Circuit
Q J K Q (t+1)
0 0 0 0
K 0 0 1 0
Q 0 1 0 1
0 1 1 1
CLK 1 0 0 1
1 0 1 0
Q 1 1 0 1
J 1 1 1 0
 Output toggles when input is asserted
◦ If T=1, then Q → Q' when CLK 
◦ If T=0, then Q → Q when CLK 

Input Q Input(t) Q(t) Q(t + 1)

T Q
0 0 0
> 0 1 1
1 0 1
CLK 1 1 0
 It is the single i/p version of JK FF

 T FF is obtained from a JK FF, if both

i/ps are tied together.

 Regardless of the present state, it

assume the complement state when the
CLK occurs while i/p T is 1.
T Flip-Flop Circuit

T
Q

CLK

Q
 Construction of Flip Flop

 There are two general methodologies for making

flip-flops
◦ Edge-triggered
◦ Master-Slave

 The state of a FF is switched by a momentary

change in the i/p signal.

 This momentary change is called a trigger and

the transition it causes is trigger the FF.
 Clocked FFs are triggered by pulses.

 A pulse starts from an initial value of 0, goes

momentarily to 1, after a short time returns to its
initial 0 value.

 The time interval from the application of the

pulse until the o/p transition occurs is a critical
factor.
 When the control input to a flip-flop changes
value, the state of the latch in the flip-flop will
change state.
 In a latch when the control input is a ‘1’, any
changes on the input will propagate to the
output with the value of i/p at the time the
control transitions from ‘1’ the final stored
value.

 In a flip-flop, the value on i/p on the rising edge

(falling edge) of the control input will be the
captured value.
Positive Edge Transition

Positive Pulse
1

0
+ve Edge -ve Edge

0
-ve Edge +ve Edge

Negative Edge Transition Negative Pulse

Edge-Triggered Flip-Flop

 It synchronizes the state changes

during clock pulse transition

 The o/p transition occur at a specific

level of the clock pulse.
 It is constructed from 2 separate FFs : One circuit
serve as master and the other as a slave

 This arrangement is also negative edge triggered.

 The purpose of the Master-Slave is to overcome

from “Race-around condition”
◦ Repetition of toggle for a single clock pulse in the input
of J-K FF is known as the Race-around condition

◦ The Race-around condition will occur when J=K=1 and

the time period of the clock pulse is greater than the
propagation delay of FF
 Consists of two clocked
S-R latches in series S S Q S Q Q
with the clock on the C C C
second latch inverted R R Q R Q Q

 The input is observed

by the first latch when C = 1

 The output is changed by the second latch with C = 0

 The path from input to output is broken by the

difference in clocking values (C = 1 and C = 0).

 Only one latch is transparent at any time. Feedback path is

blocked
 Master-Slave J-K Flip-Flop
• The master slave JK flip flop is a combination of a
clocked JK latch and a clocked SR latch. The clocked JK
latch acts as the master and the clocked SR latch acts as
the slave.
• Master is positive level triggered and due to the
presence of an inverter in the clock line, the slave is
negative level edge triggered. Hence when clock=1, the
master is active and slave is inactive. Vice versa happens
when clock=0.
 Master-Slave J-K Flip-Flop
Case I: When clock is not given, both master and slave are
inactive and there will be no change in outputs.
Case II: For clock=1, master is active, slave inactive. As
J=K=0, output of master ie Q and Q' will not change. As
soon as clock goes to 0, slave becomes active, and master
inactive. But since input to slave S and R is same, output of
slave will also remain same.
Case III: For clock=1, master is active and slave is inactive.
When J=0 and K=1, outputs of master will be Q=0, Q'=1,
which will be inputs to slave. When clock=0, slave becomes
active and takes inputs 0,1 to give output Q=0, Q'=1. This
output will not change if clock is again made 1and then 0.
Hence we get a stable output from master and slave.
 Master-Slave J-K Flip-Flop
Case IV: For clock=1, master is active and slave is inactive.
When J=1 and K=0, outputs of master will be Q=1, Q'=0,
which will be inputs to slave. When clock=0, slave becomes
active and takes inputs 1,0 to give output Q=1, Q'=0. This
output will not change if clock is again made 1 and then 0.
Hence we get a stable output from master and slave.
Case V: When clock =1, J=K=1, master output will toggle.
So S and R will invert. But slave remains inactive all this time
since clock is 1. As soon as clock becomes 0, slave becomes
active and master becomes inactive. So slave will also
toggle. These changed outputs are returned through
feedback to the master, but master does not respond to
them because clock is now 0 and master is inactive. Thus,
in one clock period, master and slave both toggle only
once, avoiding race condition caused by multiple toggling.
Combinational Circuits

ADDERS
 INPUTS OUTPUTS

A B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0
INPUTS OUTPUTS  Notice the C column
(carry line) from the
A B C S truth table?
Recognize it? It’s an
0 0 0 0
AND!:
0 1 0 1 C=A•B

1 0 0 1

1 1 1 0
  S is high if one and
INPUTS OUTPUTS exactly one input is
high …
A B C S

0 0 0 0  What expression can

we use to prove this
0 1 0 1 statement?
S = (~A • B) + (A •~B)
1 0 0 1

1 1 1 0  It is Exclusive OR. It is
usually labeled XOR
  The XOR circuit delivers
INPUTS OUTPUTS the Sum Line (S) of adding
two single digits.
Q R
A B  The AND circuit produces
A•B A + B the Carry Line (C).
0 0 0 0  A fundamental circuit
0 1 0 1 called a Half Adder,
which provides the
1 0 0 1 capability of adding two
single bit numbers.
1 1 1 0
 Half Adder
A B
A
Sum
B
S
Half
Adder
C
Carry

A B S(um) C(arry)

0 0 0 0
0 1 1 0 S = AB + A B = A  B
1 0 1 0 C = AB
1 1 0 1
 to add 3 single digit numbers by stringing together
two half-adders:

◦ We need 3 input lines, one for each number.

◦ Two input lines feed into the first half adder; the third
input line functions as a carry-in line.

◦ The second half-adder has two input lines: the output

sum from the first half-adder, plus the third, carry-in
input line.
 INPUTS OUTPUTS
A B CIN CCARRY SSUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
 The patterns between the output lines and the
input lines:

 In the truth table, CCARRY output line is true if and

only if exactly two or three input lines are high.

 The SSUM output line is high when the XOR of A

and (the sum of Input B and CIN) is high?

 In other words, add the Input B and CIN values

together, putting them through a half adder. Take
the result, and XOR it with the value of the A input
line. The result is the value for the SSUM output line
 Cin A B S(um) Cout
0 0 0 0 0
0 0 1 1 0
A B 0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
S
Carry In Full 1 0 1 0 1
(Cin) Adder 1 1 0 0 1
Cout
1 1 1 1 1

S = Cin  A  B
Cout = AB + Cin(A  B)
 3 single digit binary numbers can be added by
connecting two half-adders together

S = Cin  A  B
Cout = AB + Cin(A  B)

A S
A S A S
Half Half
Adder Adder
B B C B C Cout

Cin
S = Cin  A  B
Cout = AB + Cin(A  B)
H.A. H.A.
A

B S

Cin

Cout