HCMC University of Technology and Education

Faculty of Electrical & Electronic Engineering

Lecture:
DIGITAL SYSTEMS
Chapter 4:
Flip_Flops and Related Devices

Nguyen Thanh Hai, PhD

1
University of Technology and Education
Faculty of Electrical & Electronic Engineering
Contents
1 NAND Gate Latch
2 NOR Gate Latch
3 Clock signals
4 Clocked S-R Flip-Flop
5 Clocked J-K Flip-Flop
6 Clocked D Flip-Flop
7 D Latch
8 T Latch
9 Asynchronous Input
10Flip-Flop Synchronization
11 Data Storage Transfer
12Serial Data Transfer
13Analyzing Sequential Circuit
14Clock Generator Circuits 2
Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering

NAND Gate Latch Input Output This latch circuit

S R Qn+1 has 2 inputs and
S 1 (Set) (Reset) 2 outputs only, in
0 1 1 which the 2
1 0 0 outputs are
1 1 Qn inverting Q and Q
No change . It means that if
R 2
Forbidden Q=1/0,
Q  0 /1
0 0

State-1: inputs S=0, R=1, at NAND-1, output Q=1, at inputs of NAND-2,

R=Q=1, output Q (inverting)=0. State-2: NAND-1 and NAND-2 are
symmetric, so we explain similarly, we have output Q=0. State-3:
S=R=1, assume that the previous state of Q0=0 (n=0), Q(inverting) of
NAND-2=1 and S of NAND-1=1, so Q1(current)=0, thus it’s no change.
State-4: S=Q=0, Q=Q(inverting)=1, it’s not logic, Q must be different
Q(inverting) 3
Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering
Operating states of the latch circuit
1 using NAND gates
S

0 S 0
R Input Output
S R Q Q
Input Output
R 1 1 1 No change
S R Q Q
0 1 1 0
0
S
1
S Input Output
S R Q Q
R 1
R
1 0 0 Forbidden
Input Output
S R Q Q
1 0 0 1 4
Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering
NOR Gate Latch

Input Output
S R Qn+1
0 1 0
1 0 1
1 1 Forbidden

0 0 Qn
No change

Similar to the NAND latch, we can use NOR gates for design of one
latch circuit and its operation and table are explained and understood
as explained in the NAND circuit.
Because, 2 NOR gates are used, so its truth table is a little bit different
compared to that of the NAND circuit.

5
Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering

Example:
The waveforms of the below figure are applied to the inputs of the
latch of the figure. Assume that initially Q=0, and determine the Q
waveform.

From initial position to T1, S(inverting) and C(inverting)=1 and

output Q=0. We just consider which positions changing from 1/0
into 0/1, in this example, 6 positions (T1 to T6) are considered,
you can have a look more in Solution in next slide
6
Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering

7
Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering

Example:

8
Assoc. Prof. Nguyen Thanh Hai, PhD Figure 5-9
University of Technology and Education
Faculty of Electrical & Electronic Engineering

In Fig, assume that contact P has 2 position (1,2), if P=1, inputs

C=0, S=1 (+5V) and Q=0, inversely if P=2, inputs C=1, S=0 and Q=1
as wave figure. When P is bounced, P stays between (1,2) and at
this time, S=C=1 and Q (no change), means that
Q(current)=Q(previous)=1, called “latch: chốt”, having a look more
Solution in next slide.
When you do one real circuit using metal contacts/switches, to de-
bounce, you can use one latch circuit like this to connect to the
switch. 9
Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering

10
Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering

The End

11
Assoc. Prof. Nguyen Thanh Hai, PhD