HCMC University of Technology and Education

Faculty of Electrical & Electronic Engineering

Lecture:
DIGITAL SYSTEMS
Chapter 4:
Asynchronous MOD Counters

Assoc. Prof. Nguyen Thanh Hai, PhD

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HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Asynchronous MOD Counters

Asynchronous Counters With Mod Number < 2N
1 PRE  1

J PRE Q1 J PRE Q2 J PRE Q3

CK 1 CK 2 CK 3
CLK

K CLR Q1 K CLR Q2 K CLR Q 3

A
B
- Notice: if the counter uses n FFs (n bit=n Q), it means that it can count
from 0 to 2N -1 states. In this example, the counter uses 3 FFs, so it can
count from 000 (0) to 111 (7).
- The counter can count less than 2N, in this example with 3 FFs, so it
counts to one number less than 23=8 states (0 to 7)
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Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Asynchronous MOD Counters

For example: Design one counter can count up to state 6 and then return
state 0 and do again. 1 PRE  1

J PRE Q1 J PRE Q 2 J PRE Q 3

CK 1 CK 2 CK 3
CLK

K CLR Q1 K CLR Q2 K CLR Q 3

St Q3 Q2 Q1
0 0 0 0
Q2
1 0 0 1 Q3
2 0 1 0
The counter can count when CLR  1 and PRE  1 and
3 0 1 1
Q operates Toggle due to J=K=1. Look at truth table,
4 1 0 0 State 6, having Q2=Q3=1, return to 0, so Q2, Q3 are
5 1 0 1 connected to inputs of NAND gate and at this state,
6 1 1 0 the output of NAND gate is 0, Clear=0 and all Q=0,
the counter does again. At the state we want to 3
7 1 1 1 return, we are based on 1s to be connected to inputs
of gate and the output of the gate will be 0, Clear=0.
Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Asynchronous MOD Counters

In order to determine the output waveforms of Q1, Q2, Q3, we can note as
follows:

000 001 010 011 100 101 110

As synchronous counter, 1st clock (CK1) inputs, all Q=0, Q1 is Toggle from Low
to High, similarly, CK2 inputs, Q1 is toggle from High to Low and creates 1
Clock connected to CK of FF2. etc. when it counts up to CK7 (state 6), the
counter will reset to return to 0, at this time Q2=1 and Q3=1 and the output of
NAND = 0, Clear=0, and called MOD-6 counter. 4
Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Asynchronous MOD Counters

Similarly, you can do this example and what is the MOD number of the
counter ? Draw the truth table with the notice of MOD state and explain its
operation, draw the output waveforms?

J PRE Q1 J PRE Q 2 J PRE Q 3 J PRE Q4

CLK CLK CLK CLK

K CLR Q1 K CLR Q 2 K CLR Q 3 K CLR Q4

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Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Asynchronous MOD Counters

Similarly, you can do this example and what is the MOD number of the
counter ? Draw the truth table with the notice of MOD state and explain its
operation, draw the output waveforms?

J Q1 J Q2 J Q3 J Q4

CLK CLK CLK CLK

K CLR Q1 K CLR Q 2 K CLR Q 3 K CLR Q4

Q4
Q3
Q2

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Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Asynchronous MOD Counters

The End

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Assoc. Prof. Nguyen Thanh Hai, PhD