HCMC University of Technology and Education

Faculty of Electrical & Electronic Engineering

Lecture:
DIGITAL SYSTEMS
Chapter 4:
Flip_Flops and Related Devices

Nguyen Thanh Hai, PhD

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University of Technology and Education
Faculty of Electrical & Electronic Engineering

Clock Pulses, called Signals

HIGH input LOW input Positive Negative

clock pulse clock pulse transition transition
and one circle input clock input clock
pulse (edge- pulse (edge-
triggered) and triggered) and
When you use, looking at one arrow one arrow,
blue symbol or waveform one circle
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Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering

Clocked S-R Flip-Flop Input Output

S R CLK Qn+1
0 0 No change
CLK
1 0 1
FF Triggers
positive 0 1 0
transition 1 1 Ambiguous
1 Respond to positive edge clock pulse
S
0
This is FF-RS with CLK of
R
positive edge, so when we
CK find Q waveform, we just care
at time of Positive edge
(arrow-up), don’t care time
Q before and after it, then with
Timestates of R, S at this positive
No Set Reset Set Set edge based on table for
change determining Q waveform.3
Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering

Clocked S-R Flip-Flop Input Output

S R CLK Qn+1
0 0 No change
CLK 1 0 1
Triggers on 0 1 0
negative 1 1 Ambiguous
edge
Respond to negative edge clock pulse
1
S 0 It is similar, however its CLK
is negative edge, (arrow-
R
down in Table). Set: from
CK level Low to High; Reset:
from High to Low
Q
Time
No Set Reset Set Set
change
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Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering
Input Output
Clocked J-K Flip-Flop J K CLK Qn+1
0 0 Q0 No change
1 0 1
0 1 0
1 1 NOT Q0
(toggles)
We do similarly, however
FF-JK has Toggles state, it
means that when J=K=1, Q
is Toggle state, Q
(next)=NOT Q0(current).
We just care CLK at time of
positive edge, don’t care
before and after this edge
and inputs J,K for
determining output
waveform of Q. 5
Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering

Clocked D Flip-Flop
D

CLK
CLK

FF-D is created by connecting

J and K through one NOT gate
as shown in Figure. In Fig,
CLK is positive edge and one
input-D, so its table just has 2
states 0 and 1; always D=Q.
Similarly, we just consider
CLK at time of positive edge
for determining output
waveform based on Table and
D-FF with its waveforms with positive edge clock it depends on D state at this
time of the positive edge.
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Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering

Clocked D Flip-Flop

Enable=1, D=1, Q=1 Enable=1, D=0, Q=0

In this FF-D, CLK (Enable) is High, so the waveform Q always changes

following the change of the input D, if at this time CLK=High, but if CLK
(Enable)=Low, the state of the output Q is no change
We can do similarly, if the circuit uses CLK (inverting)=Enable (Low), so the
waveform Q always changes following the change of the input D, if at this time
CLK=Low, but if CLK (Enable)=High, the state of the output Q is no change7
Assoc. Prof. Nguyen Thanh Hai, PhD
University of Technology and Education
Faculty of Electrical & Electronic Engineering

The End

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Assoc. Prof. Nguyen Thanh Hai, PhD