MOS VLSI DESIGN (ELL734)

A Project Report
on
16-bit Low Power ALU using Shannon Adder &
Bough-Wooley Multiplier on

CMOS 65nm Technology

Submitted by: -

Manish Kumar Singh 2018CRF2528

Manu Kashyap 2018CRF2531
Abstract: In this project a 16-bit Low Power ALU using Shannon Adder & Bough-
Wooley Multiplier multiplier was designed and simulated at the gate level and at the
transistor level using the AMS simulator in Cadence Design System. We optimized the
Different Blocks of ALU for speed & Power by implementing fundamental building
blocks directly in CMOS with the 65nm process. The Operation performed by this
ALU is Addition, Multiplication, Comparison, Subtraction, XOR, XNOR, NAND & NOR.

Addition Logic:

SHANNON THEOREM: The Shannon Theorem can be categorized as the function of

many variables, f (b0, b1, b2, y, bi, y, bn) can be written as the sum of two terms, say
one with a variable ai, set to 0, and one with it set to 1.
f (b0, b1, b2, ......, bi,.....y, bn) = bi’f (b0, b1, b2, ......, 0,.....y, bn) + bi f (b0, b1, b2, ......,
1,.....y, bn)

The Shannon full Adder circuit as shown in figure this Shannon adder operation that
has sum and carry circuits are designed based on standard full adder equations. In
EX-OR gate portion can get result of sum and the processed AND gate based OR
gated based to get result of carry. According to standard full adder equation, the sum
circuits need three inputs. In order to avoid increasing the number of transistors due
to addition of a third input, as the method of Shannon based adder is performed.
Shannon’s Theorem Carry = (A.B) + (B.B’) Shannon’s full adder Sum= ((A xor B).C’)
+ ((A xor B)’.C) Carry= ((A xor B).C) + ((A xor B)’.A).
The above Circuit is designed using Pass-Transistor Logic. Thus, the output had not
full rail to rail swing. So, we have added two inverters to get the full swing output. This
led to an increase in the delay at output of about 50-60pS.

A 16-Bit Adder is Implemented using above Technique. The Delay of the Adder is
1.6 nS.
Multiplication Logic:

The Baugh Wooley multiplier is a signed array multiplier, which utilizes the 2's
complement number system in the implementation of the multiplication algorithm.
Partial products are adjusted to maximize regularity of multiplication array. This section
explains the Baugh Wooley algorithm for a 4x4 multiplier.
A 16x16 Multiplier is implemented using the above technique.

The Delay of the 16-Bit Multiplier is 1.31 nS

Subtraction:

The Subtractor is implemented using same technique as used in the design of the
Adder.

The Delay of the 16-Bit Subtractor is 1.38 nS.

16-Bit Comparator:
Demultiplexer:

XOR
XNOR

Conclusion: The 16-Bit ALU has been designed and the following Operations were
performed successfully.

Addition, Multiplication, Subtraction, Comparison, XOR, XNOR, NAND and NOR

References:

• https://ieeexplore.ieee.org/document/6529021
• http://www.ijiser.com/paper/2014/vol1issue1/Jan2014p101.1.pdf
• https://www.researchgate.net/publication/281810300_Design_of_16-
bit_low_power_ALU-DBGPU