CARRY SELECT ADDER BASED ON DUAL

RAIL ERROR DETECTION AND EASY

2020 International Conference on Power Electronics and Renewable Energy Applications (PEREA) | 978-1-7281-8396-1/20/$31.00 ©2020 IEEE | DOI: 10.1109/PEREA51218.2020.9339769

TESTABILITY
Heera Narayanan
Dept.of Electronics and
Communication Engineering
Rajiv Gandhi Institute of Technology
Kottayam,Kerala, India
heeranarayanan007@gmail.com
Dr. HelenMary M C
Dept.of Electronics and
Communication Engineering
Rajiv Gandhi Institute of Technology
Kottayam,Kerala, India
helenmarymc@rit.ac.in
Anjana G
Dept.of Electronics and
Communication Engineering
Rajiv Gandhi Institute of Technology
Kottayam,Kerala, India
anjanageethaanoor@gmail.com

Abstract—Concurrent error detection (CED) means detecting
errors parallel with normal operation of the circuit. Proposed
adder comprises of a carry select adder which can perform
error detection and testability. Error can be detected by pure
comparison. Comparing includes parity of the sum and predicted
one and also carry outputs. Parity of the sum is generated by
using XOR operation. Input patterns are produced for testing.
Test patterns for different blocks have been designed. For future
intelligent autonomous systems, this system is very important
for finding accidents. Coding is done in Verilog HDL, simulated
using ISIM Simulator and implemented using Xilinx ISE 14.7.
Index Terms—Concurrent error detectability,parity, testability,
test patterns
I. I NTRODUCTION
Nowadays, in the upcoming era of integrated circuits,
system reliability is a major problem. Concurrent error
detection is very crucial in reliable systems. A lot of
arithmetic operations are used in VLSI, out of which addition
is the most important operation [1].Reliability is a major
factor of concern. A lot of concurrent error detectable adders
were proposed earlier [3], [6], [7] and [9].Parity prediction
is used for detecting errors. In this method, errors can be
detected by comparison. Here, predicted parity and parity of
the result i.e. the XORed value of the sum bits are compared.
Proposed system is an adder with concurrent error detection.
Lot of easy testable adders were proposed, but the peculiarity
lies in the concurrent error detection property.Testability is
considered as most powerful property in those adders. It is
useful for testing parallel with operation. The proposed system
mainly consists of a multi-block carry select adder(CSA).This
system assumes two carry inputs to each block, either 0 or
1.Final sum output is calculated by selecting one carry by
using a multiplexer[13].This is the case of parity prediction.
Predicted parity and parity of sum outputs are compared for
detecting faults. It also compares its duplicated carry outputs.
In the previously proposed systems, single error faults
can be detected but not multiple outputs. Concurrent error
detection includes detecting a fault before consecutive error
occurs. Otherwise it affects the reliability of the system. As
reliability is a major factor, this condition is to be satisfied.
So the proposed adder should have the property of concurrent
error detection along with simple testability ,in that case,
fault in it can be easily found at maintenance or at any
stage[4],[8],[10],[11]. These limitations motivated the research
for a system with concurrent error detection and simple
testability. Main aim of this work is to establish such a system.
Arithmetic and Logic Unit (ALU) is a fast electronic circuit
which can carry out both arithmetic and logic operations.
ALU has direct input output access to input output devices,
memory and processor controller [5].ALU can be implemented
using our proposed system. ALU is a very crucial element for
performing operations in all systems. The rest of the paper
is organized as follows. Related works are given in section
II. Proposed system with its error detection and testability are
explained in section III. Experimental results are presented in
section IV. Concluding remarks are given in section V.
II. RELATED WORKS
A. A C-testable multi-block carry select adder[4]
A C-Testable multiple-block carry select adder is proposed.
It uses cell fault model where adders and multiplexers are
taken as cells. In order to obtain C-testability, some inputs are
added. Modifications are done on LSB. This circuit uses 16
patterns for testing. If n combinations are present, 2n patterns
are formed, neglecting the redundancy.
B. On line detection of faults in carry select adders[7]
Delay is an important factor for all digital circuits. Most
important arithmetic operation is addition. A carry select
adder with self-checking property is implemented. Transistors
determine the overhead of the adders. Various error detection
schemes have been discussed in this session, like coding
schemes. Any deviation from the expected format is consid-
ered erroneous. If any change occurs, it is the indication of
error. Performance comparison of various schemes are also

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explained in this session. This method is applicable for single two carry outputs. Parity of carry signals are also produced. It
faults only. Checking can be done using a compact header. has 2 operands Xk and Yk and sum result Sk . Gate level design
of INC and MUX are shown in the Fig.3.Concurrent error
C. Carry checking/Parity prediction adders and ALUs[9] detectability is obtained by special design of half adder and
Self-checking system generation is highly challenging incrementer. It consist of 2 carry outputs, where one is used
nowadays. Arithmetic codes, which is a type of self-checking for addition purpose and the other is used for parity prediction.
code, is used in arithmetic circuits for checking arithmetic In each block, XOR gates are used .The functionality of XOR
operations. Low hardware overhead is a matter of concern.
Checkers are used for finding this factor. It does not require
any translators for codes and used with memories as well.
It is valid for any schemes, any adders and so on. It also
utilizes comparison and two rail checking. But it results in high
hardware cost, so some techniques are introduced to reduce the
cost. It includes avoiding the duplication of complex blocks,
partial carry duplication etc.

III. PROPOSED ALGORITHM

A. Concurrent error detectable adder with easy testability
A carry select adder with concurrency property is proposed
and is given in Fig 1.The inputs are X : [xn−1 ......x0 ] and
Y: [yn−1 .....y0 ]. Sum S: [sn−1 .....s0 ] and carry cn and cn0
are the outputs. It consists of b blocks in which lowest one Fig. 2. Design of blockk .
is block0 .Bit width of each block can be nk and it can be
different from one another. Block k has input carry cink and
output carry coutk . Block0 is a ripple carry adder (RCA), it
comprises of a row of full adders, which are designed by half
adder [HA] and incrementer [INC].
An Incrementer has 3 input pins and 2 output pins. Input
consist of a two bit binary number and carry bit whereas output
consists of 2 bit sum output. All the other blocks comprises
of row of half adders, two sets of incrementers, i.e.IN C0 and
IN C1 and a row of 2:1 multiplexers [MUX]. All the other
block except block0 ,two sets of the sum result will be present,
in which one assumes carry result as 0 and other assumes
carry as 1 and the proper one is selected by the multiplexer.
It consist of input operands X and Y, their parities px and
py , where parities are produced by XORing X and XORing Y
respectively. Sum is the output of the adder circuit, PS is the
predicted parity of sum and cn and cn0 is the carry outputs.
Error caused by faults can be detected by comparison of the
predicted parity PS and sum result S. It also compares cn and
cn0 . It can also check whether there is an inconsistency in the
input.
Fig. 3. Gate level design of HA,INC and MUX.

gates is to unmask the faults, which leads to easy testability.

Fig. 1. Concurrent error detectable adder with easy testability.
Addition block blockk [k > 1] is given in the Fig.2.Each
addition block produces parity Pck , it has two carry inputs and
In each addition block, XOR is used everywhere, but not for
MSB and LSB bits. Two parity outputs PCk0 and PCk1 are
calculated as intermediate candidates in the two rows of INCs.
The PCk is obtained by MUX in left end which selects one of
the calculated parities by using carry input as the select line.
Parity of the carry bits are generated by XOR gates. With the
obtained PCk , parity of sum PS is obtained.
There are 2 carry signals and one sum output for an INC,
Sum output and carry signals are not affected by single stuck-
at fault simultaneously. But it can appear on either of it. So

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there are three possibilities. In first case, carry signals of the possible combinations are provided, out of which two patterns
INC is affected. As there are two carry signals, one is used for are enough for testing, like 110 and 111.Repeating patterns are
addition and the other is used for parity prediction. As carry neglected. So three patterns for HA and INC, two patterns for
signal for addition is affected, the carry signal ck,j creates MUX. If any fault occurs, it will be visible on output through
an error in the sum signal sk,j . If the erroneous value is not MUX.
propagated ,it is detected as the carry is not used for parity
prediction. If it is propagated, then error is also propagated. TABLE I
Error in q carry signals produce q+1 erroneous sum results. I NPUT TEST PATTERNS FOR blockk (k > 1)
In second case, sum signal is affected. If the sum signal is Pattern xk,j , yk,j Cink
erroneous, then the sum bit will be changed. So the parity of j≥1 j=0
0
Cink
the sum bit is also changed. While comparing predicted parity t0 01 11 0
with parity of sum, fault can be found. Predicted parity will t1 11 11 0
t2 10 10 0
be non-erroneous because carry signals are not affected. Third
t3 00 11 0
case is a combination of previous two cases. Both sum signal t4 01 01 1
and carry are affected. Sum bits and carry bits are consistent. t5 11 11 1
In top position of INC, carry is affected but sum is correct t6 10 00 1
t7 00 01 1
and vice-versa for the bottom positions of the INC.
Evaluation of the proposed system is done. Proposed adder
with error detection unit is given in the Fig.4. Proposed
adder in the system generates sum output and parity. A parity C. ALU using proposed adder
generator is present, which consist of XOR gates, it is used for
generating parity of the sum. A two rail checker compares the ALU has an important role in executing arithmetic and
parity of sum and predicted parity along with carry outputs. logic operations. When large numbers of bits are present,
Inputs provided to the checker are complementary inputs ,then cascading of adders are required. These can lead to carry
the output should also be complementary. If the output is propagation delay which can be reduced by carry select adder
erroneous, then it won’t be complementing to each other. configuration. Block diagram of ALU is given in Fig 5.
Hence error is detected. ALU can perform several arithmetic and logic operations. In

Fig. 4. Error detection unit.

Fig. 5. ALU block.

B. Easy testability
Testability is done with input test patterns. For each bit posi-
tion, bit values for j ≥ 1 .INC and HAs are designed carefully.
All possible combinations of the patterns are provided, out of
which recurring patterns are discarded. Only three patterns are
enough for testing, like (x,y,cin) = 100,011 and 111 through
MUX. Test patterns for blockk are given in TABLE I. Same
test pattern generation can be used for a MUX as well. All
order to perform all these operations, three lines are provided
P[2],P[1],P[0].Our proposed adder is rebuild with ALU block.
AND operation is done between P[2] and carry output from
each stage. Output of the AND gate acts as select line for
multiplexer[2]. ALU with proposed adder is given in Fig. 6.
Output from ALU block is fed as input to our proposed adder.
Some of the operations performed are increment, add with
carry, OR etc

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 Fig. 6. ALU using proposed adder.
Fig. 8. ALU Output waveform 1.

IV. EXPERIMENT AND RESULT

The architecture coded in Verilog, simulations are per-

formed using ISIM Simulator, implemented using Xilinx ISE
Design Suite 14.7. Initial block block0 is a ripple carry adder.
Carries from the previous stage will be the carry inputs of the
next stage. XOR gates are placed for parity prediction. Second
block constitute carry select adder. All the blocks following
this block will be similar.
Error detectability is tested by using parity generator and dual
rail checker. Inputs to the checker are complementary. Error is
detected if the output is not complementary. Output waveform
is given in Fig. 7.
Fig. 9. ALU Output waveform 2.

TABLE II
ALU OPERATIONS IN SPECIFIC TIME INTERVAL

Output waveform 1
1-2s x2 [31:0]
2-3s x2 [31:0]+1
3-4s x2 [31 : 0] + y2 [31 : 0]
4-5s x2 [31 : 0] + y2 [31 : 0] + 1
5-6s x2 [31 : 0] − y2 [31 : 0] − 1
Output waveform 2
1-2s x2 [31 : 0] − y2 [31 : 0]
2-3s x2 [31 : 0] − 1
3-4s x2 [31 : 0]
4-5s x2 [31 : 0]or y2 [31 : 0]
—

Fig. 7. Output waveform of adder circuit. TABLE III

C OMPARISON OF VARIOUS CED TECHNIQUES
The design of 32 bit ALU using proposed adder is coded Parity prediction RESO Berger codes
using Verilog, simulated in ISIM simulator and implemented Area(mm2) 2292 2826 3552
in Xilinx ISE 14.7.The simulated waveforms are given in Timing(ps) 3780 7387 4178
Power consumption(mw) 0.0031 0.0032 0.0056
Fig.8.and Fig.9.The table showing functions carried out by
ALU in particular time interval is given in TABLE II.
V. CONCLUSION
Comparison of various Concurrent error detection
schemes(CED) A carry select adder with error detectability is simulated in
Some of the concurrent error detection schemes include parity Xilinx ISE Design Suite 14.7. It consists of carry select adder
prediction, Berger codes, RESO, RERO etc. Parity prediction with parities. Sum parities are produced and compare the car-
utilizes minimum hardware overhead as compared to other ries of output. Faulty output can be found by comparing carries
schemes. Area, timing and power penalties of error detection and parities. Test patterns are formed to check testability. All
techniques are compared and given in TABLE III. these are done in parallel with operation of the system. Lot

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of other CED techniques are available, out of which parity
prediction is most effective. Its area overhead is very low. It
is very easy to detect error in this circuit as it involves simple
comparison. It involves duplication, so it is highly reliable.
The proposed adder is used for the construction of ALU.A
32 bit ALU is implemented using proposed adder. Different
arithmetic and logic operations can be performed.
R EFERENCES
[1] Nobutaka Kito, Member, IEEE, and Naofumi Takagi, Senior Member,
IEEE,“Concurrent Error Detectable Carry Select Adder with Easy Testa-
bility,”IEEE Transactions on computers,2018.
[2] Priyanka Nautiyal, Pitchaiah Madduri, Sonam Negi,“Implementation
of an ALU Using Modified Carry Select Adder for Low Power and
Area-Efficient Applications,“International Conference on Computer and
Computational Sciences (ICCCS),June 2015.
[3] N. Kito and N. Takagi, “Low-overhead fault-secure parallel prefixadder
by carry-bit duplication,“IEICE Transactions on Information and Sys-
tems, vol. E96-D, no. 9, pp. 1962-1970,September 2013.
[4] N. Kito, S. Fujii, and N. Takagi, “A C-testable multiple-block carry select
adder,”IEICE Transactions on Information and Systems, vol. E95-D, no.
4, pp. 1084-1092, Apr. 2012.
[5] Mahmut Yilmaz1, Albert Meixner2, Sule Ozev1, and Daniel
J. Sorin1,“Lazy Error Detection for Microprocessor Functional
Units,“22nd IEEE International Symposium on Defect and Fault Tol-
erance in VLSI Systems,May 2007.
[6] D.Vasudevan and P.Pala,“A technique for modular design of self-
checking carry select adder,“Proc.20th IEEE International Sympiosium
on defect and fault tolerance in VLSI Systems (DFT ’05) , pp. 325-333
Oct 2005.
[7] B. Kumar and P. Lala, “On-line detection of faults in carry-select
adders,”Proc. International Test Conference (ITC ’03), vol. 1, pp. 912-
918, Sep. 2003.
[8] D. Gizopoulos, M. Psarakis, A. Paschalis, and Y. Zorian, “Easily testable
cellular carry lookahead adders,“Journal of Electronic Testing, vol. 19,
pp. 285298, June 2003.
[9] M. Nicolaidis, “Carry checking/parity prediction adders and
ALUs,”IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 11, no. 1, pp. 121-128, Feb. 2003.
[10] R. D. Blanton and J. P. Hayes, “On the design of fast, easily testable
ALUs,“IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 8, pp. 220223, Apr. 2000.
[11] S. Kajihara and T. Sasao, “On the adders with minimum tests,“Proc.
Sixth Asian Test Symposium (ATS ’97), pp. 1015, Nov. 1997.
[12] J.Li and E.E.Swatrzlander Jr, “Concurrent error detection in ALUs by
recomputing with rotated operands,”International Workshop on Defect
and Fault Tolerance in VLSI Systems,May 1992.
[13] O. Bedrij, “Carry-select adder,”IRE Transactions on Electronic Comput-
ers, vol. EC-11, no. 3, pp. 340-346, June 1962.

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