REAL TIME SELF REPAIRABLE MULTIPLEXER

FOR FAULT TOLERANT SYSTEM

BY
1. 17K01A0427 G.ARUNA KUMARI
2. 17KP1A0444 K.CHAITANYA SAI
3. 17KP1A0452 K.SAI NITHISH
4. 17KP1A0408 A.BHANU PRAKASH

Under the esteemed guidance of

Mr . J . Vijay Sagar M.Tech

Assistant Professor
ECE Department

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 CONTENTS
⮚ Objective
⮚ Abstract
⮚ Introduction
⮚ Existed system
⮚ Drawbacks
⮚ Proposed system
⮚ Advantages
⮚ Applications
⮚ Software used
⮚ Result
⮚ Conclusion
⮚ Future scope
⮚ References

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 OBJECTIVE

• The Project main objectives are to find error detecting and Error correction in big size of
digital devises. It’s nothing but a Debugging process.

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 ABSTRACT

Using VLSI more number of transistors can be embedded on a single chip. As the space between
transistors or circuits decreasing the system or chip is more susceptible to faults. Fault
tolerant systems required to avoid inaccurate results. Multiplexer is a device which selects
input signals based on select signal. The existing papers deal with only self checking
multiplexer. In this paper a self repairing 2:1 multiplexer which can repair permanent and
transient faults is proposed.
Two different architectures are proposed for self repairing multiplexer. First
architecture is having additional circuitry to repair the fault in multiplexer. In second
architecture the building blocks of multiplexer like OR and AND gates itself are self
repairable. These self repairing multiplexer architectures can detect and repair the single and
multiple faults. The proposed architectures give 100% error recovery. The circuits are
simulated using Cadence tool and verified the functionality

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 INTRODUCTION

• Approximate computing is a computation that provides a possible exact result.

• Adders and multipliers frame the key segments in these applications

• To reduce hardware complexity of multipliers, truncation is widely employed .

• Approximation techniques in multipliers focus on accumulation of partial products

• The proposed multiplier saves few adder circuits in partial product accumulation

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 EXISTED SYSTEM

SELF CHECKING MULTIPLEXER

• This self checking multiplexer designed by using four transmission gates and an inverter as

shown in Fig. 1. When CS is low S0N is passed to SN. Similarly when CS is high S1N is

passed to SN. Thus it implements the function of multiplexer. In this self checking

multiplexer when SN and SN_bar are same then it shows the presence of a fault. By using

this structure only fault is detected and can’t be repairable. To make the multiplexer self

repairing two different structures are proposed. The CS bar signal is the inverted signal of

CS.

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CIRCUIT DIAGRAM

Fig:1 Self checking multiplexer

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 DRAWBACKS

• Self checking multiplexers are very less in speed.

• The existing system has very high delay.

• It can not correct the faults.

• The results of self checking multipliers are not accurate .

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 PROPOSED SYSTEM

Below diagram shows the self repairing multiplexer in which the additional
circuitry is used to detect and correct thefaults or errors

Fig. self repairable multiplexer

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 CONTINUATION……….

• In Fig. 1 the circuit enclosed in square box shows the basic structure of 2:1 multiplexer.

• Remaining structure which is not included in the square box is used for repairing the
above 2:1 multiplexer.

• The circuit is able to detect all possible single and multiple faults present in the 2:1
multiplexer and repairs the circuit.

• The circuit gives maximum accuracy

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 ADVANTAGES

• The proposed system occupies less area than the existing system .

• It gives accurate results when compared to existed system.

• The proposed system gives the output which doesn't have errors.

• Self repairable multiplexer is very high in speed than the self checking multiplexer.

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 APPLICATIONS

• The proposed model is applicable for filters.

• It can also be used in digital signal processing and in fourier transforms .

• Mostly, our system is mainly used in highly secured and safety related services.

• Self repairable multiplexers can also be used in space related applications and in defence
surveillance.

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 SOFTWARE USED

 XILINX 14.7 ISE SOFTWARE

• This Xilinx design software suite allows you to take your design from design entry through
Xilinx device programming.

• The ISE Project Navigator manages and processes your design through several steps in the
ISE design flow.

 FPGA family: SPARTAN 3E

 Windows 7 with 64 bit operating system

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 RTL SCHEMATIC

RTL is a register transfer level graphical representation of our design. And this
presentation is generated by the synthesis tool at earlier stages of a synthesis
process. It is a gate-level schematic, it shows a representation of the pre-
optimized design in terms of generic symbols such as adders, multipliers,
counters, AND gates, gates OR these are device and independent of the targeted
Xilinx

Fig. RTL SCHEMATIC of self repairable multiplexer

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 SIMULATION RESULT

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 CONTINUATION…..

The inputs are are u,v and enable is i, it is a selection line and the outputs are ff and ft ,
where ff signifies faulty output and ft signifies faultless output . ff is the output1 and its has
some faults that is error and these faults are detected and corrected by using multiplexer .
Hence by using self checking and self repairable 2:1 Mux the faults in the output are corrected
and a faultless output is generated. And selection line i must always be high that is 1. Hence
the output waveform shows that the proposed system gives accurate and error free outputs.

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 CONCLUSION

• As the multiplexer is very vital component in many systems, faults in multiplexer lead to
inaccurate results in the systems.

• Fault tolerant systems must need fault tolerant multiplexer to avoid faults.

• The proposed self repairing multiplexers can be used in multi bit adders, multipliers etc.

• The proposed self repairing multiplexers can be used in fault tolerant systems to get
100% error recoverability.

• The structure repairs itself so that no external inputs are required to repair. This avoids the
area overhead.

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 FUTURE SCOPE

• In todays world the demand for reliable and high performance devices are increased due to
computing circuits to different effects. In this proposed system we get 100% error free but it
also having some time delay like that little bit pitfall .In future we get maximum accurate
systems

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 REFERENCES

• M. Ahmadinejad, M. H. Moaiyeri, and F. Sabetzadeh, “Energy and area efficient

imprecise compressors for approximate multiplication at nanoscale,” AEU-Int. J.
Electron. Commun., vol. 110, Oct. 2019, Art. no. 152859.

• O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, “Dual-quality 4:2 compressors

for utilizing in dynamic accuracy configurable multipliers,” IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 25, no. 4, pp. 1352–1361, Apr. 2017.

• M. Ha and S. Lee, “Multipliers with approximate 4–2 compressors and error recovery
modules,” IEEE Embedded Syst. Lett., vol. 10, no. 1, pp. 6–9, Mar. 2018.

• C.-H. Lin and I.-C. Lin, “High accuracy approximate multiplier with error correction,” in
Proc. 31st ICCD Conf., Oct. 2013, pp. 33–38.

• Z. Yang, J. Han, and F. Lombardi, “Approximate compressors for errorresilient multiplier

design,” in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst., Oct.
2015, pp. 183–186.

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THANK YOU

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