PCB Design Optimization Starts in The CAD Library 6410371 PDF

PCB Design Optimization Starts in the CAD Library
PCB Libraries, Inc.
Tom.Hausherr@PCBLibraries.com
www.PCBLibraries.com
Updated 2013.06.28
Market & Standards Confusion
 The electronics industry is split down the middle, Metric units
Vs. Inch units. CAD vendors, PCB Fabrication and most American
government contractors default to the Imperial Unit System,
while private enterprise companies use the Metric Unit system.
 Terms & Definitions – Footprint Vs. Land Pattern
 Footprint, mid 1980’s OrCAD Capture for PCB library part
 Land Pattern, March 1987 IPC-SM-782, however the IPC-T-
50 definition of “Footprint” is “See Land Pattern”. But
the new IPC-T-50 says a Footprint is component pattern
 Terms & Definitions – Pad Vs. Land (all CAD vendors use Pad)
 Terms & Definitions – Chip Component names, Metric units Vs.
Inch units (1206 or 3216, 0805 or 2012, 0603 or 1608)
 IC Pad (Land) Shape – Rectangle, Oblong & Rounded Rectangle
PCB Libraries, Inc.
Challenges For Library Automation
 IPC claims there are over 2 million man hours of duplication of effort
in PCB library creation. A component manufacturer creates a new
package and thousands of PCB designers create a library part.
 IPC-SM-782 contained component package and land pattern data,
but no component manufacturer in the industry used it
 EIA-PDP-100 contained component package dimensions but no
component manufacturer used it
 JEDEC produces standards for component packages but component
manufacturer’s deviate from the standard to make unique packages
 The electronics industry needs a PCB library solution that eliminates
duplication and mingles standards with User Preferences
 A global PCB library solution will introduce true electronic product
development automation in engineering, design and manufacturing
PCB Libraries, Inc.
Challenges For Library Automation
 Companies use various CAD tools and various versions of CAD
tools and the PCB library is usually not backward compatible
due to new features. Some companies even use obsolete CAD
tools like P-CAD, OrCAD Layout and Protel.
 CAD vendors are consistently upgrading their tools and the
format is constantly changing. Writing translators for each CAD
tool version is challenging.
 CAD vendors do not support importing a neutral library format
and they protect their data via Binary code or Encrypted data.
 Component manufacturer’s cannot be responsible for creating
PCB libraries that support over 30 different CAD tool versions.
 Component manufacturer’s are creating unique component
packages that require complex footprints (land patterns)
 There are a multitude of footprint construction options
PCB Libraries, Inc.
1,800+ Footprint Variations For One Package
PCB Footprint CAD Tool Formats x 30 = 1,800+
UNITS
Metric Units Imperial Units
∞
TOLERANCE
IPC Level A IPC Level B IPC Level C User-Defined Manufacturer

IPC Level A
(Most) IPC Level B
(Nominal) IPC Level C
(Least) User-Defined
Options Manufacturer
Recommended
Options Recommended
… … … Rectangular Oblong D-Shape … … … … … … … … …

SHAPES
… … … Rectangular
Pad Shape Pad Oblong
Shape PadD-Shape
Shape … … … … … … … … …
Pad Shape Pad Shape Pad Shape
ROTATION
… IPC IEC IPC IEC … … … … … … … … …

… IPC IEC … … … …
… IPC IEC IPC IEC IPC IEC … … … … …
… … Zero Zero Zero Zero Zero Zero
… … Zero
Rot A Zero
Rot B Zero
Rot A Zero
Rot B Zero
Rot A Zero
Rot B … … … … … … …
… … … … … … …
… … Rot A Rot B Rot A Rot B Rot A Rot B … … … … … …
…
30 CAD tools X 2 units = 60 x 5 tiers = 300 X 3 pad shapes = 900 X 2 Rotations = 1,800+ variations
PCB Libraries, Inc.
Footprint (Land Pattern) Preferences
Drafting Options Design Rule Options

 Silkscreen Outline Line Width  Metric, Mils, Micrometers, Inch
 Silkscreen Outline Polarity Marker  Footprint & Pad Stack Unit Names
 Map Silkscreen to Nom or Max Body  Include Height in Footprint Name
 Silkscreen to Land (Pad) Clearance  3-Tier Environment or User (Joint Goals)
 Silkscreen Place Round-off  Pad Shape – Rectangle, Oblong, D-shape
 Silkscreen Ref Des Height  Land to Land or Thermal Clearance Min.
 Assembly Outline Line Width  Zero Component Orientation
 Assembly Outline Polarity Marker  Gang Mask Contour or Block
 Map Assembly to Nom or Max Body  Minimum Pad Trim Height (if any)
 Assembly Outline Place Round-off  Rounded Rect. % of Width, Max Radius
 Assembly Ref Des Min/Max Heights  Solder/Paste Mask Over/Under or 1:1
 Courtyard Line Width  Thermal Paste Mask Reduction %
 3D Model Line Width  Local Fiducial Sizes & Min Pitch or None

PCB Libraries, Inc.
IPC-7351C PCB Library Expert

PCB Libraries, Inc.
Footprint Library Elements (QFN)
3D Model Outline 5 Mil (0.12 mm) Silk to Pad Gap
50% Paste Mask Stencil Maximum Body Size
Reduction on Thermal Pad Automatic DRC Checked
Thermal Pad
Broken Into Squares
Perfect IPC-7351C 8 Mil (0.20 mm) Thermal to

Pad Size Calculation Pad Gap DRC Checked
(Auto-pad Trimming)
Default 1:1 Scale Paste Mask
on all Terminal Pads 6 mil (0.15 mm) Pad to
Pad Gap DRC Checked
Default 1:1 Solder Mask
(Auto-pad Trimming)
Size on all Pads
Center of Gravity Origin 2 Ref Des – Silkscreen &

Assembly Drawing
User Defined Pad Shapes
Oblong, Rectangle, D-Shape Nominal Silkscreen Outline
Line Width 5 Mil (0.12 mm)
Assembly Pin 1 Polarity visible after assembly
Silkscreen Pin 1 Polarity
(absence of Silkscreen) IPC-7351 3-Tier Placement Assembly Outline Mapped to
Courtyard External Boundary with Maximum Component Body with 5
2 Mil (0.05 mm) line width Mil (0.12 mm) Line Width

PCB Libraries, Inc.
Past & Future Innovation
Old IPC-7351B Concepts New IPC-7351C Ideas
Universal Grid Round-off 2 Mil (0.05mm) Universal Grid Round-off 1 Mil (0.01mm)
Silkscreen Outline Under Components Functional (Useful) Silkscreen Outline
1 Local Fiducial Size for 3-Tiers 3-Tier Local Fiducial Sizes
1 Silkscreen Line Width & Space for 3-Tiers 3-Tier Silkscreen Line Widths & Spaces
1 Silkscreen Ref Des Height for 3-Tiers 3-Tier Silkscreen Ref Des Heights
Multiple Shape Polarity Marking Single Shape Polarity Marking
Single Zero Component Orientation Two Zero Component Orientations – A & B
Pads on Assembly Drawing On/Off Switch for Pads on Assembly
IPC/EIA Component Dimension Letters JEDEC Component Dimension Letters
Predominant Metric Units Acceptance of Imperial & Metric Units
Pad Trim Under Component 6 Mils (0.15) No Pad Trimming Under Components
Thermal Pad Paste Mask Reduction 40% Thermal Pad Paste Mask Reduction 50%
Min. Land to Land Space 8 Mil (0.2 mm) Min. Land to Land Space 6 Mil (0.15mm)

PCB Libraries, Inc.
Anatomy of a PCB Library
 IPC 3-Tier Library System, User & Mfr. Recommended
 Solder Joint Calculations & Manufacturing Tolerances
 Component Package Lead Styles
 Footprint (Land Pattern) Naming Convention
 Padstack Naming Convention
 Placement Courtyard
 Local Fiducials
 Zero Component Orientation
 Footprint (Land Pattern) Origins
 Reference Designators
 Silkscreen & Assembly Outlines and Polarity Marking
 3D Modeling
PCB Libraries, Inc.
Five Tolerance Settings
 IPC-7351 Density Level A: Maximum (Most) Land Protrusion – For low-density product
applications, the 'maximum' land pattern condition has been developed to
accommodate wave or flow solder of leadless chip devices and leaded gull wing
devices. The geometry furnished for these devices, as well as inward and “J” - formed
lead contact device families, may provide a wider process window for reflow solder
processes as well.
 IPC-7351 Density Level B: Median (Nominal) Land Protrusion – Products with a
moderate level of component density may consider adapting the 'median' land pattern
geometry. The median land patterns furnished for all device families will provide a
robust solder attachment condition for reflow solder processes and should provide a
condition suitable for wave or reflow soldering of leadless chip and leaded Gull Wing
type devices.
 IPC-7351 Density Level C: Minimum (Least) Land Protrusion – High component density
typical of portable and hand-held product applications may consider the 'minimum'
land pattern geometry variation.
 Manufacturer Recommended: Component manufacturer recommended pattern.
 User Defined: Definable preference rules created by the customer.

PCB Libraries, Inc.
IPC-7351C 2-Tier Library System
X
Density Level A Density Level B Density Level C
Very Robust General Purpose Minimal Solder Joint
Solder Joint Solder Joint High Density Applications
May be used for hand soldering
PCB Libraries, Inc.
Custom Footprint Patterns
 Manufacturer Recommended: Component

manufacturer recommended pattern
 User: Definable preference rules created by user

PCB Libraries, Inc.
SMT Solder Joint Calculations
 These 7 factors are used to calculate the optimum Land Size

1. Component Body Tolerance – ± 4 Mil (0.1) thru ± 12 (0.3)
2. Component Terminal Tolerance – ± 8 Mil (0.2) thru ± 20 Mil (0.5)
3. Fabrication Tolerance – ± 2 Mil (0.05 mm)
4. Placement Tolerance – ± 1 Mil (0.025 mm) T 2
+ F 2
+ P 2
√
5. Land Size Round-off – ± 1 Mil or (0.01 mm or 0.05 mm)
6. Land Spacing Round-off – ± 1 Mil or (0.01mm or 0.05 mm)
7. Solder Joint Goals for Toe, Heel and Side
Gull Wing Lead Least Nominal Most
Pitch > 0.625 Level C Level B Level A
Toe 0.15 0.35 0.55
Heel 0.25 0.35 0.45
Side 0.01 0.03 0.05
Round-off Factor Round-off to the Nearest 0.01 or 0.05
Courtyard Excess 0.10 0.25 0.50

PCB Libraries, Inc.
Footprint Feature Rounding Units
Footprint Features in 0.01 mm increments

0.01 0.01 0.01
0.01 0.01 0.01

0.005 for 0.65
pitch
0.01
0.01
Line Widths Corner

0.01 0.01 0.01 Radius 0.01
*Japanese 80% rule
PCB Libraries, Inc.
Mixing PCB Design Units
 Building CAD libraries in Metric and importing them into

Imperial unit databases compromises perfection in part
placement, via fanout and trace routing.
 Avoid designing your PCB Layout in Metric and have all of
the mechanical constraints in Imperial units.
 Outputting Gerber data or X,Y coordinates for assembly
machine production can be either complex in structure
or simplified throughout the entire electronic product
development process.
 No PCB library feature should be less than 1 mil when
using Imperial units or 0.01 mm when using Metric units.
PCB Libraries, Inc.
History
 From the 1960’s through the 80’s the primary PCB design
grid system used Imperial units.
 Physical design units were in tenth Inch, but every PCB
layout used 0.001” as the base unit of measure and
everything was rounded in 1 mil increments.
 In the 1990’s the world standards organizations banded
together to agree that the metric unit system was
superior for solving PCB design development.
 IPC started to publish all literature in metric units and by
1999, JEDEC and most component suppliers complied
with the new International System (SI) measurements
PCB Libraries, Inc.
Standards Organizations For PCB Libraries
 JEDEC – Component Packages

 EIA – Component Packaging (Tape & Reel)
 IPC – Land Patterns (CAD Libraries)
 IEC – European Electronic Standards
 NIST – Naming Conventions
 JISSO/CAMEST – Package Miniaturization
 JEITA – Component Packages in Asia
 EIAJ – Component Packages in Japan
 NEMI – Component Manufacturer’s

PCB Libraries, Inc.
Gridless Shape Based Concept
 Due to the mixing of Inch & Metric PCB design units, PCB real-
estate was not optimized when working with a snap grid for
routing traces
 CAD vendor’s invented Shape Based routing technology to
optimize trace routing
 Due to the number of grid cells that need to be calculated,
going off-grid or “gridless” uses an enormous amount of
computer CPU and memory resources. The auto-router has
hundreds of thousands of additional grid options for
computation. Exception: Mentor Expedition
 A Gridless working environment in the majority of CAD tools is
difficult to manually edit or clean up trace routing
PCB Libraries, Inc.
PCB Grid System Impact
 Snapping objects to a course grid uses less CPU

processing and computer memory
 Centers traces between objects
 Provides better aesthetic looking results
 Increases PCB layout productivity and quality
 Affects all aspects of PCB design layout
 CAD Libraries
 Part Placement
 Via Fanout
 Trace Routing
PCB Libraries, Inc.
Grid Unit Increments
 There are 3 snap grid options for the base unit of measure that
everything in a PCB design layout should be rounded to:
 0.01 mm (High Res), 0.05 mm (Low Res) or 1 mil increments
 CAD Library Construction
 Part & Test Point Placement
 Via Sizes
 Mounting Holes
 Board Outline
 Via Fanout
 Trace Widths
 Routing Grid
PCB Libraries, Inc.
BGA Library Construction Collapsing Ball
 Most BGA ball features are in 0.05 mm increments
Nominal Ball Land Pattern Nominal Land
Reduction Land Variation
Diameter Density Level Diameter
0.75 25% A 0.55 0.60 - 0.50
0.65 25% A 0.50 0.55 - 0.45
0.60 25% A 0.45 0.50 - 0.40
0.55 25% A 0.40 0.45 - 0.35
0.50 20% B 0.40 0.45 - 0.35
0.45 20% B 0.35 0.40 - 0.30
0.40 20% B 0.30 0.35 - 0.25
0.35 20% B 0.30 0.35 - 0.25
0.30 20% B 0.25 0.25 - 0.20
0.25 20% B 0.20 0.20 - 0.17
0.20 15% C 0.17 0.20 - 0.14
0.17 15% C 0.15 0.18 - 0.12
0.15 15% C 0.13 0.15 - 0.10
 BGA pin pitches are in 0.05 mm increments

Exception is the 50 mil pitch (1.27 mm pitch)

 Most BGA package dimensions are in 0.05 mm increments
PCB Libraries, Inc.
BGA Library Construction Non-Collapsing Ball
 Most BGA ball features are in 0.05 mm increments
Nominal Ball Land Pattern Nominal Land
Increase Land Variation
Diameter Density Level Diameter
0.75 15% A 0.85 0.90 - 0.80
0.65 15% A 0.75 0.80 - 0.70
0.60 15% A 0.70 0.75 - 0.65
0.55 15% A 0.65 0.70 - 0.60
0.50 10% B 0.55 0.60 - 0.50
0.45 10% B 0.50 0.55 - 0.45
0.40 10% B 0.45 0.50 - 0.40
0.35 10% B 0.40 0.45 - 0.35
0.30 10% B 0.35 0.40 - 0.30
0.25 10% B 0.30 0.35 - 0.25
0.20 5% C 0.21 0.26 - 0.16
0.17 5% C 0.18 0.22 - 0.13
0.15 5% C 0.16 0.21 - 0.11
 BGA pin pitches are in 0.05 mm increments

Exception is the 50 mil pitch (1.27 mm pitch)

 Most BGA package dimensions are in 0.05 mm increments
PCB Libraries, Inc.
IPC-7351C BGA 3-Tier Features
Table 3-18 BGA’s do not have 3-Tier pad sizes
IPC-7351C BGA 3-Tier library
• Silkscreen Line Widths
• Least – 0.10 mm
• Nominal – 0.12 mm
• Most – 0.15 mm
• Reference Designator Heights
• Most – 1.50 mm
• Courtyard Excess
• Most – 0.5 mm
• Local Fiducial Sizes
• Most – 1.00 mm

PCB Libraries, Inc.
BGA Dogbone Fanout Via Sizes
BGA Thermal Trace & Number

Pad Hole Plane Solder Thermal Thermal
Pin VIA Name Spoke Space of
Size Size Clearance Mask ID OD
Pitch Width Width Traces
1.27 VIA63-30-85 0.635 0.30 0.85 0.00 None None None 0.125 2
0.65 Via-in-Pad 0.45 0.15 0.55 0.65 0.45 0.55 0.10 0.075 1
0.50 Via-in-Pad 0.275 0.125 0.40 0.50 0.30 0.40 0.10 0.05 1
0.40 Via-in-Pad 0.25 0.125 0.35 0.25 0.25 0.35 0.075 0.05 1

PCB Libraries, Inc.
0603 (EIA 0201) & 1005 (EIA 0402) Capacitors
1.0 mm Pitch BGA
0603 (EIA 0201)

Least 1005 (EIA 0402)
Environment
1005 (EIA 0402)

Via-in-Pad

PCB Libraries, Inc.
BGA Trace/Space Sizes
 Trace widths are in 0.01 mm or 1 mil increments

 Common BGA trace widths
 0.05 mm (2 mils) breakout only
 0.07 mm (3 mils) breakout only
 0.10 mm (4 mils)
 0.12 mm (5 mils)
 0.15 mm (6 mils)
 0.20 mm (8 mils)
 0.25 mm (10 mils)
 0.30 mm (12 mils)
PCB Libraries, Inc.
0.4 mm Pitch BGA with 1.0 mm PCB Material
Via-in-Pad Technology
• BGA Ball Size: 0.25 (10)
• BGA Land Dia: 0.25 (10)
• Hole Size: 0.125 (5) 8:1 aspect
• Thermal Relief Required
• Plane Clearance: 0.35 (14)
• Solder Mask: 1:1 scale
Trace/Space Data
• Trace Width: 0.05 (2)
• Trace/Trace Space: 0.05 (2)
• Trace/Via Space: 0.05 (2)
• Trace/BGA Land: 0.05 (2)
• Routing Grid: 0.05 (2)
• Part Place Grid: 0.5 (20)

PCB Libraries, Inc.
0.4 mm Pitch BGA Micro Via Technology
0.065 mm 0.11 mm
Annular Ring
0.35 mm
Plane
0.23 mm Clearance
Via Land
0.1 mm
0.28 mm Micro Via
Solder Mask Hole
0.05 mm
0.06 mm
0.17 mm
PCB Libraries, Inc.
0.4 mm Pitch BGA
Solder Mask Clearance
With Track No Track
0.025 mm 0.05 mm

PCB Libraries, Inc.
0.4 mm Pitch BGA
Solder Mask Maximum Registration Offset
Safety distance to allow

for coverage of line edge
PCB Libraries, Inc.
Staggered Micro Vias

PCB Libraries, Inc.
Stacked Micro Vias

PCB Libraries, Inc.
BGA Land
0.1 mm Micro Via Cu Foil
Layer 1
Prepreg
Layer 2
Prepreg
Layer 3
Capped to
Create Conductive
Target Land Fill
PCB Libraries, Inc.
Plated (Conductive Fill) Micro Vias
MICROFILL™ EVF Copper Via Fill
Next Generation of Pattern Viafill Plating Technology
http://www.dowelectronicmaterials.com/

PCB Libraries, Inc.
Advanced Routing Technique For 0.4 mm BGA
0.4 mm BGA routing option

0.25 mm pad with 0.05 mm snowman for drill AR
LDI Solder Mask = 0.1 mm solder dam
0.05 mm Offset
0.15 mm Space 0.05 mm Annular
0.1 mm Drill
0.4 mm Pitch
0.25 mm Land

PCB Libraries, Inc.
Advanced Routing Technique For 0.4 mm BGA
0.4 mm BGA routing option

Route outside row & 50% of channels per layer
0.075 mm Trace
0.075 mm Space
0.075 mm Space
0.1 mm Drill
0.25 mm Land
0.2 mm Space

PCB Libraries, Inc.
11 X 12 - 0.4 mm Pitch BGA
Advanced
routing
solutions for a
11 X 12 - 0.4 mm
pitch BGA
Route outside
row on layer 1
Trace Width 0.75

PCB Libraries, Inc.
Route the two

outside rows on
layer 2
Trace Width 0.75

PCB Libraries, Inc.
Route the next

three rows on
layer 3

PCB Libraries, Inc.
Route Remaining Connections on Layer 4

PCB Libraries, Inc.
0.5 mm Pitch BGA
• BGA Land Dia: 0.275 (11)
• Hole Size: 0.15 (6)
• Thermal Relief Required
Trace/Space Data

PCB Libraries, Inc.
0.5 mm Pitch BGA With Non-Collapsing Balls
Via-in-Pad Technology Trace/Space Data

• BGA Ball Size: 0.15 (6) • Trace Width: 0.075 (3)
• BGA Land Dia: 0.275 (11) • Trace/Trace Space: 0.075 (3)
• Hole Size: 0.15 (6) • Trace/Via Space: 0.075 (3)
• Plane Clearance: 0.425 (17) • Trace/BGA Land: 0.075 (3)
• Solder Mask: 1:1 scale • Routing Grid: 0.05 (2)
BGA Component
0.15 mm BGA Ball
0.1 mm Paste Mask
Solder Mask
1 mm PCB Thickness
0.15 mm Via-in-Land

PCB Libraries, Inc.
0.65 mm Pitch BGA
• BGA Land Dia: 0.4 (16)
• Hole Size: 0.15 (6)
Trace/Space Data
• Part Place Grid: 1 (40)

PCB Libraries, Inc.
0.65 mm Pitch BGA
• BGA Land Dia: 0.425 (17)
• Hole Size: 0.2 (8)
Trace/Space Data
• Via Grid: 0.65 (26)

PCB Libraries, Inc.
Filled And Capped Via
 Filled and Capped Via (Type

VII Via) - A Type V via with a
secondary metallized coating
covering the via. The
metallization is on both sides.
 This technique is used for
Via-in-pad technology for
0.65mm and 0.5mm BGA
pitch devices.
 Solder mask is 1:1 scale on
the BGA side of PCB and
Tented on the opposite side
to protect the routed trace.

PCB Libraries, Inc.
Before Assembly Process
BGA

PCB Libraries, Inc.
After Printing Paste & BGA Placement

PCB Libraries, Inc.
During Reflow Soldering

PCB Libraries, Inc.
Post Reflow Soldering

PCB Libraries, Inc.
0.8 mm Pitch BGA
 BGA Data
• BGA Ball Dia: 0.5 (20)
• BGA Land Size: 0.45 (17)
 Via Data
• Pad Size: 0.5 (20)
• Hole Size: 0.25 (10)
• Anti-Pad: 0.7 (28)
 Trace/Space Data
• Trace/Via Space: 0.125 (5
• Via Grid: 0.2 (8)
PCB Libraries, Inc.
0.8 mm Pitch BGA
 BGA Data
• BGA Ball Dia: 0.5 (20)
 Via Data
• Pad Size: 0.45 (18)
• Hole Size: 0.2 (8)
• Anti-Pad: 0.65 (26)
• Trace/Trace Space: 0.125
• Via Grid: 0.2 (8)
PCB Libraries, Inc.
1.0 mm Pitch BGA
 Via Data
• Pad Size: 0.50 (20)
• Hole Size: 0.25 (10)
• Via Grid: 0.5 (20)

PCB Libraries, Inc.
1.0 mm Pitch BGA
 Via Data
• Pad Size: 0.375 (15)
• Hole Size: 0.175 (7)
• Via Grid: 0.5 (20)

PCB Libraries, Inc.
1.0 mm Pitch BGA
 Via Data
• Land: 0.50 (20)
• Hole: 0.25 (10)
• Via Grid: 0.5 (20)

PCB Libraries, Inc.
1.0 mm Pitch BGA w/100 Ohm Internal Diff Pairs
0.11 mm
0.08 mm
0.70 mm
Plane
Clearance
0.50 mm
Via Land
0.25 mm
Via Hole
0.12 mm
0.20 mm Note: Vias are on a
0.50 mm 1 mm snap grid

PCB Libraries, Inc.
1.0 mm Pitch BGA w/50 Ohm Single Ended
0.20 mm 0.70 mm
Plane
0.095 mm Clearance
Global Feature Min
Clearance 0.1 mm
0.50 mm
Trace / Via Snap Via Land
Grid 0.05 mm
0.25 mm
0.105 mm Gap Via Hole
0.1025 mm
PCB Libraries, Inc.
1.0 mm Pitch BGA Via and Trace Sizes
 Via & Trace/Space features and routing grids are in

0.05 mm increments. Here are two vias on 1 mm grid.

PCB Libraries, Inc.
1.27 mm (50 mil) Pitch BGA
 Via Data
 Land: 0.635 (25)
 Hole: 0.30 (12)
 Plane Clearance: 0.85 (33)
 BGA Land Size: 0.6 (24)
 Trace Width: 0.127 (5)
 Trace/Trace Space: 0.127 (5)
 Trace/Via Space: 0.127 (5)
 Routing Grid: 0.127 (5)
 Via Grid: 0.635 (25)
 Part Place Grid 1: 1.27 (50)
 Part Place Grid 2: 0.635 (25)
PCB Libraries, Inc.
Metric Pitch BGA Snap Grids
 Part Placement, Via Fanout and Routing grids should be

evenly divisible into 1 mm and only 1 place past decimal
Metric Working Grids Metric Non-Working Grids
1 0.9
0.5 0.8
0.2 0.7
0.1 0.6
0.05 0.4
0.3
0.25
0.15
0.125
PCB Libraries, Inc.
Trace / Space Sizes
 Metric trace width rules are in increments of 0.05mm with

two exceptions 0.07mm (3 mil) & 0.12mm (5 mil)
 Basic Rounded Equivalents
 0.30 mm = 12 mils
 0.25 mm = 10 mils
 0.20 mm = 8 mils
 0.15 mm = 6 mils
 0.12 mm = 5 mils
 0.10 mm = 4 mils
 0.07 mm = 3 mils
 0.05 mm = 2 mils

PCB Libraries, Inc.
Plastic BGA, Chip Wire Bonded
Note: Interposer land area is solder mask defined

PCB Libraries, Inc.
BGA, Flip Chip Bonded
Note: Interposer land area is solder mask defined

PCB Libraries, Inc.
Solder Mask vs: Metal Defined Pad Design
 Two basic types of solder lands used for BGA

packages
 Non-solder mask defined (NSMD)
 Solder mask defined (SMD)
 NSMD lands are copper defined - solder mask
clearance around land
 SMD lands have solder mask overlapping the
copper land

PCB Libraries, Inc.
Solder Pads (Lands) For BGA Components
Non-Solder Mask Solder Mask
Defined Land Defined Land

PCB Libraries, Inc.
Effect of Solder Mask Relief On BGA Pads
Solder Mask Relief Around Land ~0 mm 0.15 mm
Top view of land

illustrating increase of
effective land diameter
due to trace
connections
Cross-sectional view of
land with solder ball
joint illustrating the
solder wetting down
the edge of the land
when there is solder
mask relief away from
the land edge

PCB Libraries, Inc.
Gull Wing Lead Library Construction
 Gull Wing lead package dimensions for SOP, QFP, SOD &
SOT are in 0.05 mm increments
 Pin pitches are in 0.05 mm increments
 All Land Pattern data is in 0.01 or 0.05 mm increments
 Land (Pad) Length and Width
 Land (Pad) Snap Grid
 All 2D Line Widths
 Polarity Markings
 2D Line Snap Grid
 Ref Des Height & Width
 Local Fiducials

PCB Libraries, Inc.
Chip Component Library Construction
 Chip component packages are in 0.05mm increments

 All Land Pattern data is in 0.01 or 0.05 mm increments
 Land (Pad) Length and Width
 Land (Pad) Snap Grid L L1
 All 2D Line Widths

 Polarity Markings
W
 Local Fiducials C1 C2
 Rounded Rectangle Radius
PCB Libraries, Inc.
DIP Library Construction
 DIP component packages are in 0.01mm increments

 If pin pitch is Imperial units, so are the pad centers
 Most Land Pattern data is in 0.01 mm increments –
 Pad and Hole Sizes
 Pin Pitch and Pin Span
2.54 mm
 Plane Anti-pad
 Thermal Relief & Spokes
 2D Line Widths
7.62 mm
 Polarity Markers
 Keep-out Snap Grid
PCB Libraries, Inc.
PCB Library Construction
 In every CAD library part there are four different 2D

lines that need to be defined and they all perform a
different purpose. Here are the default line width sizes
for the IPC-7351C standard library outline guidelines.
1. 3-Tier Silkscreen Outline Widths
 Most 0.15 mm (6 mils)
 Nominal 0.12 mm (5 mils)
 Least 0.10 mm (4 mils)
 User Defined ?
2. Assembly Outline, 0.1 mm (4 mils)
3. Placement Courtyard, 0.05 mm (2 mils)
4. 3D Model Outline, 0.001 mm (1 mil)

PCB Libraries, Inc.
Metric Conversion Note
 IPC: The Universal PCB Design Grid System is based on 0.01 or

0.05mm units. All shapes and sizes for every aspect of the PCB
layout should be in increments of 0.01 or 0.05mm.
Transitioning to the metric system for PCB layout is necessary
to achieve global electronic product development automation.
 NIST: The current effort toward national metrication is based
on the conclusion that industrial and commercial productivity,
mathematics and science education, and the competitiveness
of American products and services in world markets, will be
enhanced by completing the change to the metric system of
units. Failure to complete the change will increasingly
handicap the nation's industry and economy.

PCB Libraries, Inc.
Surface Mount Component Lead Styles
PCB Library Expert is not just a “Component Family” tool but it bases all rules on “Component
Lead Type”. This dramatically speeds up development time to add new component families and
features. Lead Types also simplify User Preference Options.
Ball Grid Array Bump Grid Array Land Grid Array Column Grid Array Pillar Grid Array Flat Lug
Flat Side Convex Side Concave Side Corner Concave Inward L Flat Bottom
Gull Wing Outward L J-Lead End Cap Under Body L No-Lead

PCB Libraries, Inc.
Footprint Pad Shapes vs. Lead Shape
Rectangle or Oblong D-Shape
Rounded Rectangle
QFN’s
PQFN’s

PCB Libraries, Inc.
Rounded Rectangle Pad Shape Guideline
 Used For These Component Lead Styles –

1. Gull Wing & J-Lead
2. Inward, Outward & Under Body “L Bend”
3. Side Flat, Convex & Concave and Corner Concave
4. End Cap Termination
Corner Radius =
20% Land Width
1 Mil (0.01 mm)
Land Width = Round-off
Shortest Side
Maximum Radius =
10 Mil (0.25 mm)

PCB Libraries, Inc.
Rounded Rectangular Pad Shape

PCB Libraries, Inc.
Pad (Land) Trimming Under Components
 For Gull Wing Component Lead Styles

1. The original concept was to trim Pads (lands) under the “Gull
Wing” component body for low profile (A1) stand-off
2. The new concept is No Pad (Land) Trimming is necessary except
to meet the minimum Pad to Pad (Land to Land) and/or thermal
pad to Pad (land) clearance
No Pads (Lands)
Trimmed Pads (Lands) Trimmed
6 Mil (0.15 mm) Under Component Under Component
Paste Mask (Nominal Body Size)
A1 Thickness
2 Mil (0.05 mm)
Land & Solder
Mask Thickness
PCB

PCB Libraries, Inc.
JEDEC Component Dimensions

PCB Libraries, Inc.
Component Dimensions
_u=“UNITS” _f=“FAMILY”
Millimeter = 0 CapacitorNP = 0 (non-polarized)
Micrometers = 1 CapacitorP = 1 (polarized) Chip Component Family
Inch = 2 CapacitorWR = 2 (wire rectangular)
Mil = 3 Diode = 3
Current = 4 Fuse = 4
IC = 5
Inductor = 6
InductorP = 7 (precision inductor)
LED = 8
Resistor = 9
Transistor = 10
_u="0" _f="0" A=",,110000" D="300000,,340000" E="140000,,180000" L="35000,,95000"
Units Family Maximum Body Length Body Width Lead Length

Height “Min,,Max” “Min,,Max” “Min,,Max”

PCB Libraries, Inc.
IPC-7351 Footprint Names
Ball Grid Array’s BGA + Pin Qty + C or N + Pitch P + Ball Columns X Ball Rows _ Body Length X Body Width X H
BGA w/Staggered Pins BGAS + Pin Qty + C or N + Pitch P + Ball Columns X Ball Rows _ Body Length X Body Width X H
Capacitors, Chip, Array, Concave CAPCAV + Pitch P + Body Length X Body Width X Height - Pin Qty + Environment
Capacitors, Chip, Array, Flat CAPCAF + Pitch P + Body Length X Body Width X Height - Pin Qty + Environment
Capacitors, Chip, Non-polarized CAPC + Body Length + Body Width X Height + Environment
Capacitors, Chip, Polarized CAPCP + Body Length + Body Width X Height + Environment
Capacitors, Chip, Wire Rectangle CAPCWR + Body Length + Body Width X Height + Environment
Capacitors, Molded, Non-polarized CAPM + Body Length + Body Width X Height + Environment
Capacitors, Molded, Polarized CAPMP + Body Length + Body Width X Height + Environment
Capacitors, Aluminum Electrolytic CAPAE + Base Body Size X Height + Environment
Ceramic Flat Packages CFP127P + Lead Span Nominal X Height - Pin Qty + Environment
Column Grid Array, Circular Lead CGA + Pin Qty + C + Pitch P + Pin Columns X Pin Rows _ Body Length X Body Width X Height
Column Grid Array, Square Lead CGA + Pin Qty + S + Pitch P + Pin Columns X Pin Rows _ Body Length X Body Width X Height
Pillar Column Grid Array PCGA + Pin Qty + S + Pitch P + Pin Columns X Pin Rows _ Body Length X Body Width X Height
Crystals (2 leads) XTAL + Body Length X Body Width X Height + Environment
Diodes, Chip DIOC + Body Length + Body Width X Height + Environment
Diodes, Dual Flat No-lead DIODFN + Body Length X Body Width X Height – Pin Qty + Environment
Diodes, Molded DIOM + Body Length + Body Width X Height + Environment
Diodes, MELF DIOMELF + Body Length + Body Diameter + Environment
Diodes, Side Concave, 2 Pin DIOSC + Body Length X Body Width X Height - Pin Qty + Environment
Diodes, Side Concave, 4 Pin DIOSC+ Pitch P + Body Length X Body Width X Height - Pin Qty + Environment
Fuses, Molded FUSM + Body Length + Body Width X Height + Environment
Inductors, Chip INDC + Body Length + Body Width X Height + Environment
Inductors, Molded INDM + Body Length + Body Width X Height + Environment
Inductors, Precision Wire Wound INDP + Body Length + Body Width X Height + Environment
Inductors, Chip, Array, Concave INDCAV + Pitch P + Body Length X Body Width X Height - Pin Qty + Environment
Inductors, Chip, Array, Flat INDCAF + Pitch P + Body Length X Body Width X Height - Pin Qty + Environment
Land Grid Array, Circular Lead LGA + Pin Qty + C + Pitch P + Pin Columns X Pin Rows _ Body Length X Body Width X Height
Land Grid Array, Square Lead LGA + Pin Qty + S + Pitch P + Pin Columns X Pin Rows _ Body Length X Body Width X Height
Land Grid Array, Rectangle Lead LGA + Pin Qty + R + Pitch P + Pin Columns X Pin Rows _ Body Length X Body Width X Height

PCB Libraries, Inc.
Footprint Name Update to Eliminate Duplication
 The original IPC-7351 footprint naming convention does not include

Gull Wing component lead tolerances, Thermal Pad sizes, BGA Ball
sizes or various pin assignments into account. Therefore, the same
component with different tolerances can produce a different land
size and spacing with the same footprint name.
 A footprint name of SOP50P710X120-14N can have version A, B, C,
D which do not indicate the variances in Thermal Tab or Lead Length
 There are 3 component features that affect the footprint name
1. Square Thermal Tab Size = SOP50P710X120-14T300
2. Rectangle Tab Shape = SOP50P710X120-14T300X500
3. Gull Wing Lead Length Tolerance = SOP50P710X120-14L50
4. BGA Ball Size = BGA121C50P11X11_600X600X100B23
 For component mfr. recommended footprint drop the environment
level character after the pin qty. - SOP50P710X120-14
PCB Libraries, Inc.
Footprint & Padstack Names
 The IPC-7351 Footprint (land pattern) and Padstack naming
convention strictly adheres to the metric unit system.
 However, not everyone in the electronics industry has adopted
the metric unit system.
 Component manufacturer’s name their Chip Components after
the Inch Unit system. i.e.: 1206, 0805, 0603, 0402, etc.
 Under pressure from the electronics industry to not force
companies and PCB designers into using metric units for PCB
layout, many companies using the Imperial unit system have
requested Imperial based Footprint and Padstack names
 I would not recommend building Footprints using Metric Units for
Inch based PCB design layout. The pad size, drafting items, feature
spacing & round-off values are not compatible.
 Inch design = Inch libraries & Metric design = Metric libraries
PCB Libraries, Inc.
Surface Mount Padstacks
 The surface mount component padstack consists of a

solder pad, solder mask and solder paste
 The solder mask and paste mask size are typically the same
as the pad size
 Solder Mask – Allow the PC Board manufacturer to expand
the solder mask size according to the trace/space DRC rule
technology that the PCB designer used in the PCB design
the layout. However, many designers swell mask in library.
 Solder Paste – Allow the stencil manufacturer to
over/under size the solder paste to match the
specifications of the assembly shop that the paste mask
stencil is being made for
PCB Libraries, Inc.
Block & Contour Gang Masking SMT Pads
Block Mask Contour Mask
Block Solder Mask on

Oblong pad shape does not
work well if copper pour is
used on outer layers

PCB Libraries, Inc.
Solder Mask Defined SMT Pads
 Solder Mask defined SMT Pads are popular with Flexible

Circuits and fine pitch BGA’s in Hand Held devices
 For Flex Circuits, only solder mask the Toe & Heel (not the
Side) to increase the pad to board strength
 Fine pitch BGA drop tests conclude the pad will break away
from the prepreg rather than the ball breaking solder joint

PCB Libraries, Inc.
Plated Through-hole Padstacks
 This is what a typical Through Hole Padstack is built like:

 Top Solder Mask
 Top Pad
 Inner Layer Pad
 Plane Thermal Relief
 Plane Anti-pad
 Bottom Pad
 Bottom Solder Mask
 Drilled Hole
PCB Libraries, Inc.
Plated Hole Size Calculations
Round Lead Square Lead

Rectangle Lead
Max Max Max
IPC-2222A Table 9-5

Hole Diameter to Lead Diameter Relationships
Maximum Lead + Environment Level = Minimum Hole
Level A Level B Level C
10 Mil (0.25 mm) 8 Mil (0.20 mm) 6 Mil (0.15 mm)

PCB Libraries, Inc.
Mil Proportional PTH Padstacks
Max Finished Top Inner Bottom Solder Mask Assembly Plane Thermal Thermal Padstack Name Padstack Name
Lead Ø Hole Pad Pad Pad Top & Bot Top & Bot Anti-Pad ID x OD Spoke Circular Land Square Land
12 20 40 40 40 40 40 50 40x50 9 c40h20 s40h20
14 22 42 42 42 42 42 54 42x54 10 c42h22 s42h22
16 24 44 44 44 44 44 56 44x56 10 c44h24 s44h24
18 26 46 46 46 46 46 58 46x58 11 c46h26 s46h26
20 28 48 48 48 48 48 60 48x60 11 c48h28 s48h28
22 30 50 50 50 50 50 62 50x62 11 c50h30 s50h30
24 31 52 52 52 52 52 62 51x62 12 c52h31 s52h31
26 33 54 54 54 54 54 64 53x64 12 c54h33 s54h33
28 35 56 56 56 56 56 66 55x66 13 c56h35 s56h35
30 37 58 58 58 58 58 68 57x68 13 c58h37 s58h37
31 39 60 60 60 60 60 70 59x70 13 c60h39 s60h39
33 41 62 62 62 62 62 74 61x74 14 c62h41 s62h41
35 43 64 64 64 64 64 76 63x76 14 c64h43 s64h43
37 45 68 68 68 68 68 78 65x78 15 c68h45 s68h45
39 47 70 70 70 70 70 80 67x80 15 c70h47 s70h47
41 49 74 74 74 74 74 82 69x82 16 c74h49 s74h49
43 51 76 76 76 76 76 84 71x84 16 c76h51 s76h51
45 53 80 80 80 80 80 86 73x86 16 c80h53 s80h53
47 55 82 82 82 82 82 88 75x88 17 c82h55 s82h55
49 57 86 86 86 86 86 90 77x90 17 c86h57 s86h57
51 59 88 88 88 88 88 92 79x92 17 c88h59 s88h59
53 61 92 92 92 92 92 96 81x96 18 c92h61 s92h61
55 63 94 94 94 94 94 98 83x98 18 c94h63 s94h63
57 65 98 98 98 98 98 100 85x100 19 c98h65 s98h65
59 67 100 100 100 100 100 102 87x102 19 c100h67 s100h67
Note: All Plated & Non-plated Through-hole Padstack Values are in 1 Mil increments

PCB Libraries, Inc.
Millimeter Proportional PTH Padstacks
Max Finished Top Inner Bottom Mask Assembly Plane Thermal Thermal Padstack Name Padstack Name
Lead Ø Hole Pad Pad Pad Top & Bot Top & Bot Anti-Pad ID x OD Spoke Circular Land Square Land
0.30 0.50 1.00 1.00 1.00 1.00 1.00 1.25 1x1.25 0.23 c100h50 s100h50
0.35 0.55 1.05 1.05 1.05 1.05 1.05 1.35 1.05x1.35 0.25 c105h55 s105h55
0.40 0.60 1.10 1.10 1.10 1.10 1.10 1.40 1.1x1.4 0.26 c110h60 s110h60
0.45 0.65 1.15 1.15 1.15 1.15 1.15 1.45 1.15x1.45 0.27 c115h65 s115h65
0.50 0.70 1.20 1.20 1.20 1.20 1.20 1.50 1.2x1.5 0.28 c120h70 s120h70
0.55 0.75 1.25 1.25 1.25 1.25 1.25 1.55 1.25x1.55 0.29 c125h75 s125h75
0.60 0.80 1.30 1.30 1.30 1.30 1.30 1.60 1.3x1.6 0.30 c130h80 s130h80
0.65 0.85 1.35 1.35 1.35 1.35 1.35 1.65 1.35x1.65 0.31 c135h85 s135h85
0.70 0.90 1.40 1.40 1.40 1.40 1.40 1.70 1.4x1.7 0.32 c140h90 s140h90
0.75 0.95 1.45 1.45 1.45 1.45 1.45 1.75 1.45x1.75 0.33 c145h95 s145h95
0.80 1.00 1.50 1.50 1.50 1.50 1.50 1.80 1.5x1.8 0.34 c150h100 s150h100
0.85 1.05 1.60 1.60 1.60 1.60 1.60 1.90 1.55x1.9 0.36 c160h105 s160h105
0.90 1.10 1.65 1.65 1.65 1.65 1.65 1.95 1.6x1.95 0.37 c165h110 s165h110
0.95 1.15 1.75 1.75 1.75 1.75 1.75 2.00 1.65x2 0.38 c175h115 s175h115
1.00 1.20 1.80 1.80 1.80 1.80 1.80 2.05 1.7x2.05 0.38 c180h120 s180h120
1.05 1.25 1.90 1.90 1.90 1.90 1.90 2.10 1.75x2.1 0.39 c190h125 s190h125
1.10 1.30 1.95 1.95 1.95 1.95 1.95 2.15 1.8x2.15 0.40 c195h130 s195h130
1.15 1.35 2.05 2.05 2.05 2.05 2.05 2.20 1.85x2.2 0.41 c205h135 s205h135
1.20 1.40 2.10 2.10 2.10 2.10 2.10 2.25 1.9x2.25 0.42 c210h140 s210h140
1.25 1.45 2.20 2.20 2.20 2.20 2.20 2.30 1.95x2.3 0.43 c220h145 s220h145
1.30 1.50 2.25 2.25 2.25 2.25 2.25 2.35 2x2.35 0.44 c225h150 s225h150
1.35 1.55 2.35 2.35 2.35 2.35 2.35 2.45 2.05x2.45 0.46 c235h155 s235h155
1.40 1.60 2.40 2.40 2.40 2.40 2.40 2.50 2.1x2.5 0.47 c240h160 s240h160
1.45 1.65 2.50 2.50 2.50 2.50 2.50 2.55 2.15x2.55 0.48 c250h165 s250h165
1.50 1.70 2.55 2.55 2.55 2.55 2.55 2.60 2.2x2.6 0.49 c255h170 s255h170
Note: All Plated & Non-plated Through-hole Padstack Values are in 0.01 Millimeter increments

PCB Libraries, Inc.
Proportional PTH Padstacks
The larger the hole size the larger the annular ring on the land but the Plane Anti-pad and the
Thermal Relief maintain strict fabrication DRC rules to minimize the clearance and maximize
the plane copper. For large hole sizes, the land size is larger than the Plane Clearance.
Note: Component manufacturer’s often provide hole size recommendations but not pad sizes

PCB Libraries, Inc.
Plated Through Holes

PCB Libraries, Inc.
Plated Through Holes

PCB Libraries, Inc.
Plated Through Vias
All values in Mils (mm)
Hole Size Tolerance + 0/- 1 (0.25)

Trace to Land Space 4 (0.1) 5 (0.12) Registration Tolerance ± 3 (0.075)
6 (0.15) Min.
Ground Plane
Core Shifted Layer 2 (0.05) Min.
Prepreg 4 (0.1)
10 (0.25) Trace Width
Core 8 (0.2)
Voltage Plane
20 (0.5)

PCB Libraries, Inc.
Plated Through Vias
PCB cross-section Illustration of registration tolerance

PCB Libraries, Inc.
Mil Plated Through Vias
VIA Name Top Pad Dia. Inner Pad Dia. Bottom Pad Dia. Hole Size Plane Anti-Pad Solder Mask Thermal Relief
VIA16-06-26 16 16 16 6 26 0 None
VIA16-08-26 16 16 16 8 26 0 None
VIA18-08-28 18 18 18 8 28 0 None
VIA20-08-30 20 20 20 8 30 0 None
VIA20-10-28 20 20 20 10 28 0 None
VIA22-10-30 22 22 22 10 30 0 None
VIA24-10-31 24 24 24 10 31 0 None
VIA26-10-33 26 26 26 10 33 0 None
VIA22-12-31 22 22 22 12 31 0 None
VIA24-12-33 24 24 24 12 33 0 None
VIA26-12-35 26 26 26 12 35 0 None
VIA28-12-37 28 28 28 12 37 0 None
VIA24-14-37 24 24 24 14 37 0 None
VIA26-14-39 26 26 26 14 39 0 None
VIA28-14-39 28 28 28 14 39 0 None
VIA30-14-41 30 30 30 14 41 0 None
VIA26-16-39 26 26 26 16 39 16 None
VIA28-16-41 28 28 28 16 41 16 None
VIA30-16-41 30 30 30 16 41 16 None
VIA31-16-43 31 31 31 16 43 16 None
VIA30-18-41 30 30 30 18 41 18 None
VIA31-18-45 31 31 31 18 45 18 None
VIA33-18-45 33 33 33 18 45 18 None
VIA35-18-47 35 35 35 18 47 18 None
VIA37-18-49 37 37 37 18 49 18 None
VIA31-20-43 31 31 31 20 43 20 None
VIA33-20-47 33 33 33 20 47 20 None
VIA35-20-47 35 35 35 20 47 20 None
Note: All Plated & Non-plated Through-hole Padstack Values are in 1 Mil increments

PCB Libraries, Inc.
Millimeter Plated Through Vias
VIA Name Top Pad Dia Inner Pad Dia Bottom Pad Dia Hole Size Plane Anti-Pad Solder Mask Thermal Relief
VIA40-15-65 0.40 0.40 0.40 0.15 0.65 0.00 None
VIA40-20-65 0.40 0.40 0.40 0.20 0.65 0.00 None
VIA45-20-70 0.45 0.45 0.45 0.20 0.70 0.00 None
VIA50-20-75 0.50 0.50 0.50 0.20 0.75 0.00 None
VIA50-25-70 0.50 0.50 0.50 0.25 0.70 0.00 None
VIA55-25-75 0.55 0.55 0.55 0.25 0.75 0.00 None
VIA60-25-80 0.60 0.60 0.60 0.25 0.80 0.00 None
VIA65-25-85 0.65 0.65 0.65 0.25 0.85 0.00 None
VIA55-30-80 0.55 0.55 0.55 0.30 0.80 0.00 None
VIA60-30-85 0.60 0.60 0.60 0.30 0.85 0.00 None
VIA65-30-90 0.65 0.65 0.65 0.30 0.90 0.00 None
VIA70-30-95 0.70 0.70 0.70 0.30 0.95 0.00 None
VIA60-35-95 0.60 0.60 0.60 0.35 0.95 0.00 None
VIA65-35-100 0.65 0.65 0.65 0.35 1.00 0.00 None
VIA70-35-100 0.70 0.70 0.70 0.35 1.00 0.00 None
VIA75-35-105 0.75 0.75 0.75 0.35 1.05 0.00 None
VIA65-40-100 0.65 0.65 0.65 0.40 1.00 0.40 None
VIA70-40-105 0.70 0.70 0.70 0.40 1.05 0.40 None
VIA75-40-105 0.75 0.75 0.75 0.40 1.05 0.40 None
VIA80-40-110 0.80 0.80 0.80 0.40 1.10 0.40 None
VIA75-45-105 0.75 0.75 0.75 0.45 1.05 0.45 None
VIA80-45-115 0.80 0.80 0.80 0.45 1.15 0.45 None
VIA85-45-115 0.85 0.85 0.85 0.45 1.15 0.45 None
VIA90-45-120 0.90 0.90 0.90 0.45 1.20 0.45 None
VIA95-45-125 0.95 0.95 0.95 0.45 1.25 0.45 None
VIA80-50-110 0.80 0.80 0.80 0.50 1.10 0.50 None
VIA85-50-120 0.85 0.85 0.85 0.50 1.20 0.50 None
VIA90-50-120 0.90 0.90 0.90 0.50 1.20 0.50 None
Note: All Plated & Non-plated Through-hole Padstack Values are in 0.05 Millimeter increments

PCB Libraries, Inc.
Mil Proportional NPTH Padstacks
Finished Top Inner Bottom Plane Solder Mask Assembly Keep-out Padstack
Hole Pad Pad Pad Anti-Pad Top & Bot Top & Bot Diameter Name
20 10 10 10 49 20 20 43 c8hn20
22 10 10 10 53 22 22 45 c8hn22
24 20 20 20 55 24 24 47 c20hn24
26 20 20 20 57 26 26 49 c50hn65
28 20 20 20 59 28 28 51 c50hn70
30 20 20 20 61 30 30 53 c50hn75
31 20 20 20 63 31 31 55 c50hn80
33 20 20 20 65 33 33 57 c50hn85
35 20 20 20 67 35 35 59 c50hn90
37 20 20 20 69 37 37 61 c50hn95
39 20 20 20 71 39 39 63 c50hn100
41 20 20 20 75 41 41 65 c50hn105
43 40 40 40 77 43 43 67 c100hn110
45 40 40 40 79 45 45 69 c100hn115
47 40 40 40 81 47 47 71 c100hn120
49 40 40 40 83 49 49 73 c100hn125
51 40 40 40 85 51 51 75 c100hn130
53 40 40 40 87 53 53 77 c100hn135
55 40 40 40 89 55 55 79 c100hn140
57 40 40 40 91 57 57 81 c100hn145
59 40 40 40 93 59 59 83 c100hn150
61 40 40 40 96 61 61 85 c100hn155
63 40 40 40 98 63 63 87 c100hn160
Non-plated holes with no annular ring are used for plastic alignment pegs
All Non-plated Through-hole Padstack Values are in 2 mil increments

PCB Libraries, Inc.
Millimeter Proportional NPTH Padstacks
Finished Mounted Inner Opposite Plane Solder Mask Assembly Keep-out Padstack
Hole Pad Pad Pad Anti-Pad Top & Bot Top & Bot Diameter Name
0.50 0.25 0.25 0.25 1.25 0.50 0.50 1.10 c25hn50
0.55 0.25 0.25 0.25 1.35 0.55 0.55 1.15 c25hn55
0.60 0.50 0.50 0.50 1.40 0.60 0.60 1.20 c50hn60
0.65 0.50 0.50 0.50 1.45 0.65 0.65 1.25 c50hn65
0.70 0.50 0.50 0.50 1.50 0.70 0.70 1.30 c50hn70
0.75 0.50 0.50 0.50 1.55 0.75 0.75 1.35 c50hn75
0.80 0.50 0.50 0.50 1.60 0.80 0.80 1.40 c50hn80
0.85 0.50 0.50 0.50 1.65 0.85 0.85 1.45 c50hn85
0.90 0.50 0.50 0.50 1.70 0.90 0.90 1.50 c50hn90
0.95 0.50 0.50 0.50 1.75 0.95 0.95 1.55 c50hn95
1.00 0.50 0.50 0.50 1.80 1.00 1.00 1.60 c50hn100
1.05 0.50 0.50 0.50 1.90 1.05 1.05 1.65 c50hn105
1.10 1.00 1.00 1.00 1.95 1.10 1.10 1.70 c100hn110
1.15 1.00 1.00 1.00 2.00 1.15 1.15 1.75 c100hn115
1.20 1.00 1.00 1.00 2.05 1.20 1.20 1.80 c100hn120
1.25 1.00 1.00 1.00 2.10 1.25 1.25 1.85 c100hn125
1.30 1.00 1.00 1.00 2.15 1.30 1.30 1.90 c100hn130
1.35 1.00 1.00 1.00 2.20 1.35 1.35 1.95 c100hn135
1.40 1.00 1.00 1.00 2.25 1.40 1.40 2.00 c100hn140
1.45 1.00 1.00 1.00 2.30 1.45 1.45 2.05 c100hn145
1.50 1.00 1.00 1.00 2.35 1.50 1.50 2.10 c100hn150
1.55 1.00 1.00 1.00 2.45 1.55 1.55 2.15 c100hn155
1.60 1.00 1.00 1.00 2.50 1.60 1.60 2.20 c100hn160
1.65 1.00 1.00 1.00 2.55 1.65 1.65 2.25 c100hn165
1.70 1.00 1.00 1.00 2.60 1.70 1.70 2.30 c100hn170
Non-plated holes with no annular ring are used for plastic alignment pegs
All Non-plated Through-hole Padstack Values are in 0.05 mm increments

PCB Libraries, Inc.
Mounting Holes
 Mounting holes are on every PCB design

 Mounting hardware normally consists of these 4 items:
 Phillips Head Screw
 Lock Washer
 Flat Washer
 Hex Nut
 There are 4 types of mounting holes:
 Supported – Plated through with annular ring
 Supported – Plated through with annular ring with vias
 Unsupported – Non-plated and with copper pads
 Tooling Holes and Plastic Peg Alignment – Non-plated w/no pads
 The supported mounting hole usually gets tied to the GND
plane without a Thermal Relief pattern in the padstack
PCB Libraries, Inc.
Metal Hardware Mounting Holes
 Non-plated (unsupported) holes have no connection to an
internal GND plane layer, however vias can be used for GND
 Non-plated holes used for Mounting Hardware require a
Donut Pad so that the ID is recessed from the hole
 The Plated and Non-plated mounting hole Pad Size requires
a slop tolerance for the flat washer (See Picture)

PCB Libraries, Inc.
Mounting Holes
 Vias are added to mounting holes to secure the GND
connection and crush prevention during torque
 The average via size in a mounting hole is 20 Mil
 No need for Thermal Reliefs on MTG Holes or vias
 Plane Clearance is 40 Mil (1 mm) larger than hole size
 The “Loose Fit” mounting holes are normally used on large
boards greater than 4 Inches (100 mm) length or width
 “Tight Fit” mounting holes are used for smaller board sizes
 There are 3-Tiers for the Mounting Hole family, but the
only difference is the “Placement Courtyard Excess”
 Least – 5 Mil (0.12 mm) annular
 Nominal – 10 Mil (0.25 mm) annular
 Most – 20 Mil (0.50 mm) annular

PCB Libraries, Inc.
ISO Loose Fit Mounting Holes Mils
ISO (metric) Nut, Screw & Washer Hardware Sizes Mil Units
Screw Size Pan Hex Flat Washer Lock
Dia x Thread Head Nut Washer ID Washer
M2 x 0.4 157 182 209 87 173
M2.5 x 0.45 197 227 268 107 200
M3 x 0.5 236 250 287 126 244
M3.5 x 0.6 276 273 330 150 272
ISO (metric) Hardware w/Plated & Non-plated Though Hole Padstack Data – Loose Fit – Mil Units
Pan Head Hardware on Placement Hole Top Inner Bottom Solder Plane Thermal
Screw Size PCB Courtyard Size Pad Pad Pad Mask Anti-Pad Relief
M2 x 0.4 Pan Head 190 90 170 170 170 170 130 None
M2 x 0.4 Flat Washer 236 90 216 216 216 216 130 None
M2.5 x 0.45 Pan Head 232 112 212 212 212 212 152 None
M2.5 x 0.45 Flat Washer 300 112 280 280 280 280 152 None
M3 x 0.5 Pan Head 276 138 256 256 256 256 178 None
M3.5 x 0.6 Pan Head 311 154 291 291 291 291 194 None

PCB Libraries, Inc.
ISO Loose Fit Mounting Holes Millimeters
ISO (metric) Nut, Screw & Washer Hardware Sizes Metric

M2 x 0.4 4.00 4.62 5.30 2.20 4.40
M2.5 x 0.45 5.00 5.77 6.80 2.70 5.10
M3 x 0.5 6.00 6.35 7.30 3.20 6.20
M3.5 x 0.6 7.00 6.93 8.40 3.80 6.90
ISO (metric) Hardware w/Plated & Non-plated Though Hole Padstack Data – Loose Fit – Metric Units
M2 x 0.4 Pan Head 4.80 2.30 4.30 4.30 4.30 4.30 3.30 None
M2 x 0.4 Flat Washer 6.00 2.30 5.50 5.50 5.50 5.50 3.30 None
M2.5 x 0.45 Pan Head 5.90 2.85 5.40 5.40 5.40 5.40 3.85 None
M2.5 x 0.45 Flat Washer 7.60 2.85 7.10 7.10 7.10 7.10 3.85 None
M3 x 0.5 Pan Head 7.00 3.50 6.50 6.50 6.50 6.50 4.50 None
M3.5 x 0.6 Pan Head 7.90 3.90 7.40 7.40 7.40 7.40 4.90 None

PCB Libraries, Inc.
ISO Tight Fit Mounting Holes Mils
ISO (metric) Nut, Screw & Washer Hardware Sizes Mil Units
M2 x 0.4 157 182 209 87 173
M2.5 x 0.45 197 227 268 107 200
M3 x 0.5 236 250 287 126 244
M3.5 x 0.6 276 273 330 150 272
ISO (metric) Hardware w/Plated & Non-plated Though Hole Padstack Data – Tight Fit – Mil Units
M2 x 0.4 Pan Head 190 82 170 170 170 170 122 None
M2.5 x 0.45 Pan Head 232 104 212 212 212 212 144 None
M3 x 0.5 Pan Head 276 130 256 256 256 256 170 None
M3.5 x 0.6 Pan Head 311 146 291 291 291 291 186 None

PCB Libraries, Inc.
ISO Tight Fit Mounting Holes Millimeters
ISO (metric) Nut, Screw & Washer Hardware Sizes Metric

M2 x 0.4 4.00 4.62 5.30 2.20 4.40
M2.5 x 0.45 5.00 5.77 6.80 2.70 5.10
M3 x 0.5 6.00 6.35 7.30 3.20 6.20
M3.5 x 0.6 7.00 6.93 8.40 3.80 6.90
ISO (metric) Hardware w/Plated & Non-plated Though Hole Padstack Data – Tight Fit – Metric Units
M2 x 0.4 Pan Head 4.60 2.10 4.30 4.30 4.30 4.30 3.10 None
M2.5 x 0.45 Pan Head 5.70 2.65 5.40 5.40 5.40 5.40 3.65 None
M3 x 0.5 Pan Head 6.80 3.30 6.50 6.50 6.50 6.50 4.30 None
M3.5 x 0.6 Pan Head 7.70 3.70 7.40 7.40 7.40 7.40 4.70 None

PCB Libraries, Inc.
ANSI Loose Fit Mounting Holes Mils
ANSI Nut, Screw and Washer Hardware Chart Mil Units

Screw Pan Hex Flat Washer Lock
Size Head Nut Washer ID Washer
#2-48 167 217 250 94 4.36
#4-40 219 289 375 125 172
#6-32 270 361 438 156 250
#8-32 322 397 500 188 293
ANSI Hardware w/Plated & Non-plated Though Hole Padstack Data – Loose Fit – Mil Units
#2 - 48 Pan Head 197 96 177 177 177 177 136 None
#2 - 48 Flat Washer 292 96 272 272 272 272 136 None
#4 - 40 Pan Head 260 146 240 240 240 240 186 None
#4 - 40 Flat Washer 418 146 398 398 398 398 186 None
#6 - 32 Pan Head 308 154 287 287 287 287 194 None
#6 - 32 Flat Washer 492 154 472 472 472 472 194 None
#8 - 32 Pan Head 358 180 338 338 338 338 200 None
#8 - 32 Flat Washer 562 180 543 543 543 543 220 None

PCB Libraries, Inc.
ANSI Loose Fit Mounting Holes Millimeters
ANSI Nut, Screw and Washer Hardware Chart Metric Units

#2-48 4.24 5.51 6.35 2.39 4.36
#4-40 5.56 7.34 9.52 3.18 5.31
#6-32 6.85 9.17 11.13 3.96 6.35
#8-32 8.18 10.08 12.70 4.78 7.44
ANSI Hardware w/Plated & Non-plated Though Hole Padstack Data – Loose Fit – Metric Units
#2 - 48 Pan Head 5.00 2.45 4.50 4.50 4.50 4.50 3.45 None
#2 - 48 Flat Washer 7.40 2.45 6.90 6.90 6.90 6.90 3.45 None
#4 - 40 Pan Head 6.60 3.70 6.10 6.10 6.10 6.10 4.70 None
#4 - 40 Flat Washer 10.60 3.70 10.10 10.10 10.10 10.10 4.70 None
#6 - 32 Pan Head 7.80 3.90 7.30 7.30 7.30 7.30 4.90 None
#6 - 32 Flat Washer 12.50 3.90 12.00 12.00 12.00 12.00 4.90 None
#8 - 32 Pan Head 9.10 4.60 8.60 8.60 8.60 8.60 5.60 None
#8 - 32 Flat Washer 14.30 4.60 13.80 13.80 13.80 13.80 5.60 None

PCB Libraries, Inc.
ANSI Tight Fit Mounting Holes Mils
ANSI Nut, Screw and Washer Hardware Chart Mil Units

#2-48 167 217 250 94 4.36
#4-40 219 289 375 125 172
#6-32 270 361 438 156 250
#8-32 322 397 500 188 293
ANSI Hardware w/Plated & Non-plated Though Hole Padstack Data – Tight Fit - Mil Units
#2 - 48 Pan Head 190 88 170 170 170 170 128 None
#2 - 48 Flat Washer 284 88 104 104 104 104 128 None
#4 - 40 Pan Head 244 130 224 224 224 224 170 None
#4 - 40 Flat Washer 402 130 382 382 382 382 170 None
#6 - 32 Pan Head 296 142 276 276 276 276 182 None
#6 - 32 Flat Washer 480 142 460 460 460 460 182 None
#8 - 32 Pan Head 350 169 330 330 330 330 209 None
#8 - 32 Flat Washer 550 169 532 532 532 532 209 None

PCB Libraries, Inc.
ANSI Tight Fit Mounting Holes Millimeters
ANSI Nut, Screw and Washer Hardware Chart Metric Units

#2-48 4.24 5.51 6.35 2.39 4.36
#4-40 5.56 7.34 9.52 3.18 5.31
#6-32 6.85 9.17 11.13 3.96 6.35
#8-32 8.18 10.08 12.70 4.78 7.44
ANSI Hardware w/Plated & Non-plated Though Hole Padstack Data – Tight Fit - Metric Units
#2 - 48 Pan Head 4.80 2.25 4.30 4.30 4.30 4.30 3.25 None
#2 - 48 Flat Washer 7.20 2.25 6.70 6.70 6.70 6.70 3.25 None
#4 - 40 Pan Head 6.20 3.30 5.70 5.70 5.70 5.70 4.30 None
#4 - 40 Flat Washer 10.20 3.30 9.70 9.70 9.70 9.70 4.30 None
#6 - 32 Pan Head 7.50 3.60 7.00 7.00 7.00 7.00 4.60 None
#6 - 32 Flat Washer 12.20 3.60 11.7 11.70 11.70 11.70 4.60 None
#8 - 32 Pan Head 8.90 4.30 8.40 8.40 8.40 8.40 5.30 None
#8 - 32 Flat Washer 14.10 4.30 13.5 13.50 13.50 13.50 5.30 None

PCB Libraries, Inc.
Padstack Naming Convention
 The first character in the padstack naming convention

defines the outer layer land (pad) shape
 The characters are “lower case” as the default
 There are six basic land shape identifiers
 c = Circular
 s = Square
 r = Rectangle
 b = Oblong
 d = D-shape (Square one end & Circular on other end)
 u = User defined contour (Irregular shape)
 Note: The “b” was used for Oblong because the letter
“o” can easily be confused with the character zero “0”

PCB Libraries, Inc.
Padstack Name Assumptions
 Solder Mask is 1:1 scale of the land size
 Paste Mask is 1:1 scale of the land size
 Inner Layer Land is the same shape as the outer layer land
 The Primary and Secondary lands are the same size
 The inner layer land shapes are Circular
 Vias are Circular
 Mounting Holes are Circular
 Thermal relief OD is the same size as Plane Clearance
 Thermal ID, OD and Spoke sizes use “Proportional Chart”
 Plane Clearance Anti-pad size use “Proportional Chart”
 Thermals have 4 spokes
 Illegal characters: “ ” , ; : / \ [ ] ( ) . { } * & % # $ ! @ ^ =

PCB Libraries, Inc.
Padstack Name Single Modifiers
 n = Non-plated Hole
 z = Inner Layer land dimension if different than primary layer
 x = Special modifier used alone or following other modifiers for
lands on opposite side to primary layer land dimension
 t = Thermal Relief; if different than standard padstack
 m = Solder Mask if different than default 1:1 scale of land
 p = Solder Paste if different than default 1:1 scale of land
 y = Plane Clearance if the value is different than Thermal OD
 o = Offset Land Origin
 k = Keep-out
 r = Radius for Rounded Rectangular Land Shape
 c = Chamfer for Chamfered Rectangular Land Shape

PCB Libraries, Inc.
Padstack Name Double Modifiers
 ts = Thermal Square; if different than the top side land shape

and dimensions
 sw = Thermal spoke width
 zs = Inner Layer Land Shape is Square (Note: The default is
circular)
 m0 = No Solder Mask
 mxc = Solder Mask Opposite Side Circular
 mx0 = Solder Mask Opposite Side No Solder Mask
 xc = Opposite Side Circular
 vs = Via with Square land
 hn = Hole Non-plated

PCB Libraries, Inc.
Metric Unit Padstack Name Examples
 c150h90 = Default padstack with a 1.50 mm circular land with

a 0.90 mm hole (no modifiers used)
 c150h90z140 = Inner layer land is smaller than external lands
1.40 mm or 0.10 mm smaller
 c150h90z140x170 = Opposite side land is larger than top side
land 1.70 mm or 0.20 mm larger
 c150h90z140x170m165mx185 = Solder mask opening for top
and bottom lands 0.15 mm larger for each
 c150h90z140x170m165mx185y300 = Plane clearance anti-pad
diameter is 3.00 mm
 c150h90z140x170m165mx185y300t150_180_40 = Thermal ID
1.50 mm, OD 1.80 mm, Spoke Width 0.40, Anti-pad 1.80
PCB Libraries, Inc.
Mil Unit Padstack Name Examples
 c60h39 = Default padstack with a 60 Mil circular land with a

39 Mil hole (no modifiers used)
 c60h39z55 = Inner layer land is smaller than external lands
55 Mil or 5 Mil smaller
 c60h39z55x68 = Opposite side land is larger than top side
land 68 Mil or 8 Mil larger
 c60h39z55x68m66mx72 = Solder mask opening for top and
bottom lands 6 Mil larger on top and 12 Mil on Bottom side
 c60h39z55x68m66mx72y120 = Plane clearance anti-pad
diameter is 120 Mil
 c60h39z55x68m66mx72y120t60_70_16 = Thermal ID 60 Mil
X OD 70 Mil, Spoke Width 16 Mil, Anti-pad 120 Mil
PCB Libraries, Inc.
Placement Courtyard
 IPC-7351C Placement Courtyard Oversize Maximum tolerance
 Least – 5 Mil (0.12 mm) Note: Current IPC-7351B – 4 Mils (0.1 mm)
 Nominal – 10 Mil (0.25 mm) for component body greater than 80 Mil (2 mm)
 Nominal – 5 Mil (0.12 mm) for component body less than 80 Mil (2 mm)
 Most – 20 Mil (0.50 mm) No Most Environment for components < 80 Mil
 Placement Courtyard for most Connectors is 20 mil (0.5 mm)
OK
NOT OK

PCB Libraries, Inc.
Silkscreen Outlines
 Never be located under the component because they are
covered up during assembly and do not provide any function
 J-STD-001 Assembly Requirements Section 9.2 – Silkscreen
Polarity Marking, Reference Designators, Revision and Serial
Numbers Shall be visible after assembly
 Mapped to the maximum component body outline
 Pad to silkscreen rule overrides maximum component body
 Used for post assembly placement registration accuracy
 The line width and pad to line gap are normally the same
 Should always be located inside the Placement Courtyard
 Only one line width should be used throughout PCB library

PCB Libraries, Inc.
3-Tier Silkscreen Outlines
 The preliminary recommendation for 3-Tier line widths and

Silkscreen to Pad Gap are illustrated in the pictures below
representing a SOT23-6 component package.
 The Silkscreen to Pad Clearance is the same as the Line Width
Least Density Level Nominal Density Level Most Density Level

0.10 mm Line Width 0.12 mm Line Width 0.2 mm Line Width

PCB Libraries, Inc.
Assembly Outlines
 Closed Polygon with a 0.10 mm line width
 1.00 mm 45° chamfer corner to indicate pin 1 location
 Outline shape mapped to maximum component body size

PCB Libraries, Inc.
Examples of 2-Pin Chip and Molded Outlines

PCB Libraries, Inc.
0603 (EIA 0201) Chip Capacitor

PCB Libraries, Inc.
0603 (EIA 0201) Paste Mask Volume

PCB Libraries, Inc.
Examples of 2-Pin Chip 3D Models
Capacitor Resistor Inductor
LED Diode Fuse

PCB Libraries, Inc.
Examples of 2-Pin Molded Body 3D Models
Polarized Capacitor Polarized Diode Fuse
Non-polarized Capacitor Non-polarized Diode Resistor
Inductor Precision Inductor LED

PCB Libraries, Inc.
Example of SOT23 Outlines
Component Various Silkscreen Outlines with Polarity on Pin 1
Courtyard
Assembly 3D IDF Outline IDF Model
REFDES

PCB Libraries, Inc.
Example of SOT 3D Models
SOT23 3-pin SOT23 5-pin SOT23 6-pin
SOT223 SOT143

PCB Libraries, Inc.
Example of QFN & SON Outlines
Courtyard Silkscreen w/Polarity
Assembly
REFDES
IDF Model 3D IDF Outline

PCB Libraries, Inc.
Examples of QFN, PQFN, SON & PSON 3D Models
QFN QFN PQFN PQFN

Rectangle Lead D-shape Lead Rectangle Lead D-shape Lead
SON SON PSON PSON

Rectangle Lead D-shape Lead Rectangle Lead D-shape Lead

PCB Libraries, Inc.
Example of QFP & SOP Outlines
Silkscreen w/Polarity
Courtyard
Assembly
REFDES

PCB Libraries, Inc.
Examples of QFP & SOP 3D Models
Quad Flat Pack QFP w/Thermal Tab Ceramic QFP
Small Outline Package SOP w/Thermal Tab Ceramic FP

PCB Libraries, Inc.
Example of Grid Array Outlines, BGA CGA LGA
Courtyard Silkscreen w/Polarity Assembly
REFDES

PCB Libraries, Inc.
Examples of Grid Array 3D Models
Ball Grid Array Column Grid Array
Land Grid Array Land Grid Array

Round Leads Square Leads

PCB Libraries, Inc.
Example of Axial & Radial Lead Outlines
Silkscreen – Capacitor Silkscreen - Resistor
Courtyard Assembly
REFDES

PCB Libraries, Inc.
Examples of Axial & Radial Lead 3D Models
Non-polarized Polarized
Capacitor Capacitor Diode Resistor
Non-polarized Polarized Disc LED

Capacitor Capacitor Capacitor

PCB Libraries, Inc.
Silkscreen Reference Designators
 Silkscreen reference designators are normally placed inside

the courtyard during library construction and typically
located on the land pattern origin. After part placement has
been approved, the silkscreen ref des are relocated outside
the component body so they are visible after assembly.
 The ref des line width is normally 10% of the text height
 In the past, we made all silkscreen reference designators 60
Mil (1.5 mm) height. Fabrication technology has improved
it’s time to support a 3-Tier reference designator option
 New 3-Tier recommendations:
REFDES
 Least Density Level – 1.0 mm Height
 Nominal Density Level – 1.2 mm Height
 Most Density Level – 1.5 mm Height

PCB Libraries, Inc.
Assembly Reference Designators
 The default assembly Ref Des height is 2.00 mm

 For miniature components the text height must be scalable to fit
 The default rotation of the assembly reference designator is
associated with the component body length
0.6 x 0.3 1.0 x 0.5 1.6 x 0.8 2.0 x 1.2
0201 0402 0603 0805
REFDES REFDES
Ref Des Height
REFDES REFDES
Ref Des Height
0.50 mm 0.70 mm Ref Des Height
Ref Des Height
1.00 mm
0.12 mm
These Chip assembly Ref Des are scaled down to fit inside assembly outlines

PCB Libraries, Inc.
Common Reference Designators

PCB Libraries, Inc.
Local Fiducials for BGA and QFP
 Local Fiducials have been used only on fine pitch QFP and BGA
Footprints (land patterns)
 Fine pitch QFP = Less than 0.625 mm pin pitch
 Fine pitch BGA = Less than 0.80 mm ball pitch
 Future Local Fiducial sizes will be:
 Level A (Most) = 40 mil (1.0 mm) with 80 mil (2.0 mm) solder mask & keep-out
 Level B (Nominal) = 30 mil (0.75 mm) with 60 (1.5 mm) solder mask & keep-out
 Level C (Least) = 20 mil (0.5 mm) with 40 mil (1.0 mm) solder mask & keep-out

PCB Libraries, Inc.
Zero Component Orientation
 In 2005 IPC-7351 released the first zero component orientation
standard regarding the location of “Pin 1”
 The goal was to define a consistent method for land pattern
creation with the main objective to define a “One World CAD
Library” to achieve the highest level of electronic product
development automation
 In May 2009 IEC land pattern committee voted and approved a
new zero component orientation and referred to IPC-7351 as
“Level A” and the new standard rotation “Level B”
 The EIA-481-D publishes documentation for component
packaging standards for tape & reel, tubes and trays and the
component orientation in the packaging should match the
orientation of land pattern creation, but component
manufacturer’s don’t always adhere to the EIA-481-D
PCB Libraries, Inc.
Zero Component Orientation – Level A & B
Zero Orientation with Pin 1 in Upper Left Corner Introduced
in 2007 in the IPC-7351A Publication – IPC-7351C “Level A”
Zero Orientation with Pin 1 in Lower Left Corner Introduced

in 2009 in the IEC 61188-7 publication – IPC-7351C “Level B”

PCB Libraries, Inc.
0° Orientation
Rotate Counterclockwise
90° Orientation Mirror Image

PCB Libraries, Inc.
EIA-481-D Component Orientation
EIA-481-D standard tape

and reel pictures
quadrant designations
This picture represents zero component

orientation for PCB CAD tool libraries.
IPC-7351C Level A uses quadrant 2 for
zero component orientation. IEC, JEDEC
and IPC-7351C Level B use quadrant 1
for zero component orientation of Pin 1
PCB Libraries, Inc.
Note: IPC-7351C Level A uses quadrant 2. IEC and JEDEC use quadrant 1

PCB Libraries, Inc.

PCB Libraries, Inc.
Component Family IPC-7351C (Level A) IEC 61188-7 (Level B) EIA-481-D
Chip (All Families) Polarization On Left Polarization On Left Polarization On Left
Tantalum Capacitor Polarization On Left Polarization On Left Polarization On Right
Molded Body Diode Polarization On Left Polarization On Left Polarization On Left
SODFL Polarization On Left Polarization On Left Polarization On Left EIA Color Code:
MELF Polarization On Left Polarization On Left Polarization On Left
Aluminum Capacitor
Precision Inductors
Polarization On Left
Left
Left
Left
Green = Match
PLCC, LCC Upper Center Left Center Left Center
QFP & CQFP
Bump QFP Side
Upper Left
Upper Left
Lower Left
Lower Left
Upper Left
Upper Left
Red = No Match
Bump QFP Center
SOIC, SOP, CFP, SOJ
Upper Center
Upper Left
Left Center
Lower Left
Left Center
Lower Left Purple = IPC
BGA, LGA, CGA, PGA Upper Left Lower Left Lower Left
QFN Square
QFN Rectangle
Upper Left
Upper Left
Lower Left
Lower Left
Upper Left
Lower Left
Blue = IEC
Chip Array Upper Left Lower Left Lower Left
DFN Upper Left Lower Left Lower Right
SON Upper Left Lower Left Lower Right
SOT23, SOT223 Upper Left Lower Left Lower Right
SOT143 Upper Left Lower Left Lower Right
SOT343 Upper Left Lower Left Upper left
SOT89 Upper Left Lower Left Upper Right
SOTFL Upper Left Lower Left Lower Right
TO-252 Upper Left Lower Left Upper Left
TO-263 Upper Left Lower Left Upper Left
Oscillator (Multi-pin) Upper Left Lower Left Lower Left
Crystal (2-pin) Left Left Left
SMT Connectors Left Left Left
PTH Connectors Left Left Left
DIP Upper Left Lower Left Lower Left
SIP Upper Left Left
Axial Lead Polarization On Left Polarization On Left Polarization On Left
PCB Design Optimization
Radial Lead
Starts in the CADPolarization
Library On Left Polarization On Left
PCB Libraries, Inc.

PCB Libraries, Inc.

PCB Libraries, Inc.
Footprint Origins
 The land pattern origin is typically located at the center of gravity

of the component, but sometimes this is difficult to calculate with
irregular shaped components, so Pin 1 is used in these cases. Also
Pin 1 in most through-hole connectors.
 The centroid origin marking in the picture below is an unfilled
0.50 mm diameter circle with a 0.05 mm line width with a 0.70
mm crosshair for cursor alignment.

PCB Libraries, Inc.
3D Model Library Parts
 The PCB Library Expert has a 3D IDF Model Outline

& Height Attribute built into every PCB library part
to use as a mechanical drafting aid for the reduction
of errors in product packaging
 3D STEP Models have much more detail than 3D IDF

PCB Libraries, Inc.
Schematic Symbol Library Automation
 Our next big software programming project is Schematic Symbol

library automation & integration.

PCB Libraries, Inc.
Parts on Demand (POD) Coming Soon
 www.pcblibraries.com/pod/showpart.asp “Parts on Demand” (POD)

website that will sync with the Library Expert tool for uploading and
downloading FPX files will be on-line in October 2013.
 POD will also offer Schematic Symbols, Footprints & 3D models.

PCB Libraries, Inc.
Tom.Hausherr@PCBLibraries.com
www.PCBLibraries.com

PCB Design Optimization Starts in The CAD Library 6410371 PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

PCB Design Optimization Starts in The CAD Library 6410371 PDF

Uploaded by

Copyright:

Available Formats

PCB Design Optimization Starts in the CAD Library

PCB Libraries, Inc.

Metric Units Imperial Units

IPC Level A IPC Level B IPC Level C User-Defined Manufacturer

… … … Rectangular Oblong D-Shape … … … … … … … … …

… IPC IEC IPC IEC … … … … … … … … …

Drafting Options Design Rule Options