2338 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO.

10, OCTOBER 2013

Active Millimeter-Wave Phase-Shift Doherty Power

Amplifier in 45-nm SOI CMOS
Amir Agah, Student Member, IEEE, Hayg-Taniel Dabag, Student Member, IEEE, Bassel Hanafi,
Peter M. Asbeck, Fellow, IEEE, James F. Buckwalter, Member, IEEE, and Lawrence E. Larson, Fellow, IEEE

Abstract—A 45 GHz active phase-shift Doherty PA is proposed

and implemented in 45-nm SOI CMOS. The quarter wave-length
transmission line at the input of the auxiliary amplifier is replaced
by an amplifier, increasing the gain and PAE by more than 1 dB and
5%, while reducing the die area. Use of slow-wave coplanar waveg-
uides (S-CPW) improves the PAE and gain by approximately 3%
and 1 dB, and further reduces the die area. Two-stack FET am-
plifiers are used as the main and auxiliary amplifiers, allowing a
supply voltage of 2.5 V and increasing the output power. The ac-
tive phase-shift Doherty amplifier demonstrates a peak power gain
and PAE of 8 dB and 20% at 45 GHz. It occupies 0.45 mm , and
at 6-dB back-off power, the PAE is 21%.
Index Terms—Class AB, CMOS, device parasitic, impedance
matching, load pull, millimeter-wave, power amplifier, power com-
bining, power-added efficiency (PAE), reliability, transformer.

I. INTRODUCTION

W ITH the growth in applications of the millimeter-wave

spectrum for broadband terrestrial wireless communi-
cation, satellite radio and automotive radar, the need for fully
integrated high-power, high-efficiency millimeter-wave power
amplifiers (PAs) is growing. Traditionally, this field has been
dominated by III-V and SiGe technology due to the high gain
and high output power of these processes. However, the lower
cost and higher integration level offered by CMOS technology
has motivated research into CMOS mm-wave PA design. At the
same time, the low breakdown voltage and poor passive element
quality factor of silicon technology poses major challenges. Re-
cent work in SOI CMOS, e.g., 14.5 dBm saturated output power
and 25% PAE at 60 GHz with 65-nm SOI CMOS [1], 12.5 dBm
Psat and 15% PAE at 80 GHz [2] and 18.6-dBm Psat and 34%
PAE at 45 GHz with 45-nm SOI CMOS [3], shows that SOI
CMOS is becoming a realistic alternative to III-V and SiGe
technology for these applications.
Manuscript received December 27, 2012; revised May 15, 2013; ac-
cepted May 16, 2013. Date of publication July 03, 2013; date of current
version September 20, 2013. This paper was approved by Associate Editor
Jan Craninckx.
A. Agah, H.-T. Dabag, B. Hanafi, P. M. Asbeck, and J. F. Buckwalter are
with the Department of Electrical and Computer Engineering, University of Cal-
ifornia at San Diego, La Jolla, CA, 92093 USA (e-mail: aagah@ucsd.edu).
L. E. Larson was with the Department of Electrical and Computer Engi-
neering, University of California at San Diego, La Jolla, CA 92093-0407 USA.
He is now with the School of Engineering, Brown University, Providence, RI
02912 USA (e-mail: lawrence_larson@brown.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2013.2269854
Fig. 1. (a) Traditional Doherty amplifier. (b) Proposed active phase-shift
Doherty amplifier.
Most power amplifiers have high power-added efficiency
(PAE) at peak power levels, but the efficiency drops as the input
power decreases. However, modern communication systems
employ modulation techniques that exhibit high peak-to-av-
erage power ratios (PAPRs) and demand for amplifiers with
high efficiency over a wide power range is increasing. The
traditional Doherty power amplifier is one of the circuits that
satisfy this demand by providing peak efficiency at 6-dB back
off as well as peak power.
The integration of a millimeter-wave transmitter for radar,
guidance and high data rate satellite communication at 45 GHz
has encouraged research in high efficiency PAs that operate with
high-efficiency in back-off, and recent work has addressed the
design of Doherty power amplifiers at 45 GHz [4]. In this paper,
a modified Doherty PA is presented that addresses the limita-
tions of the traditional design. The results demonstrate improved
back-off PAE as well as higher gain for a mm-wave Si CMOS
PA. Block diagrams of the traditional Doherty PA is shown in
Fig. 1(a).
In Section II, the challenges of designing a fully integrated
Doherty PA for mm-wave applications are discussed and the
active phase-shift Doherty PA is proposed, shown in Fig. 1(b).

0018-9200 © 2013 IEEE

AGAH et al.: ACTIVE MILLIMETER-WAVE PHASE-SHIFT DOHERTY POWER AMPLIFIER IN 45-nm SOI CMOS 2339

Section III explains the FET stacking technique used to im-

prove output power. In Section IV, the slow-wave CPW is dis-
cussed and compared to the traditional ground shielded CPW.
In Section V, the design and implementation of a Doherty PA
with ground-shielded CPW and slow-wave CPW are presented
as well as the proposed active phase-shift Doherty PA. The cir-
cuit measurements are reported in Section VI along with a com-
parison to previous results.

II. FULLY INTEGRATED DOHERTY POWER AMPLIFIER

A. Review of Conventional Doherty Amplifier Design

A conventional Doherty amplifier consists of two power am- Fig. 2. Ideal drain efficiency of the conventional Doherty PA with different
biasing for the main and auxiliary amplifier. Drain current conduction angle is
plifiers—a main amplifier and an auxiliary (peaking) ampli- 110 for class-C operation.
fier—interconnected with two quarter-wavelength transmission
lines as shown in Fig. 1(a) [5]. The main amplifier is designed
to be on at all input power levels, while the auxiliary amplifier is . However, the efficiency of the aux-
only on at high input power levels. This is achieved by biasing iliary amplifier is not at its maximum until it reaches its peak
the auxiliary amplifier in class C and biasing the main amplifier output power, at which point, the overall efficiency peaks. Fig. 2
in class A. shows the simulated ideal drain efficiency of the Doherty PA as
The characteristic impedance of the transmission line at the a function of the normalized output power, assuming zero knee
output of the main amplifier is twice the load impedance. At low voltage for the transistors and lossless transmission lines. Fig. 2
input power levels (LP), when the auxiliary amplifier is off, the also includes the simulated efficiency of the Doherty PA for dif-
impedance seen by the main amplifier is: ferent classes of operation for the main and auxiliary amplifier
[9].
(1) In a conventional Doherty amplifier [5], the phase shift
needed for (5) is achieved by utilizing a quarter-wavelength
and as a result the voltage swing at the output of the main am- transmission line at the input of the auxiliary amplifier, and the
plifier at low input power is auxiliary amplifier is designed to have twice the transconduc-
tance of the main amplifier [5].
(2)
B. Design of a Fully-Integrated mm-Wave Doherty PA
where is the current swing at the output of the main am- The small size of the quarter wavelength transmission lines
plifier. The current of the main amplifier and are designed and the high of the CMOS transistors allows fabrication of
so that when , reaches its max- compact and fully integrated Doherty PAs at millimeter-wave
imum, which is frequencies. However, the low gain of the amplifiers at these
bands is a challenge. The maximum current gain of a single-
(3) stage amplifier is limited by , where is the short-circuit
current gain cutoff radian frequency. Assuming that
where is the power supply voltage of the main ampli-
, it can be shown that
fier and is the maximum . Since the voltage
swing is maximized, the efficiency of the main amplifier peaks (6)
as well.
Increasing the input power further increases above Considering 45 GHz as the operating frequency and
, and the auxiliary amplifier turns on. Assuming , a single-stage design provides roughly 14 dB power
infinite output impedance for the main and auxiliary amplifiers, gain. With the high losses of the passive elements in a standard
the voltage at the output of the main amplifier is [6], [7] Si technology, achieving more than 7 or 8-dB gain from a single
stage is difficult.
(4) Since ,where is the power gain
and DE is the drain efficiency, reducing the gain by only 2 dB
Considering that , if the output current of the reduces the PAE by approximately 13%, when the PA has the
auxiliary amplifier is set to initial gain of 6 dB. This PAE reduction is less than 1.5%, when
the PA has 16 dB of gain. So even a small increase in the gain of
(5) a PA can have a significant effect on the PAE, when the initial
gain is low.
and substituted into (4), then becomes independent of Additionally, the low quality factor of the passive ele-
and remains at its peak value in (3). As a result, the effi- ments is a major obstacle. EM simulations show that a quarter-
ciency of the main amplifier also remains at its peak even when wavelength transmission line has approximately 0.7 dB loss at
2340 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013

Fig. 3. Simulated efficiency as a function of loss in the output transmission line

of a Doherty PA with class A main and class C auxiliary amplifier.

Fig. 4. Phase-shifting preamplifier and auxiliary amplifier.

45 GHz, which further reduces the gain. Fig. 3 shows the effect
of this transmission line loss on the efficiency of the Doherty PA
at peak and 6-dB back-off power. The efficiency drops by 10% C. Active Phase-Shift Doherty Amplifier
with a 1 dB transmission line loss at 6 dB back-off power. As was mentioned in the previous Section, the single-stage
To increase the gain, one can use a preamplifier to drive a Do- gain of the mm-wave Doherty PA is low, which reduces the
herty PA or utilize two-stage amplifiers as the main and auxiliary PAE. To increase the gain of the Doherty PA, without sacri-
PAs [8]. However both of these solutions have major efficiency ficing back-off efficiency, and reduce the area of the PA, an ac-
penalties, especially at back-off power, since the driver ampli- tive phase-shift Doherty amplifier is proposed that creates a 90
fier is not operating at its peak efficiency in the back-off power phase shift at the input of the auxiliary amplifier.
region. The circuit shown in Fig. 4 illustrates the combination of the
To address these problems, an active phase-shift Doherty am- phase-shifting preamplifier and the auxiliary amplifier. When
plifier is proposed, where the input quarter wave transmission the circuit parameters of the phase-shifting preamplifier are cor-
line is replaced with a phase-shifting preamplifier as shown in rectly selected, the required 90 phase shift is generated be-
Fig. 1(b). To reduce the output transmission line loss, a slow- tween and . In a Doherty PA, the geometry of is
wave coplanar waveguide (CPW) transmission line is investi- selected according to the required peak power capability of the
gated in Section IV [4]. The length of this transmission line is auxiliary amplifier. Therefore, the geometry of driver is
further reduced by incorporating the parasitic capacitance at the set to a size that delivers enough power to saturate the auxil-
output of the main amplifier. iary amplifier and to therefore achieve the best efficiency. In
In a conventional Doherty PA, the auxiliary amplifier is off this case, and .
at low input power levels. In practice, the auxiliary amplifier If of is neglected, the voltage gain from to
gradually turns on, as the input power increases and the load is (7), shown at the bottom of the page, where
impedance of the main amplifier is modulated before it reaches
its peak efficiency. For example, from (1), if the auxiliary am- (8)
plifier turns on prematurely and delivers 10% of its peak current
to the load, the impedance seen by the main amplifier reduces
by 10%, resulting in a 10% reduction in efficiency. Since the auxiliary amplifier is a stacked-FET PA and the total
One possible solution is to bias the auxiliary amplifier in deep capacitance at the drain of is resonated with , which is
class C but this will reduce its gain significantly. Adaptive bi- explained in detail in Section III, the admittance seen at the drain
asing adjusts the gate d.c. bias of the auxiliary amplifier as a of is
function of input power [9]–[11] to keep the amplifier in deep
class C at low input power and in class AB at high input power (9)
levels. As a result, the auxiliary amplifier is totally off at low
input power and now has sufficient gain at high input power Assuming that is small compared to at millimeter-
levels. An uneven power drive Doherty PA [12] is another solu- wave frequencies, (8) can be rewritten as
tion to this problem, which is not employed here because of the
low gain of the mm-wave amplifiers. (10)

(7)
AGAH et al.: ACTIVE MILLIMETER-WAVE PHASE-SHIFT DOHERTY POWER AMPLIFIER IN 45-nm SOI CMOS 2341

Fig. 5. Analysis and circuit simulation of and vs. to achieve Fig. 6. and using (10) and circuit simulation, when
at 45 GHz, when , , and .
and .

where . By substituting (10) into (7)

(11)

Equation (11) shows that the preamplifier creates a 90 phase

shift between and at frequency Fig. 7. Phase shift as a function of frequency for a transmission line and the
active phase-shift preamplifier.

(12)
also shows the agreement between the circuit simulation and
analytical results.
and must be selected to establish the desired phase. As was mentioned in Section II-A, the auxiliary amplifier has
Fig. 5 plots the relation between and using (12) when twice the transconductance of the main amplifier as shown in
and . Fig. 6. The active phase-shift preamplifier increases the gain of
By substituting in (11) using (12), the auxiliary amplifier, which assists in achieving this goal.
As shown in Fig. 6, the frequency at which
is lower than the peak gain resonance frequency ) where
is maximum. The resonance occurs approximately at

(13) (16)
Fig. 5 shows the simulated and calculated at 45 GHz
when . There is an optimum
value for and that maximizes the gain, while achieving
90 phase shift. To determine the optimum value of , The result is that the phase-shifting preamplifier sacrifices
less than one dB gain to achieve the required phase shift.
Simulations show that the transmission line length required
(14) for is much smaller than , and the use of the phase-
shifting preamplifier reduces the overall area by approximately
Solving (14) shows that the value of that achieves the 20%.
highest gain is Fig. 7 plots the phase of as a function of frequency and
compares it to the phase shift of a quarter-wavelength transmis-
sion line. This simulation shows that the phase-shifting ampli-
(15) fier can be utilized at the input of the auxiliary amplifier in the
Doherty PA to create the required phase shift with little band-
width penalty. In fact, this technique increases the gain of the
and the value of that maximizes the gain is calcu- auxiliary amplifier as shown in Fig. 6. To take best advantage of
lated from (12), and is shown graphically in Fig. 5. this increased gain, the power consumption of the phase-shifting
By using the extracted parameters from circuit simulation, preamplifier should be minimized. Therefore, the preamplifier is
when , and implemented as a common-source amplifier with a 1.2 V power
into (11), and are plotted in Fig. 6. This graph supply.
2342 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013

Fig. 10. Simulated as a function of frequency.

its maximum value, unlike traditional analog circuits with con-

Fig. 8. Schematic of the main amplifier using a stacked-FET technique.
stant bias current. Using quasi-static approximation, this low
current reduces the probability of hot carrier injection signifi-
cantly. Some preliminary measurements are also conducted to
ensure the reliable operation of the stacked PAs, which will be
discussed in Section VI.
The ideal relation between the drain voltage swings is

(17)

where is the RF swing at the drain of the FET in the

stack. The increased voltage swing along the stack is achieved
by increasing the impedance seen at the drain of FET,
ideally

(18)

Fig. 9. Simulated 45-GHz waveforms of a two-stack amplifier.

A high is the other cause of breakdown. The gate of
is not RF grounded, allowing a limited gate voltage swing, pre-
venting the breakdown of the stacked FET by lowering the
III. STACKED FET DESIGN FOR IMPROVED VOLTAGE and as shown in Fig. 8.
HANDLING AND POWER Assuming that the relationship between and is deter-
Nanometer scale CMOS FETs traditionally suffer from mined by (17), the admittance at the drain of is
low breakdown voltage. To overcome this limitation, a
FET-stacking technique is utilized to achieve high output (19)
voltages without sacrificing reliability. By using the stacking
technique, the power supply voltage can be , where Assuming that the imaginary part of this admittance is res-
is the number of stacked FETs and is the drain-source onated with an inter-stack matching network and ,
breakdown voltage of a single device. the of is
Fig. 8 shows the schematic of the stacked-FET amplifier and
Fig. 9 shows the simulated drain and gate voltages of the FETs (20)
in this design. As shown in Fig. 9, the d.c. voltage is equally
distributed between the FETs, allowing operation with a power where . Considering (20) and ,
supply of 2.5 V. , can written as
For reliable operation of the FETs in the stacked architecture,
the peak RF voltage swing seen over and of each de-
vice should be kept below a certain breakdown voltage as well.
Preliminary reliability measurements in [3] and [14] shows that
this voltage is approximately 2.5 V peak for and . To ad- (21)
dress this problem, the RF swing should be distributed equally
between the FETs in the stack as shown in Fig. 8. Hot carrier in- From (20) and (21) at low frequencies. To verify
jection is the major cause of degradation of FETs in power am- this, is plotted as a function of frequency in Fig. 10.
plifiers and the quasi-static approximation is the main tool for The preliminary reliability measurements show that the peak
modeling this behavior [15], [16]. However, as shown in Fig. 8, swing of of a 45-nm SOI FET can reach as high as 3 V
the current through the FETs is almost zero when reaches without causing degradation in the device [3], [14]. is 420 fF,
AGAH et al.: ACTIVE MILLIMETER-WAVE PHASE-SHIFT DOHERTY POWER AMPLIFIER IN 45-nm SOI CMOS
Fig. 11. Slow-wave CPW structure with .
based on (16), to provide enough swing at the gate of and
the drain of to avoid breakdown of the FETs.
To achieve the highest PAE and Pout from a stacked PA, the
load impedance presented to each device must be optimized.
This optimum load impedance should be purely resistive and
satisfy (12) [5]. An interstage matching network is used between
the drain of and the source of [19].
IV. SLOW-WAVE TRANSMISSION LINE STRUCTURE
Since a quarter-wave line is relatively long (
at 45 GHz), the overall die area of a traditional Doherty ampli-
fier is determined by the size of the input and output networks.
At the same time, the losses of these CPW transmission lines
reduces the overall gain and efficiency. In order to improve the
performance, a slow-wave CPW is investigated.
Seki and Hasegawa proposed a slow-wave CPW for reducing
the signal speed to create a more compact quarter-wave CPW
transmission line [20]. This technique has recently been intro-
duced in mm-wave PA design [22].
The design of a slow-wave CPW is shown in Fig. 11 and
consists of floating metal strips underneath the signal line and
ground planes of a CPW. These metal strips are perpendicular to
the signal line. Considering the symmetry of the S-CPW struc-
ture, the voltage of each floating metal stripe is 0 V with respect
to the CPW line, therefore they can be considered as an effective
shield between the CPW and the substrate, which minimizes the
substrate loss. However, unlike the grounded substrate shield,
these floating strips increase the distributed capacitance of the
line without reducing the distributed inductance [22]. Since
(22)
where is the wavelength and is the signal velocity. There-
fore, the signal speed, impedance, and wavelength are reduced,
resulting in more compact quarter wavelength transmission
lines [22].
The simulated attenuation constant , phase constant
and quality factor (Q) of a shielded 50 CPW with
and a slow-wave CPW with are compared
in Fig. 12(a) and (b) using Sonnet. The quarter-wave S-CPW is
30% shorter than the grounded CPW and although it has higher
loss per unit length, it has lower loss per unit wavelength and
higher in comparison to the shielded CPW.
2343
Fig. 12. Simulated , and Q for a ground-shielded (800 ) and slow-wave
(620 ) CPW. .
V. DESIGN OF MM-WAVE DOHERTY PAS
In this section, the design of three Doherty PAs fabricated
in 45-nm SOI CMOS will be reviewed. In Section V-A, two
traditional Doherty PAs are designed using stacked amplifiers as
main and auxiliary PAs. One amplifier uses slow-wave CPWs
and the other employs ground-shielded CPWs as a comparison.
As discussed in previous section, the length of the slow-
wave CPWs is 30% shorter than the shielded CPW, and since the
length of transmission lines are the main factor in determining
the overall area of the Doherty PA, using them reduces the total
chip area by 20%.
In Section V-B the design of the third amplifier—the pro-
posed active phase-shift Doherty PA is discussed.
A. Doherty Amplifiers Using Traditional and Slow-Wave
Transmission Line Structures
The schematic of the designed Doherty power amplifiers are
shown in Fig. 13.
All the transmission lines in this work are implemented with
2.2 thick top metal layer to minimize resistive loss. As was
mentioned in Section II-A, should be in Doherty
PA, where is the characteristic impedance of the transmission
line. Therefore, requires . However,
the maximum possible characteristic impedance on this metal
layer is approximately 60 , since the minimum width of the
line is 4 . This motivates the need for an impedance trans-
forming section at the output of the Doherty PA that transforms
the 50 load to a lower impedance—in this case 25 . This
impedance transformation is implemented using a shunt capac-
itor and a series transmission line as shown in Fig. 13.
2344
Fig. 13. Schematic of the Doherty amplifiers with ground-shielded CPW and slow-wave CPW.
Fig. 14. Impedance seen by main and auxiliary amplifiers at back-off power.
Since and is transformed to 25 , this
transmission line ideally provides a 100 load for the main
amplifier. However, the parasitic capacitance at the output of
the main amplifier introduces an undesirable susceptance to this
resistive load reducing the efficiency of the main amplifier. To
provide a purely 100 resistive load for the main amplifier, the
length of this transmission line is reduced by 200 to 600
and the parasitic capacitance is included in the impedance
transforming network. Fig. 14 shows the network of the series
600- transmission line and the shunt parasitic capacitance
at the output of the main amplifier transferring a 25 load to
100 . Using this technique, the loss of the transmission line is
reduced by approximately 0.1 dB.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013
Fig. 15. Simulated gain, DE and PAE of the Doherty PA with ground-shielded
CPW as a function of output power.
Simulation results at 42 GHz for the DE, PAE and gain of the
Doherty PA with and without the slow-wave CPW are shown in
Fig. 15 and Fig. 16. Both of these PAs achieve approximately
18-dBm saturated output power. Comparison of these figures
indicates that the Doherty PA with the slow-wave CPW achieves
approximately 5% and 6% more DE and PAE at 6-dB back-off
power when compared to the PA with ground shielded CPW, a
significant improvement.
As was mentioned in Section II-B, the auxiliary amplifier
should be totally off at back-off to achieve the best efficiency.
One possible way to achieve this goal is to bias the auxiliary
amplifier in deep class C, which reduces the gain at high output
power. To address the problem of the auxiliary amplifier turning
on prematurely, adaptive biasing is evaluated. Adaptive biasing
AGAH et al.: ACTIVE MILLIMETER-WAVE PHASE-SHIFT DOHERTY POWER AMPLIFIER IN 45-nm SOI CMOS
Fig. 16. Simulated gain, DE and PAE of the Doherty PA with slow-wave CPW
as a function of output power.
Fig. 17. Simulation of the effect of adaptive biasing on DE of the circuit of
Fig. 13.
Fig. 18. Simulation of the effect of adaptive biasing on gain of the circuit of
Fig. 13.
adjusts the bias of the auxiliary amplifier according to the input
power as shown by the rule:
(23)
As a result of the adaptive biasing, the auxiliary amplifier
is biased in deep class C at low input powers, therefore the
back-off efficiency of the main amplifier is 7% higher than the
case when the auxiliary amplifier is biased in class AB, as shown
in Fig. 17; at high input powers, the auxiliary amplifier is biased
in class AB providing 2 dB higher gain than the case when it is
biased in class C as shown in Fig. 18.
As explained in Section II-A, the transconductance of the
auxiliary amplifier must be twice the transconductance of the
main amplifier to achieve the best performance at peak output
2345
power. The bias voltages of the auxiliary amplifier shown in (23)
are selected such that the transconductance criterion is met and
efficiency is maximized. Simulation shows that changing
from 0.15 V to 0.25 V only changes the peak PAE by 2% indi-
cating that the design is robust even if no calibration is done.
The other advantage of adaptive biasing is that the moment
of switching on and off for the auxiliary amplifier is determined
by the input power, making the system much less sensitive to
threshold voltage variations. The drawback of using the adap-
tive biasing is complexity of the control and discontinuity in the
gain characteristic of the PA shown in Figs. 16 and 17, which
potentially degrades linearity. This will be investigated in future
work.
B. Active Phase-Shift Doherty PA Design
The working principles of the active phase-shift Doherty have
been introduced in Section II-C.
As was explained there, a preamplifier is utilized at the input
of the auxiliary amplifier to increase the gain and provide the
required phase-shift. Although this amplifier is off at low input
power and has no effect on the back-off efficiency, its power
consumption should be significantly lower than the DC power
consumption of the auxiliary amplifier to avoid a significant
degradation of the overall efficiency at high power. As is shown
in Fig. 19, the auxiliary amplifier is a two-stack PA with width
of 256 and a 2.5 V power supply; therefore a CS amplifier
with width of 128 and a 1.2 V power supply is utilized as a
phase-shifting preamplifier.
As discussed in Section V-A, adaptive biasing is utilized to
maximize the efficiency and gain at back-off and peak power,
respectively. However, adaptive biasing modifies the input ca-
pacitance of the auxiliary amplifier, changing the phase shift
created by the phase-adjusting preamplifier according to (11).
In this work, the pre-amplifier is tuned to provide the correct
phase-shift at peak power. Therefore the variation of due to
dynamic biasing has no effect on peak efficiency and the phase
shift error occurs only at low input powers. However, this will
have a negligible effect on the overall efficiency at these power
levels, since the output current of the auxiliary amplifier is sig-
nificantly smaller than that of the main amplifier.
Simulations of the slow-wave Doherty show that the peak
PAE occurs at 17.3 dBm and d.c. power consumption of
165 mW, which corresponds to 33% DE. However, due to the
higher gain of the active phase-shift Doherty, the peak PAE oc-
curs at 18 dBm of with a DE of 27%. This shows that the
penalty of using the phase-shifting amplifier on the DE is ap-
proximately 5% at the peak PAE point.
Simulations confirms that the active phase-shift Doherty ex-
hibits 1.2 dB higher gain at back-off than the traditional ap-
proach, which is attributed to the increased gain of the main
amplifier due to the lower loss of the input network. Assuming
identical DE of 32% at back-off power for both PAs, the 1.2 dB
increase in the overall gain, translates into a PAE increase of
roughly 3%.
Fig. 20 shows the simulated gain, DE and PAE of the active
phase-shift Doherty PA, which shows the gain increases by 1.5
dB at peak and back-off power and the PAE is also improved by
1% and 5% at peak and 6-dB back-off power respectively. The
2346 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013

Fig. 19. Schematic of the active phase-shift Doherty PA.

Fig. 20. Simulated gain, DE and PAE of active phase-shift Doherty PA a as a

function of output power.

total area of this PA is 20% smaller than the Doherty PA using

the slow-wave CPW.

VI. MEASUREMENT RESULTS

The photomicrographs of the three Doherty PAs are shown in
Fig. 21. The active phase-shift Doherty PA, passive phase-shift
Doherty PA with slow-wave CPW and the passive phase shift
Doherty PA with ground shielded CPW occupies 0.45 ,
0.64 and 0.77 , which shows the advantage of the
active phase-shift Doherty over the traditional Doherty design
in terms of area.
All the results in this section are measured at 42 GHz for a
2.5 V supply. All the PAs have greater than 17.5 dBm saturated
output power and there is a good agreement between simulation Fig. 21. Photo micrograph of (a) Doherty PA with G-CPW, (b) Doherty PA
and measurement. with S-CPW, (c) active phase-shift Doherty.
The measured and simulated gain, PAE, and drain efficiency
of the passive phase-shift Doherty PA with ground-shielded gain and it achieves 20% DE and 12% PAE at back-off. The
CPWs are plotted in Fig. 22 and Fig. 23. It has 6-dB small-signal low PAE at back-off is attributed to the drop in the gain of the
AGAH et al.: ACTIVE MILLIMETER-WAVE PHASE-SHIFT DOHERTY POWER AMPLIFIER IN 45-nm SOI CMOS 2347

Fig. 22. Gain as a function of output power of the Doherty PA with ground-
shielded CPW. Fig. 25. PAE and DE of the Doherty PA with slow-wave CPW.

Fig. 23. PAE and DE of the Doherty PA with ground-shielded CPW. Fig. 26. Gain as a function of output power of the active phase-shift Doherty
PA.

Fig. 24. Gain as a function of output power of the Doherty PA with slow-wave
CPW.
Fig. 27. PAE and DE of the active phase-shift Doherty PA.

PA. The DE and PAE of this PA at peak output power are 31%
and 21% respectively.
The measured and simulated gain, PAE and drain efficiency
of the Doherty PA with slow-wave CPWs are plotted in Figs. 24
and Fig. 25. It achieves 24% DE and 17% PAE at back-off,
which is 4% and 5% higher than the ground-shielded CPW Do-
herty PA, demonstrating the benefit of the lower loss of the slow-
wave transmission lines. The DE and PAE of the slow-wave
CPW Doherty PA are 33% and 23% at peak output power, which
is also 2% higher than the Doherty PA with ground-shielded
CPW.
The measured and simulated gain, PAE, and DE of the third Fig. 28. Comparison of the measured PAE of the three Doherty PAs.
design—the active phase-shift Doherty PA—are plotted in
Figs. 26 and 27. It exhibits roughly 7.7 dB small-signal gain
and it achieves 28% DE and 21% PAE at back-off. However, Fig. 28 and Fig. 29 compares the measured PAE and gain of
the peak PAE of the active phase-shift Doherty only reaches all the three Doherty PAs, which demonstrates the advantage of
20%, which is 3% lower than the slow-wave Doherty and 1% the active phase-shift Doherty PA over the traditional designs.
lower than Doherty PA with ground-shielded CPW. This is To ensure the reliable operation of the implemented PAs, each
explained by the higher power consumption of this design, of them has been measured at 1-dB compression point with 2.5
because of the additional phase-shifting amplifier. V power supply for more than 3 hours and Fig. 30 plots the
2348
COMPARISON
Fig. 29. Comparison of the measured gain of the three Doherty PAs.
Fig. 30. Measured gain at 1-dB compression point as a function of time for the
three Doherty PAs.
measured gain as a function of time. No degradation is observed
during this laboratory testing of the amplifiers.
Table I is a comparison of the three fabricated Doherty PAs
in this work with other published results in the mm-wave fre-
quency range. This work demonstrates the highest output power
compared to all previous CMOS work as well as the highest
efficiency for an amplifier operating under 6-dB back-off
conditions.
VII. CONCLUSION
In this paper, a traditional 45 GHz Doherty PA is designed
with shielded CPWs in 45-nm SOI CMOS technology. To im-
prove the performance and reduce the area, shielded CPWs are
substituted with slow-wave CPW in a second PA, resulting in
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013
TABLE I
TO PREVIOUS RESULTS
20% smaller chip area, 1 dB more gain and 4% more PAE.
Finally, an active phase-shift Doherty PA is proposed and im-
plemented, which reduces the overall area by another 30% and
increases the gain by 1.2 dB. At 6-dB back-off power, the ac-
tive phase-shift Doherty achieves 21% PAE, which is 4% higher
than the passive phase-shift Doherty amplifier with slow-wave
CPW, and at the peak power, the PAE reaches 20%, which is
3% lower than the Doherty amplifier with slow-wave CPW.
The Doherty PAs achieve a saturated output power greater than
17.5 dBm.
ACKNOWLEDGMENT
The authors are grateful to the DARPA LEAP program for
access to the IBM 45-nm SOI technology and to the DARPA
ELASTx program (Dr. S. Raman), and the US Army Research
Office (Dr. D. Palmer) for support. Additionally, the authors
thank the members of the High-Speed Devices Group at UCSD
and Don Kimball for important discussions on the design and
testing of this work.
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2349
Amir Agah (S’11) received the B.Sc. degree in
electrical engineering from the University of Tehran,
Tehran, Iran, in 2007, the M.S. degree in electrical
engineering from the Delft University of Technology,
Delft, The Netherlands, in 2009, and is currently
working toward the Ph.D. degree at the University
of California at San Diego, La Jolla, CA, USA.
He has previously held internship positions
at Qualcomm Inc., San Diego, CA, USA, and
Broadcom Corporation, Utrecht, The Netherlands.
His research interests include cellular and mil-
limeter-wave PA and transceiver design in advance CMOS technologies.
Hayg-Taniel Dabag (S’10) received the Dipl.-Ing.
degree in electrical engineering from Ruhr University
Bochum, Bochum, Germany, in 2008, the M.S. de-
gree in electrical engineering from the University of
California at San Diego, La Jolla, CA, USA, in 2011,
and is currently working toward the Ph.D. degree in
electrical and computer engineering at the University
of California at San Diego.
He attended Purdue, West Lafayette, IN, USA, as
an exchange student during his undergraduate study
and held two internships with Qualcomm Inc., where
he was involved with high-voltage tolerant analog circuits, mixed-signal inte-
grated circuit (IC) design, and DAC behavioral modeling. His research inter-
ests include RF and millimeter-wave amplifier design and digital predistortion
of PAs.
Bassel Hanafi received the B.Sc. degree in elec-
tronics and communications and M.Sc. degree in
electronic engineering from Ain Shams University,
Cairo, Egypt, in 2005 and 2009, respectively, and
is currently working toward the Ph.D. degree at the
University of California at San Diego, La Jolla, CA,
USA.
From 2005 to 2009, he was a Teaching and Re-
search Assistant with the Electronics and Communi-
cations Engineering Department, Ain Shams Univer-
sity. From 2006 to 2009, he was an Analog/MS De-
sign Engineer with Si-Ware Systems, Cairo, Egypt. During the summer of 2010,
he was an Intern with the Audio Group, Broadcom Corporation, Irvine, CA,
USA. His research interests include RF/millimeter-wave transceiver design and
analog/MS circuits.
Peter M. Asbeck (M’75–SM’97–F’00) received the
B.S. and Ph.D. degrees from the Massachusetts Insti-
tute of Technology, Cambridge, MA, USA, in 1969
and in 1975, respectively.
He was with the Sarnoff Research Center,
Princeton, NJ, USA, and with Philips Labora-
tory, Briarcliff Manor, NY, USA, where he was
involved in the areas of quantum electronics and
GaAlAs/GaAs laser physics. In 1978, he joined
the Rockwell International Science Center, where
he was involved in the development of high-speed
devices and circuits using III-V compounds and heterojunctions. He pioneered
efforts to develop heterojunction bipolar transistors based on GaAlAs/GaAs
and InAlAs/InGaAs materials. In 1991, he joined the University of California
at San Diego, La Jolla, CA, USA, where he is the Skyworks Chair Professor of
the Department of Electrical and Computer Engineering. He has authored or
coauthored over 350 publications. His research interests are in development of
high-performance transistor technologies and their circuit applications.
Dr. Asbeck is a member of the National Academy of Engineering. He has
been a Distinguished Lecturer of the IEEE Electron Device Society and the
IEEE Microwave Theory and Techniques Society (IEEE MTT-S). He was the
recipient of the 2003 IEEE David Sarnoff Award for his work on heterojunction
bipolar transistors and the 2012 IEEE MTT-S Distinguished Educator Award.
2350
James F. Buckwalter (S’01–M’06) received the
Ph.D. degree in electrical engineering from the
California Institute of Technology, Pasadena, CA,
USA, in 2006.
He is currently an Associate Professor of electrical
and computer engineering with the University of
California at San Diego (UCSD), La Jolla, CA, USA.
From 1999 to 2000, he was a Research Scientist
with Telcordia Technologies. During Summer 2004,
he was with the IBM T. J. Watson Research Center,
Yorktown Heights, NY, USA. In 2006, he joined
Luxtera, Carlsbad, CA, USA. In July 2006, he joined the faculty of UCSD as
an Assistant Professor.
Dr. Buckwalter was the recipient of a 2004 IBM Ph.D. Fellowship, the 2007
Defense Advanced Research Projects Agency (DARPA) Young Faculty Award,
and the 2011 National Science Foundation (NSF) CAREER Award.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013
Lawrence E. Larson (F’00) received the B.S.
degree in electrical engineering from Cornell Uni-
versity, Ithaca, NY, USA, and the Ph.D. degree from
the University of California, Los Angeles, CA, USA
(UCLA).
From 1980 to 1996 he was at Hughes Research
Laboratories, Malibu, CA, USA, where he directed
the development of high-frequency microelectronics
in GaAs, InP and Si/SiGe and MEMS technologies.
He joined the faculty at the University of California
at San Diego, La Jolla, CA, USA (UCSD), in 1996,
where he was the inaugural holder of the Communications Industry Chair. He
was Director of the UCSD Center for Wireless Communications from 2001 to
2006 and was Chair of the Department of Electrical and Computer Engineering
from 2007 to 2011. He moved to Brown University, Providence, RI, USA, in
2011, where he is Founding Dean of the School of Engineering.
Dr. Larson was a recipient of the Hughes Sector Patent Award in 1994 for his
work on RF MEMS, co-recipient of the 1996 Lawrence A. Hyland Patent Award
of Hughes Electronics, for his work on low-noise millimeter-wave HEMTs,
co-recipient of the 1999 IBM Microelectronics Excellence Award for his work
in Si/SiGe HBT technology and co-recipient of the CICC Best Invited Paper
Award in 2005. He is on the Boards of Aethercomm, Tahoe RF and Black Sands
Technologies. He has published over 300 papers, co-authored three books, and
received over 40 U.S. patents.