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Content is final as presented, with the exception of pagination.
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
A Low-Noise, Low-Power Amplifier With
Current-Reused OTA for ECG Recordings
Jie Zhang , Hong Zhang , Member, IEEE, Quan Sun, and Ruizhi Zhang
Abstract—This paper presents a low-power and low-noise
capacitive-feedback amplifier with a current-reused OTA for ECG
recordings. To improve the noise-power efficiency, the proposed
OTA employs a current-reused architecture, which adopts an
inverter-based differential input stage for low noise, and a class-
AB output stage for large output range and high gm /I efficiency.
The driving branch of the class-AB output stage is merged into the
input stage to realize current reuse and reduce power consump-
tion further. Fabricated in a 0.35-µm CMOS process, the amplifier
consumes 160 nA from a 2-V supply, while achieving an input-
referred noise of 2.05 µVrm s , corresponding to a noise efficiency
factor (NEF) of 2.26. The measured common-mode rejection ratio
(CMRR) and power supply rejection ratio (PSRR) exceed 65 dB
and 70 dB, respectively. The total harmonic distortion (THD) is
less than 1% with a 15-mVp p input at 20 Hz and the active area is
0.3 mm × 0.6 mm.
Index Terms—Bio-signal amplifier, class-AB, current-reused,
ECG recording, inverter-based, low noise, low power.
I. INTRODUCTION
EARABLE and implantable electrocardiography(ECG)
W sensors are widely used to monitor the individual’s heart
condition for early detection of cardiovascular diseases, such as
cardiac arrhythmia and heart failure. The recording amplifier is
one of the most important parts in terms of power, noise and
linearity performance in an ECG sensor [1], [2]. For chronic
monitoring, ultra-low power consumption is essential to pre-
serve long battery life or maximize the working hours before
recharging. To realize robust ECG recording, the input-referred
noise needs to be low enough for accurate data acquisition. Ad-
ditionally, large dynamic range and small harmonic distortion
are also important for bio-signal recordings [3].
Many research activities have been carried out to improve the
performance of OTAs in terms of power, noise and linearity for
ECG recording applications. The design in [4] employs a mod-
ified folded-cascode topology with source degeneration and the
current in the folded branch is largely scaled down compared
with that in the input branch. The power and noise contribution
Manuscript received September 30, 2017; revised February 8, 2018 and March
15, 2018; accepted March 21, 2018. This work was supported by the National
Science Foundation of China under Grant 61474092. This paper was recom-
mended by Associate Editor J. Van der Spiegel. (Corresponding author: Hong
Zhang.)
The authors are with the School of Microelectronics, Xi’an Jiaotong Uni-
versity, Xi’an 710049, China (e-mail:, jacky99@stu.xjtu.edu.cn; hongzhang@
xjtu.edu.cn; sunq@aerosemi.com; rzzhang@mail.xjtu.edu.cn).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TBCAS.2018.2819207
1932-4545 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
1
from the folded branches are reduced remarkably, however, as
noted in [2] and [5], the large degeneration resistors consume
extra voltage headroom, and the high current ratio between the
input and the folded branches requires elaborate matching of
the current mirrors. The amplifier with an open-loop single-
ended current-reused complimentary-input structure in [6] has
achieved very high power efficiency. However, the single-ended
structure shows relatively poorer supply rejection, higher sensi-
tivity to process variations and lower linearity than the differen-
tial counterpart. Furthermore, the closed-loop fully differential
amplifiers with inverter-based input stage [1], [2], [7] are applied
widely for its excellent power-noise performance, sufficient lin-
earity and power supply rejection performance. With a single-
stage, current-reused fully-differential topology, the design in
[2] achieves excellent noise efficiency factor (NEF), common-
mode rejection ratio (CMRR) and power supply rejection ratio
(PSRR). However, as cascode structure is used to boost the gain,
the output dynamic range may be limited under lower supply
voltages. As for the flicker noise (1/f noise), the chopper mod-
ulation technique is widely employed for the amplifiers in a
system where clock signals are available [8]–[11]. Although the
chopper technique achieves remarkable reduction in 1/f noise,
it requires relatively large bandwidth for the amplifier, and ad-
ditional clock circuits, switches and low-pass filter for signal
processing, which increase the circuit complexity and overall
power consumption. Another commonly used method to reduce
the 1/f noise is increasing the input transistors’ area, which has
the advantage of low power consumption at the cost of relatively
larger chip area [1]–[7], [12].
In this paper, a low-power and low-noise capacitive feedback
amplifier based on a current-reused OTA for ECG recordings
is presented. The design achieves a very efficient power-noise
factor since the proposed OTA topology makes an efficient use
of the supply current. First of all, the OTA employs an inverter-
based differential input stage for low noise, and a class-AB
output stage for large output range, high gm /I efficiency and lin-
earity. Moreover, the driving unit of the class-AB output stage is
embedded into the input stage to reduce the power consumption
further. Therefore, the proposed OTA reuses the supply current
both in the input stage and output stage to achieve high power-
noise efficiency and high linearity. As a result, the proposed
amplifier achieves an input-referred noise of 2.05 μV rms with
160-nA current consumption, corresponding to a NEF of 2.26.
This paper is organized as follows. Section II introduces
the structure of the capacitive feedback amplifier. Section III
describes the topology and noise analysis of the proposed
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2 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
Fig. 1. Fully-differential capacitive-feedback amplifier structure.
current-reused OTA. Measurement results are provided in
Section IV while the conclusion is drawn in Section V.
II. CAPACITIVE FEEDBACK AMPLIFIER
The capacitive feedback amplifier is a popular topology in
biomedical recordings [1]–[15], which utilizes capacitors to set
the mid-band gain and to reject the DC offset from the skin-
electrode. The amplifier in this paper also adopts capacitive feed-
back with fully differential architecture to achieve high CMRR
and PSRR, as shown in Fig. 1. With a first-order OTA, it can
be derived that the closed-loop transfer function of a capacitive-
feedback amplifier in Fig. 1 exhibits band-pass responses [15].
The mid-band gain of the amplifier, A, is set by the ratio be-
tween the input capacitor Cin and the feedback capacitor Cf ,
i.e., A ≈ Cin /Cf . The lower cutoff frequency, fL , is given by
1/(2πRp Cf ), where Rp is the MOS-BJT pseudo-resistor which
occupies small area but can realize resistance larger than 1012
Ω [1]. The higher cutoff frequency, fH , equals to gm /(2πACL ),
where gm is the transconductance of the OTA. In addition, the
transfer function includes a high-frequency right-half-plane zero
at gm /(2πCf ).
If the OTA is realized with Miller compensated two-stage
structure, the transfer function can be derived approximately as
Cin 1 − s A V , s tC1 gf m , s t 2
H (s) ≈    (1)
Cf 1 + 1 1 + s gCm C, s tC1 iCn f
sR p C f
where gm ,st1 is the transconductance of the first stage, gm ,st2
is the transconductance of the second stage, AV ,st1 is the volt-
age gain of the first stage and CC is the Miller compensation
capacitor. The value of fH changes to gm ,st1 /(2πACC ). The
closed-loop transfer function in (1) is obtained under the as-
sumption that the loop gain of the capacitive-feedback amplifier
has a non-dominant pole with frequency higher than the loop
gain’s unit-gain frequency. However, the non-dominant pole
will affect the stability of the amplifier. Assuming Cin  Cf ,
the unit-gain frequency of the loop gain can be obtained as
ft ≈ (Cf /Cin )gm ,st1 /(2πCC ), and the non-dominant pole’s fre-
quency can also be derived as fnd ≈ gm ,st2 /[2π(CL + Cf )]. The
value of fnd should be η times larger than ft to ensure stable
operation of the amplifier, i.e.,
gm ,st2 Cf gm ,st1
>η (2)
(CL + Cf ) Cin CC
where η is a coefficient determining how much phase margin
can be achieved for the amplifier. For example, η should be
larger than 1.22 to achieve a phase margin of higher than 45°,
while a phase margin larger than 60° requires η > 2.2 [16].
According to (2), the circuit parameters of the amplifier can be
designed to achieve the required phase margin with given output
load capacitance, CL .
In addition, two reset switches are added to initialize the
input and output nodes to the common-mode voltage quickly
before the amplifier starts to operate or reset the amplifier when
the output is saturated due to motion artifacts or electrode fall-
off [13], [14]. Although not included in this chip, saturation
detection can be implemented as a system-level function of
ECG recordings, as that in [14], [15].
The input-referred noise is one of the most important specifi-
cations for ECG recording amplifiers. According to [12], the re-
lationship between the input-referred noise density of the overall
capacitor feedback amplifier, vn,A and the input-referred noise
density of the OTA, vn,OTA is written as
 2
2 Cin + Cp + Cf 2
vni,A = vn,OTA (3)
Cin
Thus, to achieve low-power and low-noise ECG recording
system, the key point is to design an OTA showing low input-
referred noise with low power consumption.
III. PROPOSED CURRENT-REUSED OTA
A. OTA Topology
Compared with the single-stage OTA architecture, the two-
stage one is more commonly used in bio-sensing applications
for its wider output swing, better linearity, and larger open-
loop gain. Several techniques have been used to improve the
performance of two-stage OTAs under limited power consump-
tion. Firstly, at the input stage, inverter-based input pairs are
exploited to double the transconductance under the same bias
current,
√ which improves the power-to-noise efficiency by a fac-
tor of 2 [7]. Secondly, class-AB structures are commonly used
at the output stage. Because the class-AB structure employs two
transconductors with single branch of bias current, it exhibits
higher current efficiency and transient speed compared to the
class-A counterpart with the same quiescent current. Therefore,
it is attractive to design an OTA with both inverter-based input
stage and class-AB output stage to increase the overall current
efficiency. This kind of OTA is termed as current-reused OTA in
this paper because it makes an efficient use of the supply current
both in the input and output stages.
Fig. 2(a) shows a conceptual structure of the widely used
inverter-based input stage, which provide 2 transconductors with
only one branch of DC circuit. The structure of a commonly-
used class-AB output stage is shown in Fig. 2(b), in which the
driving circuit is used to stabilize the quiescent current in the
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ZHANG et al.: LOW-NOISE, LOW-POWER AMPLIFIER WITH CURRENT-REUSED OTA FOR ECG RECORDINGS
Fig. 2. (a) Conceptual structure of the inverter-based input stage; (b) concep-
tual structure of class-AB output stage with floating controlled stage; (c) the
proposed two-stage current-reused OTA topology.
output stage, while feed approximately equal small-signal com-
ponents to MN 2 and MP 2 . There are several methods to imple-
ment the driving circuit, including the floating controlled class-
AB structure [17], [18] and the current-mirror-biased class-AB
structure [19]. In these structures, at least one extra current
branch is needed for the driving stage, which will lower the cur-
rent efficiency for ultra-low-power applications. Although the
quasi-floating gate (QFG) technique [1], [20] is also used to real-
ize driving circuit for class-AB output stage without DC current
consumption, it uses a large capacitor to pass the small signal,
which consumes relatively large area. The capacitor can’t be too
small in low-frequency applications because it determines the
minimum signal frequency it passes and also the voltage loss
resulted from the parasitic capacitance.
In order to increase the current efficiency as far as possible,
this paper proposes a current-reused OTA topology with the
control circuit for the class-AB output stage embedded in the
inverter-based input stage, as shown in Fig. 2(c), which elimi-
nates the extra bias branch and also its power consumption. The
detailed OTA structure is discussed in the following sub-section.
B. Circuit Implementation of OTA
The proposed OTA is composed of a two-stage current-reused
main OTA, a bias circuit for accurate control of the quiescent
current in the main OTA and a continuous-time common mode
feedback (CMFB) circuit, as shown in Fig. 3(a), (b) and (c),
respectively. Fully-differential configuration is used to suppress
the common-mode artifacts and power-line interferences. In or-
der to ensure the loop stability, Miller-compensation capacitors
and resistors (CC = 2 pF, RZ = 1 M Ω) are added to achieve a
phase margin larger than 60 degree. The class-AB output stage
provides large output driving capability to mitigate the output
distortion and improves the recovery speed after resetting of the
amplifier. The aspect ratio and DC current of each transistor
in the OTA are shown in Fig. 3. The simulated Cgs and Cgd
3
are about 130 fF for each input transistor operating in the sub-
threshold region. Considering Miller effect, the input parasitic
capacitor Cp has a total value of about 10 pF which is estimated
through resonance-based simulation and noise simulation.
The quiescent currents in the class–AB output transistors,
M9 (M10 ) and M11 (M12 ), are determined by the class-AB con-
trol unit composed of M5 (M6 ) and M7 (M8 ), which determines
the dynamic operation of the output transistors. Obviously, the
control unit is embedded in the inverter-based first stage to make
efficient use of the DC current of the first stage.
In order to realize enough voltage gain, high output
impedance should be ensured for the driving nodes, i.e., nodes
A, B, C, and D in Fig. 3(a). This means that the embedded class-
AB control unit should not lower the output impedance of the
first stage, which has an original value of ro1,3 ||ro2,4 . In order to
calculate the actual output impedance of the control unit at driv-
ing node A (B), the small-signal equivalent circuit is simplified
as shown in Fig. 4(a), in which MN and MP represent the class-
AB control unit. Using the small-signal equivalent model shown
in Fig. 4(b), we can obtain vo = iX ro3,4 , v1 = −vo , v2 = −vX .
It follows that
vX
routA,B =
iX
rn ||rp + gm n ro3,4 (rn ||rp ) + ro3,4 gm n
= ≈ ro3,4
1 + gm p (rn ||rp ) gm p
(4)
Similarly, the output impedance at driving node C (D) is
approximately
gm p
routC,D ≈ ro1,2 (5)
gm n
To obtain high impedances for the two nodes at the same time,
the values of gmp and gmn should be almost the same. This can be
fulfilled easily as gmp and gmn are controlled by VB P 2 and VB N 2
respectively. With gmp = gmn , the driving nodes A (B) and C (D)
remain as high impedance nodes, and the small-signal voltage
gain of the two stage OTA can be obtained approximately as
AV ≈ (gm 1,2 + gm 3,4 ) (ro1,2 ||ro3,4 )
× (gm 9,10 + gm 11,12 ) (ro9,10 ||ro11,12 ||RC1,2 ) (6)
It is about 4 times larger than that of the traditional non-
current- reused two-stage OTA under the same current con-
sumption.
Fig. 3(b) shows the bias circuit to control the quiescent cur-
rents in the main OTA, which determines the standby power
and the impedance at the driving nodes A (B) and C (D).The
quiescent currents in M7 (M8 ) and M11 (M12 ) are replicated
from those in MB8 and MB7 . Similarly, the quiescent current in
M5 (M6 ) and M9 (M10 ) are replicated from those in MB12 and
MB11 . The bias circuit together with careful sizing of M5 ∼ M 8
ensure gm 5,6 ≈ gm 7,8 . More detailed analysis for the quiescent
current control circuit can be found in [21].
The CMFB circuit of the OTA is shown in Fig. 3(c). Al-
though switched-capacitor CMFB circuit can also be employed
to ensure higher differential output range with lower area and
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4 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS

Fig. 3. Schematic of the proposed current reused OTA with aspect ratios (μm/μm) and bias currents: (a) main amplifier; (b) bias circuit; (c) continuous-time
common-mode feedback amplifier.

Based on simulation, the resistors are designed with values of

Fig. 4. (a) Simplified schematic of the class-AB control unit to calculate the
output impedance; (b) corresponding small signal equivalent model of (a).
lower power consumption, the continuous-time CMFB is cho-
sen for the prototype amplifier to avoid the design of clock
circuits in a clockless application [14]. In order to obtain wide
differential output swing, the output common-mode voltage is
sensed by two resistors, RC 1 and RC 2 . Generally, a large value
of the resistors is desired to ensure that the DC gain of the
OTA is not degraded by the common-mode resistors. How-
ever, large resistors occupy considerable chip area. Therefore,
there is a design tradeoff when choosing the resistance value.
RC 1 = RC 2 = 10 M Ω. The current flowing through RC 1 and
RC 2 for large differential output voltage can be compensated
by the class-AB output structure, which provide a large driving
current independent of the DC bias current. The common-mode
error amplifier acts as a voltage buffer with a gain of about
1, and its output controls the gate of M13 to adjust the output
common-mode voltage of the OTA. The remaining common-
mode path overlaps the differential-mode path. As a result, the
loop gain of the common-mode loop almost equals to the gain
of the two-stage OTA, and the loop stability is ensured by the
Miller compensation structure. The total current consumption
of the CMFB amplifier is only 10 nA. Thus, this CMFB strat-
egy provides high loop gain and bandwidth while ensures wide
differential output swing with very small power consumption.
C. Common-Mode Input Range
In ECG recordings, the power-line interference can be quite
large, up to several hundred millivolt. In this design, all tran-
sistors are biased in the subthreshold region. To ensure proper
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ZHANG et al.: LOW-NOISE, LOW-POWER AMPLIFIER WITH CURRENT-REUSED OTA FOR ECG RECORDINGS 5

operation for transistors in the first stage, the input common-

mode level should satisfy the following conditions
⎧
⎪ VCM ,m in = max
⎪
⎪

⎪
⎪
⎪
⎨ VGS3,4 + VDS,m in,13 ,
VDD − |VGS1,2

| − |VGS9,10 | + |VDS,m in,1,2 | 
(7)
⎪
⎪
⎪
⎪ VDD − |VGS1,2 | − |VDS,m in,0 | ,
⎪
⎪
⎩VCM ,m ax = min
VGS3,4 + VGS11,12 − VDS,m in,3,4
where VDS,min,i and VGSi are the required minimum drain- source Fig. 5. (a) Simplified schematic to analyze noise contribution of the class-
voltage, gate-source voltage and threshold voltage for transistor AB control unit; (b) corresponding small signal model for analyzing the noise
Mi , respectively. contribution of MN.
From (7), the input common-mode range depends on the
supply voltage, gate-source voltage and minimum drain-source contributed by the NMOS in the class-AB control unit can be
voltage. In this design, as all transistors in the main OTA operate obtained as
in weak inversion, the minimum drain-source voltage is about
4UT ≈ 100 mV, where UT is the thermal voltage. The supply vno,n = (vu gm 9,10 + vd gm 11,12 ) (ro9,10 ||ro11,12 ||RC1,2 ) (12)
voltage, VDD , is chosen to be 2 V for the target process. To
guarantee weak inversion of the transistors, VG S 3,4,11,12 is set Thus, the corresponding input-referred noise density of MN
as about 600 mV for NMOS while |VG S 1,2,9,10 | set as about 700 can be obtained:
mV for PMOS. Thus, the input common-mode swing ranges
2
vno,n
approximately from 0.7 to 1.1 V. 2
vni,n = =
A2V
D. Noise Analysis of OTA  2
gm 9 , 1 0 ro 1 , 2 − gm 1 1 , 1 2 ro 3 , 4 i2n,N
Normally, biasing the input transistors into subthreshold   2 (13)
regime is helpful to improve the noise-to-power efficiency [22]. AV1 · gm 9 , 1 0 + gm 1 1 , 1 2 (1 + gm n ro3,4 + gm p ro1,2 )
The thermal current noise density of a MOS transistor operating
Where AV 1 = (gm 1,2 + gm 3,4 )(ro1,2 ||ro3,4 ), is the gain of
in the weak inversion can be written as
the first stage. A noise cancellation effect can be observed in
i2n = 2kT ngm (8) the numerator of (13), which comes from the fact that vu and vd
are fully correlated and with inverted phases. Furthermore, the
where n is subthreshold slope factor, which is around 1.4 as noise contribution is attenuated by the gain of the first stage, as
simulated in the target technology, k is the Boltzmanns constant, indicated by (13).
T is the absolute temperature, and gm is the transconductance of Similarly, the input-referred noise contributed by the PMOS
the transistor. Based on the simplification mentioned, the output in the class-AB control unit can be obtained as
thermal voltage noise density of the amplifier contributed by the
input transistors can be derived approximately as 2
vni,p =
2
vno,th ≈ 2kT n (2gm 1,2 + 2gm 3,4 ) [(ro1,2 ||ro3,4 ) (gm 9,10 ro1,2 − gm 11,12 ro3,4 )2 i2n,P
(14)
× (gm 9,10 + gm 11,12 ) (ro9,10 ||ro11,12 ||RC1,2 )]2 [AV1 · (gm 9,10 + gm 11,12 ) (1 + gm n ro3,4 + gm p ro1,2 )]2
(9)
Then the overall input-referred noise power contributed from
In order to figure out the output noise contribution from the class-AB control unit is
the class-AB control unit, a simplified schematic is shown in
Fig. 5(a), in which in,N and in,P are used to represent the noise 2
vni,ctrl 2 2
unit = vni,n + vni,p (15)
current of MN and MP respectively. To simplify the analysis,
the equivalent small signal circuit in Fig. 5(b) only includes which is negligible as it is much smaller than that from the input
the noise contribution of MN. From small-signal analysis, the transistors.
voltage noise at the driving nodes can be obtained as Therefore, the input transistors dominate the noise contribu-
ro3,4 tion in the OTA and the input-referred thermal noise density can
vd ≈ in,N (10) be obtained using (6) and (9):
1 + gm n ro3,4 + gm p ro1,2
−ro1,2 2
vno,th 4kT n
vu ≈ in,N (11) 2
vni,th = ≈ (16)
1 + gm n ro3,4 + gm p ro1,2 A2V gm 1,2 + gm 3,4

Because both vu and vd arise from the same noise source, in,N With gm 1,2 = gm 3,4 , the input-referred thermal voltage noise
they are correlated with each other. The output voltage noise density is
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6 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS

4kT n
2
vni,th ≈ (17)
2 · gm 1,2
It is half of the thermal noise density from the non-inverter-
based amplifiers under the same condition of current consump-
tion. As a result, the input-referred noise voltage
√ contributed by
the thermal noise is reduced by a factor of 2.
The flicker noise (or 1/f noise) current flowing through the
channel of the MOS transistors is a major concern for a low-
noise and low-frequency circuit. The 1/f current noise density
in a MOS can be written as
2
K gm
i2n,f = (18)
f W LCox Fig. 6. Chip photo of the proposed amplifier.

where K is a process-dependent constant, Cox is the gate-oxide

capacitance per unit area. As given by (18), 1/f noise is in-
versely proportional to the gate area and frequency. To achieve
low input-referred noise, chopper modulation can be applied to
reduce the 1/f noise in those systems where clock signals are
available, at the cost of a relatively large power consumption
and the design complexity. As a stand-alone prototype amplifier
in this design, we use large width and length for all input transis-
tors, M1 to M4, to suppress the 1/f noise at the cost of relatively
larger active area. Similar to the analysis for the thermal noise,
the input-referred noise voltage contributed
√ by flicker noise can
also be reduced by a factor of 2 when compared with the
non-inverter based input structure.
The definition of noise efficiency factor (NEF) in [23] is used Fig. 7. Measured differential, common-mode and power-supply gain.
to benchmark the noise-to-power trade-off for the capacitive-
feedback amplifier:

2Itot
N EF = v̂ni,rm s (19)
π × UT × 4kT × BW
where v̂ni,rm s is the input-referred rms noise voltage, Itot is
the total current, UT is the thermal voltage, and BW is the 3-dB
bandwidth of the capacitive-feedback amplifier in Hz. The input-
referred rms noise voltage should be obtained by integrating the
input referred noise density within the noise bandwidth of the
capacitive-feedback amplifier. With an approximation of first-
order band-pass frequency response for the amplifier, the input-
referred rms noise can be derived as
 ∞
π
2
v̂ni,rm s = 2
vni,th df ≈ vni,th
2 · BW (20) Fig. 8. The frequency spectrum for a 20-Hz input sinusoid signal with
0 2 15-mVpp amplitude.
In (20), the flicker noise is not included for simplicity of
calculation, which is suppressed by using large width and length Therefore, the NEF can be reduced by increasing the ratio of
for the input transistors. the first-stage current to Itot . The value of Itot can be decomposed
For transistors operating in subthreshold region, the EKV further into 3 components:
model can be applied to estimate the transconductance [1]:
Itot = 2Id1,2 + 2Id9,10 + Iothers (23)
Id
gm = (21)
nUT where Id9,10 is the current in one branch of the differential
output stage, and Iothers is the sum of the currents in other circuits
where Id is the drain current through the MOS transistor.
including the CMFB circuit and bias circuit. From (21) and the
Substituting (17) and (20), (21) into (19), the NEF of the
stability requirement for the capacitive-feedback amplifier given
capacitive-feedback amplifier can be obtained as:
 by (2), the relationship between Id9,10 and Id1,2 can be derived as
Itot CL + Cf Cf
N EF = n (22) Id9,10 > η Id1,2 (24)
2Id1,2 CC Cin
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ZHANG et al.: LOW-NOISE, LOW-POWER AMPLIFIER WITH CURRENT-REUSED OTA FOR ECG RECORDINGS
Fig. 9. Measured input-referred noise spectrum of the proposed amplifier,
computed as the measured output noise spectrum divided by the mid-band gain.
Fig. 10. The measured transient input-referred noise waveform and its ampli-
tude histogram. The standard deviation of the input-referred noise is 2.05 μV,
which agrees with the noise spectrum measurement.
Therefore, the minimum current in the output stage to ensure
given phase margin can be obtained from (24). Substituting (23)
and (24) into (22), the NEF can be rewritten as
 design specification, and the −3-dB bandwidth ranges from 0.2
CL + Cf Cf
N EF > n 1 + η +p (25)
CC Cin
where p(= Iothers / (2Id1,2 )) is the ratio of the current in other
circuits to the first-stage current (p is 2/3 in this design). As
indicated by (24), because the closed-loop gain is relatively
large (Cin /Cf = 100) in this work, the minimum Id9,10 to ensure
stability is very small. For example, even if (CL + Cf ) is 5 times
as large as CC , the minimum Id9,10 is only about 0.1Id1,2 to
ensure a phase margin of 60◦ (η = 2.2), resulting in a minimum
NEF of 1.87 from (25). However, the value of Id9,10 influences
not only the stability but also the open-loop gain and output
linearity. To ensure enough open-loop gain and linearity, the
current in the output stage should be much larger than that given
by (24). In this design, Id,9,10 is assigned the same current as
Id1,2 to achieve the required open-loop gain and linearity based
on simulation. Therefore, the theoretical NEF can be calculated
as 2.29 according to (22).
E. Monte-Carlo Simulations
In order to evaluate the robustness of the amplifier to pro-
cess variations, a 500-run Monte-Carlo simulation is performed
under a 2-V supply voltage and a 1-V common-mode voltage.
The phase margin of the OTA is larger than 45 degree for all
cases, which ensures the stability of the amplifier. The mid-band
closed-loop gain has a mean value of 39.7 dB and a standard
deviation of 0.13 dB, which proves that the closed-loop gain of
7
the amplifier is almost independent of process variations. The
higher cutoff frequency, fH , showing a mean value of 210.5
Hz and a standard deviation of 14.5 Hz. Although the variation
of the fH is relatively large, the bandwidth is still within the
required range for ECG recordings. While the lower cutoff fre-
quency, fL ranges from 1 mHz to 30 mHz with a mean value of
15 mHz. The total harmonic distortion of the output is below 1%
with a 15 − mVpp input signal for all cases. Above Monte-Carlo
simulation results verify that the proposed amplifier is reliable
under process variations.
IV. MEASUREMENT RESULTS
The capacitive-feedback amplifier with the proposed current-
reused OTA is fabricated in a 0.35-μm CMOS technology with
die photo shown in Fig. 6, and the core area is about 300 μm ×
600 μm. Seen from the photo, most of the chip area is occupied
by the capacitors and the input transistors. The performances of
the amplifier are measured under a 2-V supply voltage, and the
common-mode voltage is 1 V. Measurement results show that
the amplifier draws a DC current of 160 nA from the supply.
And the current consumption is broken down as follows: 60 nA
for the input stage, 60 nA for the output stage and 40 nA for the
bias and common-mode feedback circuits. For a 20-Hz sinusoid
input with 15-mVpp amplitude, the rms current consumption
increases to about 190 nA.
The amplifier is designed with a closed-loop gain of 100,
with Cin of 40 pF, and Cf of 400 fF. The measured transfer
function of the amplifier is shown in Fig. 7. The mid-band gain
of the amplifier is 39.8 dB, which is slightly lower than the
to 200 Hz. The measured lower corner frequency is a little larger
than the simulated value. The difference is probably caused by
the leakage or the parasitic resistance of the feedback capacitor,
which decreases the effective resistance of the pseudo resistance
to the order of 1012 Ω.
CMRR and PSRR are calculated as the ratios of the differ-
ential gain to the common-mode gain and to the power-supply
gain, respectively. The measured CMRR and PSRR exceed 65
dB and 70 dB over the range of 0.2 to 200 Hz, respectively, as
shown in Fig. 7. To obtain the THD of the amplifier, a 10-bit
ADC with sampling rate of 500 S/s (SFDR > 80 dB) is used to
sample the output, and the spectrum is obtained by performing
a 1024-point FFT to the sampled data. Fig. 8 shows the fre-
quency spectrum for a 20-Hz sinusoid input signal with 15-mV
peak-to-peak amplitude. The THD of the amplifier under test in-
cluding 12 harmonic tones is obtained as 0.32%. Measurement
results on more samples show that the maximum input range is
15 mVpp to ensure a THD of less than 1%.
The measured input-referred noise spectrum of the amplifier
is shown in Fig. 9, which is obtained by dividing the output
noise spectrum by the mid-band gain of the amplifier. The total
input-referred noise is 2.02 μV rms integrated from 100 mHz to
10 kHz. The measured transient input-referred noise waveform
and its amplitude histogram is shown in Fig. 10. The standard
deviation of the input-referred noise is 2.05 μV, which agrees
with the value obtained from the noise spectrum measurement.
By using (19), the NEF of the amplifier is calculated to be 2.26
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
8 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
TABLE I
AMPLIFIER PERFORMANCES AND COMPARISONS
Fig. 11. Measured input-referred ECG signal from a subject’s chest.
from the measurement results. The low NEF is a result of the
current-reused architecture of the OTA.
The power efficiency factor (PEF) that includes the supply
voltage VDD is also an important parameter to evaluate the power
efficiency for biomedical amplifiers. As given in [9], PEF can
be calculated as
Ptot
P EF = N EF 2 · = N EF 2 · VDD (26)
Itot
The calculated PEF of this amplifier is 10.2.
The measured performances of the amplifier are summarized
in Table I, with comparison to other related works. The am-
plifiers in [8] and [9] adopt the chopper modulation technique
while others do not. The proposed amplifier achieves the
best NEF among the amplifiers with the 2-stage OTAs in the
comparison table. Although our NEF is a little larger than those
of the amplifier with single-stage OTA in [9] and the BPA2 in
[7], the proposed amplifier achieves much better linearity and
output range. The achieved linearity is also comparable to other
amplifiers with 2-stage OTAs in the comparison table. The PEF
for this work is not the best one, but it is better than the designs
in [1] and [4] which are fabricated in similar technologies.
The minimum supply voltage of proposed amplifier is mainly
limited by the high threshold voltages of the transistors in the
0.35-μm CMOS technology used. Fortunately, because of the
two-stage class-AB structure, the proposed design is suitable for
more advanced technologies with lower supply voltages while
maintaining a sufficient dynamic range. Therefore, a lower PEF
is expected to be achieved in more advanced technologies.
We also made a test board to verify that the amplifier can be
used as a preamplifier to record the ECG signals. For acquir-
ing the ECG signal with good quality, a driven-right-leg circuit
and a stand-alone differential-to-single-ended PGA are included
in the board. A typical three-electrode measurement was per-
formed with the reference electrode connected at the right leg of
the subject. The other two electrodes were at the subject’s chest
and connected to the differential input nodes of the proposed
amplifier. The acquired input-referred ECG signal is shown
in Fig. 11, which proves that the amplifier performs well for
recording of ECG signals. Although the proposed OTA aims at
ECG recordings, it can also be exploited to other biopotential
signals, such as electromyography (EMG), electrooculography
(EOG), with proper modifications in the transfer function of the
capacitive feedback network.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
ZHANG et al.: LOW-NOISE, LOW-POWER AMPLIFIER WITH CURRENT-REUSED OTA FOR ECG RECORDINGS
V. CONCLUSIONS
In this paper, we present a low noise and low power capacitive-
feedback amplifier based on a current-reused OTA, which meets
the stringent requirements of ECG recordings. The OTA em-
ploys inverter-based differential pairs in the first stage to im-
prove the power-to-noise efficiency, and class-AB output stage
to enhance the gm /I efficiency. By embedding the class-AB
control unit into the input stage, extra bias current branches are
removed to further reduce the power consumption. Fabricated
in 0.35-μm CMOS technology, measurement results show that
the amplifier achieves good performances in terms of linearity,
power and noise and has the ability to record ECG signals.
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Jie Zhang received the B.S. degree in microelec-
tronics engineering from Xi’an Jiaotong University,
Xi’an, China, in 2010, where he is currently work-
ing toward the Ph.D. degree. His research interests
include low-power analog and mixed signal circuits
and systems for biomedical applications.
Hong Zhang (M’14) received the B.S. degree in elec-
tronic engineering from Xi’an University of Technol-
ogy Xi’an, China, in 2000, and the Ph. D. degree in
electronic engineering from Xi’an Jiaotong Univer-
sity, Xi’an, China, in 2008, respectively. Since 2008,
he has been with the Department of Microelectronics,
Xi’an Jiaotong University, where he is currently an
Associate Professor. From June to September 2009,
he was a Visiting Scholar with KU Leuven and IMEC,
Belgium. From August 2016 to August 2017, he was
a Visiting Professor with the Department of the Elec-
trical and Computer Engineering, University of Toronto. His research interests
include high speed ADC and low-power biomedical IC design.
Quan Sun received the B.S. and M.S. degrees in
electronic engineering. from Xi’an Jiaotong Univer-
sity, Xi’an, China, in 2003 and 2006, respectively.
Since September 2015, he has been working toward
the doctorate degree with the Department of Micro-
electromics, Xi’an Jiaotong University. He was with
Beijing Shidai Minxin Technology Co., Ltd., from
2006 to 2011 as a Member of Technical Staff in the
area of high-performance converters. From 2011 to
2015, he was with Xi’an Aerosemi Technology Co.,
Ltd., where he was the Technical Director for Preci-
sion Nyquist Converters. His research interests include high precision ADC and
BMS IC design.
Ruizhi Zhang received the B.S., M.S., and Ph.D.
degrees n electronic engineering from the Depart-
ment of Electronic Engineering, Xi’an Jiaotong Uni-
versity, Xi’an, China, in 1982, 1987, and 1995,
respectively. From 1982 to 1984, he was with
Semiconductor Research Center, Ministry of Elec-
tronic Industry of China, where he worked on the
design and fabrication of MOSFET. Since 1988,
he has been with the Department of Microelec-
tronic, Xi’an Jiaotong University, and his current re-
search focuses on the low-power design of analog
CMOS ICs.