Analog and Mixed VLSI Design

Module :1
Analog building blocks
1.1-Need for CMOS analog and mixed signal designs, MOS Transistor
as sampling switch, active resistances, current source and sinks,
current mirror.
1.2-Voltage References: Band Gap References, General Considerations,
Supply-independent biasing, Temperature independent references,
PTAT current generation and Constant Gm biasing

1
 Analog building blocks

• Why Analog?
• Why Analog Design Difficult?
• Why Integrated?
• Why CMOS?

2
 Why Analog?

Speech signal:

Music signal:

EMG signal:
3
 Why Analog?

Birds voice

Seismic signal

ECG signal
4
 Why Analog?

Communication signal:

Nature is analog and hence at least “front-ends”

will be Analog followed by A to D converters and
later to DSP
Naturally occurring signals are analog-at least at
microscopic level 5
 Why Analog?

• We are surrounded by “digital” devices:

– digital cameras,
– digital TVs,
– digital communications (cell phones and WiFi),
– the Internet, etc.
• Why, then, are we still interested in analog circuits?
Isn’t analog design old and out of fashion?
• Will there even be jobs for analog designers?
6
 Why Analog?

Need of Processing of Natural Signals:

• The electrical version of natural signals may be
prohibitively small for direct digitization by the ADC

• The signals are also accompanied by unwanted, out-of-

band interferes

7
 Why Analog?

Amplifier boost
the signal

Analog filter
supresses the
out-of-band
components

Fig. 1: (a) Digitization of natural signal (b) Addition of amplification and filtering for higher
sensitivity 8
 Why Analog?

When Digital Signals Become Analog

• The use of analog circuits is not limited to analog
signals
• If a digital signal is so small and/or so distorted that a
digital gate cannot interpret it correctly
For example: consider a long USB cable carrying data rate
of hundreds of megabits per second between two laptops

9
 Why Analog?

• Laptop 1 delivers the data to the cable in the form of a sequence of ONEs and ZERO
• Unfortunately, the cable exhibits a finite bandwidth, attenuating high frequencies and
distorting the data as it reaches Laptop 2.
• This device must now perform sensing and processing, the former requiring an analog
circuit (called an “equalizer”) that corrects the distortion
• The cable attenuates high frequencies, so need to design the equalizer to amplify such
frequencies

10

Fig. 2: Equalization to compensate for high-frequency

attenuation in a USB cable.
 Why Analog?

Disk Drive Electronics:

• The data stored magnetically on hard disk is in binary form
• The data is read by a magnetic head and converted to electrical signal
• The amplitude is few millivolts, the noise content is very high, and the bits experience
substantial distortion
• The signal is amplified , filtered, and digitized for further processing

Fig. 3: Data stored and retrieved from hard disk 11

 Why Analog?

Wireless Receivers:
• The signal picked up by the antenna of a radio-frequency (RF) receiver, e.g. Cell phone,
exhibits an amplitude of a few millivolt
• The signal is accompanied by large interferers
• The receiver must amplify the low level signal

12

Fig. 4: Signal and interferers received by the

antenna of a wireless receiver
 Why Analog?

Optical Receivers:
• For transmission of high –speed data over very long distances, cables are generally prove
inadequate bcz of their limited bandwidth and considerable attenuation
• Thus the data is converted to light and transmitted over an optical fiber
• At the receiver end the light is converted to a small electrical current by photodiode
• The receiver must process this low level signal

Fig. 5: Optical fiber system

13
 Why Analog?

Sensors:

Fig. 6: (a) Simple accelerometer, (b) differential accelerometer 14

 Why Analog?

Microprocessors and Memories:

• Memories need high speed sense amplifiers

• In microprocessors many issues related to the

distribution and timing of data and clocks across large
chip
15
 Why Analog Design Difficult?

• Analog Design Challenges:

– Digital VLSI circuits- trade-off between speed and power dissipation and
area
– Analog VLSI circuits-multi-dimensional trade-off –speed, power
dissipation, gain, precision, supply voltage etc…
• Transistor Imperfections
• Declining Supply Voltages
• Power Consumption
• Circuit Complexity
• PVT Variations 16
 Why Integrated?

• The idea of placing multiple electronic devices on the same substrate was
conceived in the late 1950s
• In 60 years, the technology has evolved from producing simple chips
containing a handful of components to fabricating flash drives with one
trillion transistors as well as microprocessors comprising several billion
devices
• Gordon Moore predicted in the early 1970s, the number of transistors per
chip has continued to double approximately every one and a half years
• The minimum dimension of transistors has dropped from about 25 μm in
1960 to about 12 nm in the year 2015
• Tremendous improvement in the speed of integrated circuits
17
 Why CMOS?

• CMOS technologies rapidly captured the digital market: CMOS

gates dissipated power only during switching and required very
few devices, two attributes in sharp contrast to their bipolar or
GaAs counterparts
• The dimensions of MOS devices could be scaled down more
easily than those of other types of transistors
• The low cost of fabrication and the possibility of placing both
analog and digital circuits on the same chip so as to improve
the overall performance and/or reduce the cost of packaging
made CMOS technology attractive 18
 Why CMOS?

• Another critical advantage of MOS devices over bipolar

transistors is that the former can operate with lower
supply voltages. In today’s technology, CMOS circuits run
from supplies around 1 V and bipolar circuits around 2 V
• The lower supplies have permitted a smaller power
consumption for complex integrated circuits
• The intrinsic speed of MOS transistors has increased by
orders of magnitude in the past 60 years, exceeding that
of bipolar devices 21
 Levels of Abstraction

Figure 1.5 Abstraction levels in circuit design: (a) device level,

(b) circuit level, (c) architecture level, (d) system level. 22
Classification of transistors

23
n-Channel MOSFET EMD AND DMD

25
n-Channel enhancement-type MOSFET (emd)
NORMALLY OFF
DEVICE
28
29
n-Channel enhancement-type MOSFET (emd)
+ve threshold
voltage

30
n-Channel enhancement-type MOSFET (emd)
n-Channel enhancement-type MOSFET (emd)

Output (drain) characteristics 32

n-Channel enhancement-type MOSFET (emd)

Transfer characteristics Output (drain) characteristics

33
 p-Channel enhancement-type MOSFET
-ve
threshold voltage

34
p-Channel enhancement-type MOSFET

35
 n-Channel depletion-type MOSFET(dmd)

DMD MOSFET

NORMALLY ON DEVICE
37
 n-Channel depletion-type MOSFET
n-Channel depletion-
type MOSFET with VGS =
0 V and applied voltage
VDD
 n-Channel depletion-type MOSFET
Reduction in free carriers
in a channel due to a
negative potential at the
gate terminal

SS

39
n-Channel depletion-type MOSFET

40
 n-Channel depletion-type MOSFET
Output (drain) and transfer characteristics

41
N-channel and p-channel depletion mode mosfets

P-CHANNEL

42

N-CHANNEL DMD P-CHANNEL DMD

p-Channel depletion-type MOSFET
Symbols of depletion mode mosfets

44
 The MOS Transistor

Aluminum Polysilicon
 MOSFET as a SWITCH
Ideal Switch Characteristics
For a semiconductor device like a MOSFET to act as an ideal switch,
it must have the following features:
• During ON state, there should not be any limit on the amount of
current it can carry
• In OFF state, there should not be any limit on the blocking voltage
• When the device is in ON state, there should be zero voltage drop
• OFF state resistance should be infinite
• Operating speed of the device has no limits
46
MOSFET as a SWITCH

48
 MOSFET as a SWITCH
Practical Switch Characteristics
In a practical situation, a semiconductor device like a MOSFET has the following characteristics.
• During ON state:
– limited power handling capabilities
• limited conduction current
• Limited blocking voltage during OFF state
• Finite turn on and turn off times----- which limit the switching speed.
• Limited maximum operating frequency
• When the device is ON, there will be a finite on state resistance resulting in a forward voltage drop
• There will also be a finite off state resistance which results in a reverse leakage current.
• A practical switch experiences power loses during:
– on state,
– off state and also
– during the transition state (on to off or off to on).

49
50
• When operating as a switch:
– if the gate voltage, VG, is high --- the transistor “connects” the source and the drain
together
– if VG is low --- isolates the source and the drain

• For what value of VG does the device turn on?

• What is the “threshold” voltage?
• What is the resistance between S and D when the device is on (or off)?
• How does this resistance depend on the terminal voltages?
• Can we always model the path between S and D by a simple linear resistor?
• What limits the speed of the device? 51
 MOSFET Structure

• The lateral dimension of the gate along the source-drain path is called the length, L, and that
perpendicular to the length is called the width, W

• Leff = Ldrawn - 2LD,

where Leff is the “effective” length,
52
Ldrawn is the total length, and
LD is the amount of side diffusion
Simple NMOS device

Simple PMOS device

CMOS

53
MOS symbols
54
 55
Figure: (a) A MOSFET driven by a gate voltage; (b) formation of depletion region; (c) onset of inversion;
(d) formation of inversion layer
 QB 0 Qox
VT 0  GC  2 F  
Cox C ox
57
58
physical parameters affecting the threshold voltage of
a MOS structure
Four physical components of the threshold voltage:

QB Qox
VT  GC  2 F  
Cox Cox
QB 0 Qox
VT 0  GC  2 F  
Cox Cox
59
physical parameters affecting the threshold voltage of
a MOS structure
Four physical components of the threshold voltage:
(i) the work function difference between the gate and the
channel
(ii) the gate voltage component to change the surface
potential
(iii) the gate voltage component to offset the depletion
region charge, and
(iv) the voltage component to offset the fixed charges in
the gate oxide and in the silicon-oxide interface 60
physical parameters affecting the threshold voltage of
a MOS structure
(i) the work function difference between the gate and the
channel
• The work function difference ΦGC between the gate and
the channel
For metal gate

GC   F ( substrate)   M
For polysilicon gate

GC   F ( substrate)   F ( gate)

61
physical parameters affecting the threshold voltage of
a MOS structure
(ii) the gate voltage component to change the surface
potential
• Now, the externally applied gate voltage must be
2 F
changed to achieve surface inversion, i.e., to change
the surface potential by

62
physical parameters affecting the threshold voltage of
a MOS structure
(iii) the gate voltage component to offset the depletion
region charge
The depletion region charge density at surface inversion
Φs= -ΦF
QB 0   2q.N A . si .  2 F

63
physical parameters affecting the threshold voltage of
a MOS structure
• If the substrate (body) is biased at a different voltage
level than the source, which is at ground potential
(reference), then the depletion region charge density
can be expressed as a function of the source-to-
substrate voltage VSB

QB   2q.N A . si .  2 F  VSB

64
physical parameters affecting the threshold voltage of
a MOS structure
• The component that offsets the depletion region
charge is then equal to

QB 0

Cox

Where, Cox is the gate oxide capacitance per unit area

 ox
C ox 
t ox 65
physical parameters affecting the threshold voltage of
a MOS structure
(iv) the voltage component to offset the fixed charges in
the gate oxide and in the silicon-oxide interface
• There always exists a fixed positive charge density Qox
at the interface between the gate oxide and the silicon
substrate, due to impurities and/or lattice
imperfections at the interface
• The gate voltage component that is necessary to
Qox
offset this positive charge
 at the interface is
Cox 66
physical parameters affecting the threshold voltage of
a MOS structure
• For zero substrate bias (VSB=0), the threshold voltage Vt0 or
Vth0 is expressed as: QB 0 Qox
VT 0  GC  2 F  
Cox Cox

• For nonzero substrate bias, on the other hand, the depletion

charge density term must be modified to reflect the influence
of VSB upon that charge, resulting in the generalized threshold
voltage expression: QB Qox
VT  GC  2 F  
Cox Cox
67
Energy band diagram of p-type silicon semiconductor
• Fermi potential ΦF is the function of temperature and doping,
• Denotes the difference between the intrinsic Fermi level Ei and the Fermi level EF

E F  Ei For a p-type For a n-type

F  semiconductor semiconductor
q
kT ni kT ND
F p  ln F n  ln
q NA q ni
Acceptor concentration NA Donor concentration ND

k is Boltzmann constant q denotes the unit (electron) charge

Intrinsic material carrier concentration = ni = 1.45× 1010 cm-3

Thermal Voltage=VT= kT/q= 26mV at 300K 68

Energy band diagram of p-type silicon semiconductor

• Fermi potential ΦF is the function of temperature and

doping,
• Denotes the difference between the intrinsic Fermi
level Ei and the Fermi level EF
E F  Ei For a p-type For a n-type
F  semiconductor semiconductor
q
kT ni kT ND
F p  ln F n  ln
q NA q ni
Positive Fermi potential for n-type
Negative Fermi potential for p-type 69
 Linear and saturated operation
Three Regions of operation
– Linear/constant
resistance/triode/ohmic
region
– Saturation/ active/constant
current region
– Cut-off/off region

Cut-off Mode:
when VGS < VTH
70
 Linear and saturated operation
Linear/constant
resistance/triode/
ohmic region:
• For small drain-to-
source voltage
(VDS), the
characteristics are
Linear Mode:
when VGS ≥ VTH and linear
VDS ≤ VGS –VTH • Device behaves as 71

a voltage
 Linear and saturated operation
Saturation/ active/ constant
current region:
• For sufficiently large VDS the
transistor current (ID) saturates
• ID almost independent of VDS
• MOSFET behaves as a voltage
controlled current source,
with VGS controlling the
current

Saturation Mode:
when VGS ≥ VTH and
VDS ≥ VGS –VTH 72
Linear and saturated operation
Linear and saturated operation

74
Linear and saturated operation

75
 Linear and saturated operation
• Here, the source and the substrate terminals are connected to
ground, i.e., Vs = VB = 0.
• The gate-to-source voltage (VGS) and the drain-to-source
voltage (VDS) are the external parameters controlling the drain
(channel) current ID.
• The gate-to-source voltage is set to be larger than the
threshold voltage Vth to create a conducting inversion layer
between the source and the drain.
• We define the coordinate system for this structure such that
the x-direction is perpendicular to the surface, pointing down
76
into the substrate, and the y-direction is parallel to the surface
 Linear and saturated operation
• The y-coordinate origin (y = 0) is at the source end of
the channel
• The channel voltage with respect to the source will be
denoted by Vc(y)
• Now assume that the threshold voltage Vth is constant
along the entire channel region, between y = 0 and y =
L
• Next, assume that the electric field component Ey
along the y-coordinate is dominant compared to the
77
electric field component Ex along the x-coordinate.
 Linear and saturated operation
• This assumption will allow us to reduce the
current-flow problem in the channel to the y
dimension only
• Note that the boundary conditions for the channel
voltage VC are:

78
 Linear and saturated operation
• Also, it is assumed that the entire channel region
between the source and the drain is inverted, i.e.,

79
 Linear and saturated operation
• The channel current (drain current) ID is due to the
electrons in the channel region traveling from the source
to the drain under the influence of the lateral electric
field component Ey
• Let Q(y) be the total mobile electron charge in the surface
inversion layer
• This charge can be expressed as a function of the gate-to-
source voltage VGS and of the channel voltage V(y) as
follows: 80
 Linear and saturated operation

81
Figure: Simplified geometry of the surface inversion layer (channel region).
 Linear and saturated operation
Consider the incremental resistance dR of the differential
channel segment

82
 Linear and saturated operation
• Assuming that all mobile electrons in the inversion
layer have a constant surface mobility (μn), the
incremental resistance can be expressed as follows.
• The minus sign is due to the negative polarity of the
inversion layer charge QI

83
 Linear and saturated operation
• the channel (drain) current ID flows between the source
and the drain regions in the y-coordinate direction.
• Applying Ohm's law for this segment yields the voltage
drop along the incremental segment dy, in the y
direction.

84
 Linear and saturated operation
• This equation can now be integrated along the channel,
i.e., from y = 0 to y = L, using the boundary conditions
given

85
 Linear and saturated operation
• The left-hand side of this equation is simply equal to L
ID. The integral on the right-hand side is evaluated by
replacing QI(y)

86
87
 Linear and saturated operation
• Assuming that the channel voltage Vc, is the only
variable that depends on the position y, the drain
current is found as follows

88
 Linear and saturated operation
• Equation represents the drain current ID as a simple
second-order function of the two external voltages, VGS
and VDS. This current equation can also be rewritten as

89
 Linear and saturated operation
• where the parameters k and k' are defined as
Process transconductance parameter

Device transconductance parameter

W=width of channel, L=length of the

Aspect ratio channel
90
 Linear and saturated operation
Saturation Mode:
when VGS ≥ VTH and
VDS ≥ VGS –VTH

• Substitute VDS = VGS –VTH

The drain current ID becomes a function only of the gate-to-

source voltage VGS, 91

beyond the saturation boundary

We call VGS − VTH the “overdrive voltage” and W/L the
“aspect ratio”

If in above equation, VDS << 2(VGS − VTH), we have

92
Now the drain current is a linear function of VDS
each parabola can
be approximated by
a straight line
With the condition
VDS << 2(VGS−VTH),
we say the device
operates in the deep
triode region
93
Figure : Linear operation in deep triode region
The linear relationship implies that the path from the
source to the drain can be represented by a linear resistor
equal to:

94
• A MOSFET can operate as a resistor whose value is
controlled by the overdrive voltage (so long
as VDS << 2(VGS − VTH))

Figure: MOSFET as a controlled linear resistor.

MOSFETs operating as controllable resistors play a crucial role in many analog circuits. For example,
a voltage-controlled resistor can be used to adjust the frequency of the clock generator in a laptop
computer if the system must go into a power saving mode 95
 Overdrive voltage
• The overdrive voltage (VOV) is defined as the voltage
between transistor gate and source (VGS) in excess of
the threshold voltage (VTH) where VTH is defined as the
minimum voltage required between gate and source to
turn the transistor on (allow it to conduct electricity).
• Overdrive voltage (VOV) is also known as "excess gate
voltage" or "effective voltage."
• VOV = VGS − VTH
96
 Overdrive voltage
• VOV is important as it directly affects the output drain
terminal current (ID) of the transistor
• By increasing VOV, ID can be increased until saturation
is reached
• Overdrive voltage -- used to determine the region of
operation of the MOSFET
VDS< VGS-VTH i.e. VDS<VOV and VGS>VTH-----------linear
VDS> VGS-VTH i.e. VDS>VOV and VGS>VTH----------saturation
97
 Overdrive voltage
• In an NMOS transistor,
the channel region
under zero bias has an
abundance of holes
• By applying a negative
gate bias (VGS < 0) we
attract more holes, and
this is called
accumulation. 98
 Overdrive voltage
A positive gate voltage
(VGS > 0) will attract
electrons and repel
holes, and this is called
depletion because we
are depleting the
number of holes.

99
 Overdrive voltage
At a critical voltage called
the threshold voltage (VTH)
the channel will actually be
so depleted of holes and
rich in electrons that it will
INVERT to being n-type
silicon, and this is called
the inversion region.
100
 Overdrive voltage
As we increase this
voltage, VGS, beyond VTH,
we are said to be then
overdriving the gate by
creating a stronger
channel, hence the
overdrive is defined as
(VGS − VTH)
101
• What happens if the drain-source
voltage exceeds VGS − VTH?
• the drain current does not follow the
parabolic behavior for VDS >
VGS − VTH
• ID becomes relatively constant ----device
operates in the “saturation” region
• if VDS is slightly greater than
VGS − VTH, then the inversion layer stops
at x ≤ L, Figure: Saturation of drain current
• we say the channel is “pinched off”
102
103
ID is relatively independent of VDS

If ID is known, then VGS is obtained as

104
Figure: Saturated MOSFETs operating
as current source.

105
MOS Transconductance:
• MOSFET operating in saturation produces a current in response
to its gate-source overdrive voltage
• We may define a figure of merit that indicates how well a
device converts a voltage to a current
• We define the figure of merit as the change in the drain current
divided by the change in the gate-source voltage

106
108
• gm represents the sensitivity of the device: for a high gm, a small
change in VGS results in a large change in ID
• In analog design, we sometimes say a MOSFET operates as a
“transconductor” or a “V/I converter” to indicate that it
converts a voltage change to a current change.
• Interestingly, gm in the saturation region is equal to the inverse
of Ron in the deep triode region.

109
Figure: Approximate MOS transconductance as a function of overdrive and 110
drain current.
For PMOS devices, the drain current in linear and saturation
region:

111
Figure: Saturated MOSFETs operating as
current sources.

112
For a PFET, the transconductance in the saturation region is
expressed as:

113
For the arrangement shown in Figure, plot the
transconductance as a function of VDS.
• VDS ≥ Vb − VTH, M1 is in saturation, ID
is relatively constant
• As ID is constant, and we have

so gm also constant

114
For the arrangement shown in Figure, plot the
transconductance as a function of VDS.
• If the drain voltage falls below the
gate voltage by more than one
threshold, M1 enters the triode
region
• The drain current in triode region is:

115
For the arrangement shown in Figure, plot the
transconductance as a function of VDS.

• The transconductance drops in

the triode region
• For amplification, we usually
employ MOSFETs in saturation

116
 Second-Order Effects
• Body Effect
• Channel-Length Modulation
• Subthreshold Conduction

117
 Body Effect

• We tacitly assumed that the

bulk and the source of the
transistor were tied to ground.
• What happens if the bulk
voltage of an NFET drops
below the source voltage
• Since the S and D junctions
remain reverse-biased, we
surmise that the device
continues to operate properly,
but some of its characteristics
may change
118
What happens if the bulk voltage of an NFET drops below the source voltage?

Figure: NMOS device with negative bulk voltage.

119
 Figure: Variation of depletion region charge with bulk voltage.
VS = VD = 0, and VG is somewhat less than VTH, so that a depletion region is formed under the gate
but no inversion layer exists.
As VB becomes more negative, more holes are attracted to the substrate connection, leaving a
larger negative charge behind; the depletion region becomes wider
124
Figure: Variation of depletion region charge with bulk voltage.
125
 Figure: Variation of depletion region charge with bulk voltage.
• The threshold voltage is a function of the total charge in the depletion region because the gate
charge must mirror Qd before an inversion layer is formed.
• Thus, as VB drops and Qd increases, VTH also increases.
• This phenomenon is called the “body effect” or the “back-gate effect.”

Qd Qox
VT  GC  2 F   126

Cox Cox
where
Qd 0 Qox
VTH 0  GC  2 F  
Cox C ox

body-effect coefficient

VSB is the source-bulk potential difference

γ typically lies in the range of 0.3 to 0.4 V1/2

127
• Body effect is usually undesirable.
• The change in the threshold voltage often complicates the
design of analog (and even digital) circuits
• Device technologists balance Nsub and Cox to obtain a reasonable
value for γ .

128
 Channel-Length Modulation

129
Figure: Channel length modulation in an n-channel MOSFET operation in saturation mode.
Linear and saturated operation
Linear and saturated operation

131
Linear and saturated operation

132
• Consider the inversion layer charge QI that represents the total
mobile electron charge on the surface
• The inversion layer charge at the source end of the channel is

• The inversion layer charge at the drain end of the channel is

133
At the edge of saturation, i.e., when the drain-to-source voltage reaches VDSAT

Sub this value in equation

The inversion layer charge at the drain end becomes zero

In reality, the channel charge does not become exactly equal to zero, but it indeed
becomes very small.
134
• For VDS > VDSAT the channel is pinched-off at the drain end, i.e.,
at y = L
• If the drain-to-source voltage VDS is increased even further
beyond the saturation edge so that VDS > VDSAT an even larger
portion of the channel becomes pinched-off
• The effective channel length is reduced to

• where ΔL is the length of the channel segment with QI = 0

135
 --------------(A)

The above equation accounts for the actual shortening of the channel,
also called channel length modulation

Since L'< L, the saturation current calculated by using (A) will be larger
than that found by using (B) under the same bias conditions.

--------------(B) 136
The channel length shortening ΔL is actually proportional to the square
root of (VDS - VDSAT)

To simplify the analysis even further, we will use the following empirical
relation between Δ L and the drain-to-source voltage instead:

λ is an empirical model parameter, and is called the channel length 137

modulation coefficient
Assuming that λVDS << 1, the saturation current can now be written as:

This simple current equation prescribes a linear drain-bias dependence for

the saturation current in MOS transistors, determined by the empirical
parameter λ.

138
Figure: Current-voltage characteristics of an n-channel MOS transistor,
139
including the channel length modulation effect.
With channel-length modulation, the expressions for gm

140
 Subthreshold Conduction
• We have assumed that the device turns off abruptly as VGS
drops below VTH

• In reality, for VGS ≈ VTH, a “weak” inversion layer still exists and
some current flows from D to S if we apply positive VDS

• Even for VGS < VTH, ID is finite, but it exhibits an exponential

dependence on VGS , called “subthreshold conduction”

141
 Subthreshold Conduction
• We have assumed that the device turns off abruptly as VGS drops below VTH

• In reality, for VGS ≈ VTH, a “weak” inversion layer still exists and some current flows from D to S if we apply positive
VDS

• Even for VGS < VTH, ID is finite, but it exhibits an exponential dependence on VGS , called “subthreshold conduction”

142
 Subthreshold Conduction
• This effect can be formulated for VDS greater than roughly 100
mV as:

• Where I0 is proportional to W/L, ξ > 1 is a non-ideality factor,

and VT = kT/q

143
 MOS Device Capacitances
• In analog circuits, the capacitances associated with the
devices must also be taken into account so as to predict
the high-frequency behavior
• Oxide related MOSFET CAPACITANCES
 Overlap capacitances(voltage
independent )
 Capacitances which result from the interaction between the
gate voltage and the channel charge (voltage dependent)
• Junction related MOSFET CAPACITANCES
 Cross-sectional view and top view (mask view) of a typical n-channel MOSFET

Where LM = the mask length (drawn length) of the gate

L= the actual channel length is indicated by L
LD=The extent of both the gate-source and the gate-drain overlap
Lumped representation of the parasitic MOSFET
capacitances.
Oxide Related Capacitance
Overlap capacitances:
• The two overlap capacitances that arise as a result of this structural
arrangement are called CGD (overlap) and CGS (overlap)

where Cox = Ɛox/tox= oxide capacitance per unit area

 Cut-off region
Vgs≤ Vth
• No conducting channel that links the surface to the
source and to the drain
• Therefore, the gate-to-source and the gate-to-drain
capacitances are both equal to zero: Cgs = Cgd= 0.
 Linear Mode
• In linear-mode operation, the inverted channel
extends across the MOSFET, between the source
and the drain
• This conducting inversion layer on the surface
effectively shields the substrate from the gate
electric field; thus, Cgb = 0
• In this case, the distributed gate-to-channel
capacitance may be viewed as being shared
equally between the source and the drain,
 Saturation region
• The inversion layer on the surface does not extend
to the drain, but it is pinched off
• The gate-to-drain capacitance component is
therefore equal to zero (Cgd = 0) .
• The source is still linked to the conducting
channel, its shielding effect also forces the gate-
to-substrate capacitance to be zero, Cgb = 0.
Approximate oxide capacitance values for
three operating modes of the MOS
Three-dimensional view of the n' diffusion
region within the p-type substrate
• The n+ diffusion region forms a number of planar pn-
junctions with the surrounding p-type substrate,
indicated here with 1 through 5.
• The dimensions of the rectangular box representing the
diffusion region are given as W, Y, and Xj
Types and areas of the pn-junctions
 MOS Small-Signal Model

Figure: (a) Basic MOS small-signal model; (b) channel-length modulation represented
by a dependent current source; (c) channel-length modulation represented by a
resistor; (d) body effect represented by a dependent current source. 157

In many analog circuits, MOSFETs are biased in the saturation region, we derive the corresponding small-signal model
Basic MOS small-signal model

Apply a change to the gate-

source voltage, ΔV = VGS, where
VGS is a small-signal quantity. The
drain current changes by gmVGS
and is modeled by a voltage-
dependent current source tied
between the drain and source
terminals
158
 Small signal model with channel-length modulation effect

channel-length modulation represented channel-length modulation

by a dependent current source represented by a resistor

159
 Tied between D and S, the resistor is given by:

the output resistance, r0 affects

the performance of many analog
circuits
e.g. r0 limits the maximum it is assumed that λVDS << 1.

voltage gain of most amplifiers

160
 Small signal MOSFET model with body effect

• the bulk potential influences the

threshold voltage and hence the
gate-source overdrive
• with all other terminals held at a
constant voltage, the drain current
is a function of the bulk voltage
• the bulk behaves as a second gate
• Modeling this dependence by a
current source connected between body effect represented by a dependent current source
D and S

161
Small signal MOSFET model with body effect
body effect represented by a dependent current source

In the saturation region, gmb can be expressed as:

We also have

Thus,

162
where η = gmb/gm and is typically around 0.25
As expected, gmb is proportional to γ
Complete MOS small-signal model

163
PMOS Small-Signal Model

Figure: (a) Small-signal test of a PMOS device, and

(b) Small-signal model

164
 NMOS Versus PMOS Devices
• In most CMOS technologies, PMOS devices are quite inferior to
NMOS transistors
– Due to the lower mobility of holes, μpCox ≈ 0.5μnCox, yielding low
current drive and transconductance
• Moreover, for given dimensions and bias currents, NMOS
transistors exhibit a higher output resistance, providing more
ideal current sources and higher gain in amplifiers
• Incorporating NFETs rather than PFETs wherever possible is
preferred
165
 Current mirror

• A current mirror is a circuit designed to copy a current

through one active device by controlling the current in
another active device of a circuit, keeping the output
current constant regardless of loading

• Current mirror is used to provide bias currents and

active loads to circuits

166
 Current Mirrors
• MOS devices operating in saturation can act as a current source
• some DACs employ an array of current sources to produce an
analog output proportional to the digital input
• current sources, in conjunction with “current mirrors,” can
perform useful functions on analog signals

167
Basic Current Mirrors

Figure: Applications of current sources. 168

 Basic Current Mirrors
How should a MOSFET be biased so as to operate
as a stable current source?
To gain a better view of the issues, let us consider
the simple resistive biasing shown in Fig.
Assuming M1 is in saturation, we can write

Figure: Definition of current 169

by resistive divider
 • This expression reveals various PVT
(Process, Voltage, Temperature)
dependencies of Iout.
• The overdrive voltage is a function
Figure: Definition of current of VDD and VTH
by resistive divider
• Threshold voltage may vary by 50 to
100 mV from wafer to wafer
• Both μn and VTH exhibit temperature
dependence
• Thus, Iout is poorly defined
170
 Process variation (semiconductor)
• Process variation is the naturally occurring variation in the attributes of
transistors (length, widths, oxide thickness) when integrated circuits are
fabricated
• The amount of process variation becomes particularly pronounced at
smaller process nodes (<65 nm)
• The variation becomes a larger percentage of the full length or width of
the device and as feature sizes approach the fundamental dimensions
such as the size of atoms and the wavelength of usable light for
patterning lithography masks
• Process variation causes measurable and predictable variance in the
output performance of all circuits but particularly analog circuits due to
mismatch
• If the variance causes the measured or simulated performance of a
particular output metric (bandwidth, gain, rise time, etc.) to fall below or
rise above the specification for the particular circuit or device, it reduces
the overall yield for that set of devices.
 • The issue becomes more severe as
the device is biased with a smaller
overdrive voltage, e.g., to consume
less headroom and support greater
voltage swings at the drain
• With a nominal overdrive of, say,
200 mV, a 50-mV error in VTH results
in a 44% error in the output current
Figure: Definition of current 172
by resistive divider
Figure: Concept of current mirror.

The golden current generated by a bandgap

reference is “read” by the current mirror and
a copy having the same characteristics as
those of IREF is produced
For example Icopy=IREF or 2IREF 174
 The design of current sources in analog circuits is
based on “copying” currents from a reference, with
the assumption that one precisely-defined current
source is already available
While this method may appear to entail an endless
loop, it is carried out as illustrated in Fig.
A relatively complex circuit—sometimes requiring
external adjustments—is used to generate a stable
reference current, IREF, which is then “cloned” to
Figure: Use of a reference to generate
create many current sources in the system
various currents.
We study the copying operation here and the
reference generator (which is based on “bandgap”
techniques)

175
 • How do we generate copies of a reference current?
• In Figure 1, how do we guarantee that Iout = IREF?

• For a MOSFET, if ID = f (VGS), then VGS = f −1(ID)

• if a transistor is biased at IREF, then it produces

VGS = f −1(IREF) [Figure 2. (a)]

• Thus, if this voltage is applied to the gate and source
terminals of a second MOSFET, the resulting current
is Iout = f [ f −1(IREF)] = IREF [Figure 2 (b)]

Figure 1: Conceptual means • From another point of view, two identical MOS
of copying currents.
devices that have equal gate-source voltages and 176

operate in saturation carry equal currents (if λ = 0)

 • How do we generate copies of a reference
current?
• In Figure 1, how do we guarantee that
Iout = IREF?

• For a MOSFET, if ID = f (VGS), then VGS = f −1(ID)

• if a transistor is biased at IREF, then it produces

VGS = f −1(IREF) [Figure 2. (a)]

• Thus, if this voltage is applied to the gate and
source terminals of a second MOSFET, the
resulting current is
Iout = f [ f −1(IREF)] = IREF [Figure 2 (b)]
• From another point of view, two identical
Figure 2 (a) Diode-connected device providing
inverse function; (b) basic current mirror. MOS devices that have equal gate-source
177
voltages and operate in saturation carry equal
currents (if λ = 0)
 Neglecting channel-length modulation, we can write

Figure: basic current mirror.

The key property of this topology is that:

• it allows precise copying of the current with no dependence on process and temperature
• the translation from IREF to Iout merely involves the ratio of device dimensions, a quantity
178
that can be controlled with reasonable accuracy.
Find the drain current of M4 if all of the transistors are in saturation

We have

Also,

where

179
Calculate the small-signal voltage gain of the circuit shown in Figure

181
 Cascode Current Mirrors
For the simple mirror, we can write

and hence

Figure: Basic current mirror.

182
 Cascode Current Mirrors

VDS1 = VGS1 = VGS2, VDS2 may not equal VGS2 because of the
circuitry fed by M2

To suppress the effect of channel-length modulation, we

can:
(1) force VDS2 to be equal to VDS1, or
(2) force VDS1 to be equal to VDS2

Figure: Basic current mirror. To suppress the effect of channel-length modulation,

a cascode current mirror can be used
183
Ensure that VDS2 ------ is constant and equal to VDS1

Figure: (a) Cascode current source, (b) modification of mirror circuit to generate the cascode 184
bias voltage, and (c) cascode current mirror.
 But how do we ensure that VDS2 = VDS1?

Figure: Basic current mirror.

Transistor M3 is added in the basic current mirror circuit

Figure: Cascode current source
and Vb is chosen such that Vx=Vy, so Iout closely tracks IREF

185
 But how do GENERATE Vb?

Our objective is to ensure Vx=Vy

We must generate Vb such that

Vb − VGS3 = Vx= VDS1= VGS1

Or
Vb = VGS3 + Vx

This suggest that if a VGS is

Figure: modification of added to Vx, the required
mirror circuit to generate value of Vb can be obtained Figure: Cascode current source
the cascode bias voltage,
Vb = VGS3 + VGS1
Vb can be established by two diode-connected devices in
series, provided that 186
VGS0 + VGS1 = VGS3 + VGS1, and hence VGS0 = VGS3
 Cascode Current Mirrors

Figure: (a) Cascode current source, (b) modification of mirror circuit to generate the cascode 187
bias voltage, and (c) cascode current mirror.
Sizing of the transistors
• We typically select L2 = L1 and scale W2
(in integer units) with respect to W1 to
obtain the desired multiple of IREF
• Similarly, for VGS3 to be equal to VGS0, we
choose L3 = L0 and scale W3 with respect
to W0 by the same factor, i.e., W3/W0 =
W2/W1
• In practice, L3 and L0 are equal to the
minimum allowable value so as to
188
minimize their width, while L1 and L2
may be longer in some cases Figure: cascode current mirror
In Fig. A, sketch VX and VY as a function of IREF. If IREF requires 0.5 V to
operate as a current source, what is its maximum value?

 
From figure, we have Vx=Vy
For M1, VGS1=VDS1=VX
But,

189

Figure: A
In Fig. A, sketch VX and VY as a function of IREF. If IREF requires 0.5 V to
operate as a current source, what is its maximum value?
To find the maximum value of IREF, we have

Thus,
Figure: A

and hence

190

Figure: B
While operating as a current source
with a high output impedance and
accurate value, the topology of
Fig. 5.12(c) nonetheless consumes
substantial voltage headroom. For
simplicity, let us neglect the body i.e., two overdrive voltages plus one threshold voltage
effect and assume that all of the
transistors are identical. Then, the
minimum allowable voltage at node
P is equal to

191

Figure: (a) Cascode current source, (b) modification of mirror circuit to generate the cascode bias voltage, and (c) cascode current mirror.
Figure: (a) Cascode current source with minimum headroom voltage; (b) headroom
consumed by a cascode mirror.
192
Second Approach In order to avoid the VTH penalty in the voltage headroom of the above cascode
current source, we force VDS1 to be equal to VDS2 instead. To understand this principle, we return to
Fig. 5.14(a) and recognize that the VTH headroom consumption is eliminated only if Vb = VGS3+(VGS2−
VTH2), i.e., only if VDS2 is around one overdrive voltage. How can we then ensure that VDS1 = VDS2
(= VGS2 −VTH2)? Since M1 is a diode-connected device, it appears impossible to expect a VDS1 less than
one threshold.
A simple escape from the foregoing quandary is to create a deliberate voltage difference between
the gate and drain of M1 by a means of a resistor. Illustrated in Fig. 5.16(a), the idea is to choose
R1 IREF ≈ VTH1 and Vb = VGS3 +(VGS1 − VTH1). Now, VDS1 = VGS1 − R1 IREF ≈ VGS1 − VTH1, which is
equal to Vb − VGS3 and hence to VDS2.

Figure: (a) Use of IR drop to improve accuracy of current mirror, (b) generation of Vb, and 193
(c) alternative generation of Vb.
 Bandgap References
The objective of reference generation is to establish a dc voltage or current that is independent of the
supply and process and has a well-defined behavior with temperature.
In most applications, the required temperature dependence assumes one of three forms:
(1) proportional to absolute temperature (PTAT);
(2) constant-Gm behavior, i.e., such that the transconductance of certain transistors remains
constant;
(3) temperature independent
We can therefore divide the task into two design problems: supply-independent biasing and definition
of the temperature variation.
In addition to supply, process, and temperature variability, several other parameters of reference
generators may be critical as well. These include output impedance, output noise, and power
194

dissipation.
 Bandgap References
PROPORTIONAL TO ABSOLUTE TEMPERATURE (PTAT);

Absolute zero is the temperature at which the particles of matter (molecules and atoms) are at their
lowest energy points. Some people think that at absolute zero particles lose all energy and stop
moving. This is not correct. In quantum physics there is something called zero point energy, which
means that even after all the energy from particles has been removed, the particles still have some
energy

Absolute temperature, also called thermodynamic temperature, is the temperature of an object on a

scale where 0 is taken as absolute zero. Absolute temperature scales are Kelvin (degree units Celsius)
and Rankine (degree unit Fahrenheit).

Common temperatures in the absolute scale are:

0 °C (freezing point of water) = 273.15 K
25 °C (room temperature) = 298.15 K
100 °C (boiling point of water) = 373.15 K 195

0K (absolute zero) = - 273.15 Celsius

 Supply-Independent Biasing
We implicitly assumed that a “golden” reference current is available
if IREF does not vary with VDD, and channel length modulation of M2 and M3 is neglected, then ID2 and ID3
remain independent of the supply voltage.
The question then is—How do we generate IREF?

196

Figure: Current mirror biasing using an ideal current source

 Supply-Independent Biasing
As an approximation of a current source, we tie a resistor from VDD to the gate of M1
The output current of this circuit is quite sensitive to VDD:

197

Figure: Current mirror biasing using (a) an ideal current source and (b) a resistor.
 Supply-Independent Biasing
As an approximation of a current source, we tie a resistor from VDD to the gate of M1
The output current of this circuit is quite sensitive to VDD:

198

Figure: Current mirror biasing using a resistor.

 Supply-Independent Biasing
In order to arrive at a less sensitive solution, we
postulate that the circuit must bias itself, i.e., IREF
must be somehow derived from Iout .

The idea is that if Iout is to be ultimately

independent of VDD, then IREF can be a replica of Iout
.
Figure illustrates an implementation where M3
and M4 copy Iout , thereby defining IREF. In essence,
IREF is “bootstrapped” to Iout . With the sizes chosen
here, we have Iout = K IREF if channel-length
modulation is neglected.
since each diode-connected device feeds from a Figure: Simple circuit to establish
current source, Iout and IREF are relatively supply-independent currents.
199
independent of VDD
 Supply-Independent Biasing
if M1–M4 operate in saturation and λ ≈ 0, then the
circuit is governed by only one equation, Iout = K IREF

if we initially force IREF to be 10 μA, the resulting Iout of

K × 10 μA “circulates” around the loop, sustaining
these current levels in the left and right branches
indefinitely

To uniquely define the currents, we add another

constraint to the circuit i.e Rs
Figure: Addition of RS to define
resistor Rs decreases the current of M2 while the the currents
200
PMOS devices require that Iout = IREF because they
have identical dimensions and thresholds
We can write: VGS1 = VGS2 + ID2RS

Neglecting body effect, we have

and hence

201
As expected, the current is independent of the supply
Figure: Addition of RS to define
voltage (but still a function of process and temperature)
the currents
 Temperature-Independent References
Reference voltages or currents that exhibit little dependence on temperature prove essential
in many analog circuits

It is interesting to note that, since most process parameters vary with temperature, if a
reference is temperature-independent, then it is usually process-independent as well

How do we generate a quantity that remains constant with temperature?

We postulate that if two quantities having opposite temperature coefficients (TCs) are added
with proper weighting, the result displays a zero TC.

For example, for two voltages V1 and V2 that vary in opposite directions with temperature,
we choose α1 and α2 such that α1∂V1/∂T +α2∂V2/∂T = 0, obtaining a reference voltage,
VREF = α1V1 + α2V2, with zero TC. 202
 Rope pulls, Tug of war

• We must now identify two voltages that have positive and negative
TCs.
• Among various device parameters in semiconductor technologies,
the characteristics of bipolar transistors have proven the most
reproducible and well-defined quantities that can provide positive 203

and negative TCs

 We can compensate for this negative temperature drift by
summing this current with another current with an equally
strong positive temperature coefficient

We referred to this as a PTAT or Proportional To

Absolute Temperature current

The VBE of Q1 is impressed across R2 and the resulting

current flows through Q2 to become IREF, neglecting
the base currents of Q1 and Q2.

Here, IREF, will be equal to VBE divided by R2 and have the

strong negative temperature coefficient

This negative temperature coefficient of the current is

often referred to as CTAT or Complementary To
Absolute Temperature
Figure: Combining CTAT
and PTAT currents to make
a constant IREF

Figure: Combined CTAT and PTAT current sources makes

a constant
 Negative-TC Voltage
The base-emitter voltage of bipolar transistors or, the forward voltage of a
pn-junction diode exhibits a negative TC
For a bipolar device, we can write

Where VT --- volt equivalent of temperature, IS --- reverse saturation current

where
K is the Boltzmans constant (1.38066-23 J/K)
q is the charge of electron (1.6021910-19C)
206
T is the temperature of diode junction (oK)
At from temperature (T=300oK), VT = 26mv
 Negative-TC Voltage
A

IS --- reverse saturation current is proportional to

Where,
μ denotes the mobility of minority carriers and
ni is the intrinsic carrier concentration of silicon
The temperature dependence of these quantities is represented as
where m ≈ −3/2

where Eg ≈ 1.12 eV is the bandgap energy of silicon207

 Negative-TC Voltage

IS --- reverse saturation current is proportional to

The temperature dependence of these quantities is represented as
where m ≈ −3/2

where Eg ≈ 1.12 eV is the bandgap energy of silicon

Thus,

where b is a proportionality factor

208
 Negative-TC Voltage
We have, rearranging equation A

we can now compute the TC of the base-emitter voltage.

So, take the derivative of VBE with respect to T
Actually, we must know the behavior of IC as a function of the temperature
To simplify the analysis, we assume that IC is held constant
Thus,

209
 Negative-TC Voltage
we have,

Therefore,

210
 Negative-TC Voltage
we can write

• This Equation gives the temperature coefficient of the base-

emitter voltage at a given temperature T , revealing dependence
on the magnitude of VBE itself
211
• With VBE ≈ 750 mV and T = 300 K, we have ∂VBE/∂T ≈ −1.5 mV/K
 Positive-TC Voltage
if two bipolar transistors operate at unequal
current densities, then the difference between
their base-emitter voltages is directly proportional
to the absolute temperature

if two identical transistors (IS1 = IS2) are biased at

collector currents of nI0 and I0 and their base
currents are negligible, then

212
 Positive-TC Voltage

Thus, the VBE difference exhibits a positive temperature

coefficient:

213
this TC is independent of the temperature or behavior
of the collector currents
Calculate VBE in the circuit , where Q2 is formed as the parallel combination of m units,
each identical to Q1.
Neglecting base currents, we can write

The temperature coefficient is

therefore equal to (k/q) ln(nm). In
this circuit, the two transistors’
current densities differ by a factor
of nm.
214
 Bandgap Reference
With the negative- and positive-TC voltages obtained above, we can now develop a
reference that has a nominally zero temperature coefficient

We write,

where VT ln n is the difference between the base-emitter voltages of the two bipolar
transistors operating at different current densities

215
How do we choose α1 and α2?

With VBE ≈ 750 mV and T = 300 K,

we have,
∂VBE/∂T ≈ −1.5 mV/K

216
Let us now devise a circuit that adds VBE to 17.2VT
• the base currents are assumed to be negligible
• transistor Q2 consists of n unit transistors in parallel, and
• Q1 is a unit transistor

Suppose we somehow force VO1 and VO2 to be equal

Figure: Conceptual generation of

temperature-independent voltage

217
This circuit requires three modifications to become
practical:
• First, a mechanism must be added to guarantee that
VO1 = VO2
• Second, since ln n = 17.2 translates to a prohibitively
large n, the term RI = VT ln n must be scaled up by a
reasonable factor
• Third, VO2, which is somehow forced to
be equal to VO1, cannot become
temperature-independent because
VO2 ≈ VBE1 ≈ 800 mV whereas, for temperature
independence, we must have
VO2 = VBE2 + 17.2VT ≈ 1.25 V Figure: Conceptual generation of
temperature-independent voltage.
This circuit is an implementation
accomplishing all tasks:
• Here, amplifier A1 senses VX
and VY , driving the top
terminals of R1 and R2 (R1 = R2)
such that X and Y settle to
approximately equal voltages
• The reference voltage is
obtained at the output of the
amplifier
Figure : Actual implementation of
the concept shown in Fig
PTAT Current Generation

Figure: Generation of a PTAT current.

PTAT Current Generation

Figure: Alternative method of

generating a PTAT current.
PTAT Current Generation

Figure: Generation of a
temperature-independent voltage.
 Constant-Gm Biasing
The transconductance of MOSFETs plays a critical role
in analog circuits, determining such performance
parameters as noise, small-signal gain, and speed.

it is often desirable to bias the transistors such that

their transconductance does not depend on the
temperature, process, or supply voltage

A simple circuit used to define the transconductance is

the supply-independent bias topology Figure: Addition of RS to
define the currents
Recall that the bias current is given by

247
Gm- value independent
of the supply voltage and
MOS device parameters

248
249
250
251
252
253
254
255
256
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