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VDD
PA tracking Latch
Latch reseting regenrating
M5 M6
VDD
+ -
Vo Vo
Vo+
CL M9 CL
Vo
M7 M8
Vo-
VSS VSS
Vo Vo
1 1 Vo
0
o
V gm Vo /sCL 1 gm /sCL Vo
Vo t 0 Vo t 0 expt gm /CL
Vo+ Vo-
CL CL
Vo(t=0)
t Vo = 1V
M7 M8
Vo Vo(t=0) t/(CL/gm)
1V 100mV 2.3
CL Vo t
1V 10mV 4.6 t ln
gm Vo t 0
1V 1mV 6.9
1V 100V 9.2
Vm+ V m- =1 R9 R9
M1 M2 x Vo +
Vo-
Vo+ 2 2 Vo-
Vi M9 X
-1 -1
M7 M8
gm7 gm7
gm1 gm5R9 R9 1
A V1 A V2 , to be amplifier.
gm3 2 gm7R9 2 gm7
Vo 0 Vi 0 A V Vi 0 A V1A V2
-
10 100 V
Vo
10 10 V
Comparator fails to produce valid logic outputs within T/2 when input falls
into a region that is sufficiently close to the comparator threshold
Vi BER
1LSB
j
Vo t Vi 0 A V1A V2 expt gm /CL
Vos
Cascade preamp stages (typical flash comparator has 2-3 pre-amp stages)
Use pipelined multi-stage latches; pre-amp can be pipelined too
Vo+ Vo-
Cgs Cgd
CM
M9 jump
CL CL Vo+
M7 M8
Vo-
Kickback noise disturbs reference voltages, must settle before next sample
M3 M4 M5 M6
Differential pair mismatch:
2
W
Vos 1
Vos Vth Vov L
Vo+ V o- 2 2 2
W
M1 M2
Vi M9
4
L
M7 M8
g gm5R9
A V1 m1 A V2
VSS gm3 2 gm7R9
Preamp Latch
Vos,34 Vos,56
2 2 2 2
Total input-referred Vos,78 Vos,dyn
Vos Vos,12
2 2
comparator offset: A
2
A
2
A V2
2 2
A V1 A V2
2
V1 V1
2
A
P P SP D2 ,
2 2 1st term dominates
WL for small devices
where, W and L are the effective width and length, D is the distance
A Vth2
Threshold : Vth =
2
+ S Vth2D2
WL
2 A 2
Current factor : S 2D2
2
WL
W X X X X X X X X
L
10 identical resistors
L L
R1 RS with std R1 R2 RS 10 10R1 with std R2 ,
W W
10
R2 R j 2 10R12 R2 10R1
2
j1
R2 10R1 1 R1 R 1 1 Spatial
averaging
R2 10R1 10 R1 R A WL
N stages:
N
N
A0 A0
AN
1 j / 0 1 / 2
0
1
A 0N
A N 3dB , 3dB 0 2 1
N
OS ,in
A pre A pre
Resistorpull up :
A V gm1 RL
M3 Ip Ip M4
Vo + Vo-
gm1 I 2 W L 1
AV n
gm3 p I 2 Ip W L 3
Vi+ M1 M2 Vi-
Ip diverts current away from PMOS diodes (M3 & M4), reducing (W/L)3
Higher gain without CMFB
Needs biasing for Ip
M3 & M4 may cut off for large Vin, resulting in a slow recovery
M3 M5 M6 M4 1
ro3
-1
ro5
gm3 gm5
Vo + Vo-
Vid gm1Vid ro1 Vod
Vi+ M1 M2 Vi-
1 1 g r
gm1 // //ro1//ro3 //ro5 m1 o1
dm
DM gain : A V
M7 gm3 gm5 3
NMOS diff-pair loaded with PMOS diodes and a PMOS cross-coupled latch
High DM gain, low CM gain, good CMRR
Simple, no CMFB required
(W/L)34 > (W/L)56 needs to be ensured for stability
Ref: K. Bult and A. Buchwald, An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,
JSSC, vol. 32, pp. 1887-1895, issue 12, 1997.
M3 M4
RL RL
+
Vo Vo-
X
Vi+ M1 M2 Vi-
M5
M5 M6
Vi+ M1 M3 M4 M2 Vi-
Vi+ M1 M2 Vi-
I. Mehr and L. Singer, A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC, IEEE
JSSC March 2000, pp. 318-25.
Pre-amp
CML-Latch
A 0.9-V 60-W 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range
IEEE JSSC, vol. 43, no. 2, Feb. 2008
Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over
100-dB SFDR," IEEE JSSC, vol. 39, pp. 2139 - 2151, December 2004.
J. Lin and B. Haroun, "An embedded 0.8 V/480 W 6B/22 MHz flash ADC in 0.13
m digital CMOS Process using a nonlinear double interpolation technique," IEEE
JSSC, vol. 37, pp. 1610 - 1617, Dec. 2002.