Modeling The DAB Converter - V10

The Dual Active Bridge Converter
GSEP http://gsep.uc3m.es
U C 3 M The DAB converter 1
OUTLINE
1. DAB converter basics
1. Steady state, phase shift control
2. Basics on ZVS
3. DAB design
2. DAB Series Resonant converter
1. Steady State analysis
2. DABSRC design
3. Review of other bidirectional converters
4. Basic average modeling
1. DAB phase shift dynamic model
2. DAB model with output PI filter
3. DAB model with input filter: the Extra Element Theorem
4. DAB model with parasitics
5. DABSRC average model: introduction
5. Discrete time model
1. Fundamentals
2. DAB discrete model
3. DABSRC discrete model
6. Compensator calculation
7. Control of modular architectures
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
Dual Active Bridge Invention
Dual Active Bridge first reference
DAB general characteristics
• Two active bridges operating with

50% duty cycle. Phase shift between
them controls the power flow: lagging S1 S2 S5 S6 +
bridge receives power from the ilk Lk 1 n
leading bridge C
• Possible ZVS in a wide range: high Vg + vlk - + R
+ vo
vDAB2
efficiency. vDAB1
-
• Widely used in bidirectional - VL
applications: electric vehicle, solid -
S3 S4 S7 S8
state transformers, etc.
 High number of components, including a transformer

✓ Isolated
 Complex operation and control: eight switches
✓ High voltage ratio
 Cost ?
✓ Step-down or step-up in both directions
✓ High power density
✓ ZVS allowed
✓ Output current does not depend on output voltage
✓ Input current does not depend on input voltage
Basic operation (phase shift)
3
Example
S1,S4 S2,S3
1: Dual
S5,S8
Active
S6,S7
1 S1 S2 S5 S6 +
0
-1
ilk Lk 1 n
C R
-2
Vg + vlk - +
+ vo
-3
vDAB1 vDAB2
VDAB1 VDAB2 - -
VL
200 Vo -
100 S3 S4 S7 S8
Vg
0
-100
-200
Llk
Ilk Vlk
Vlk/5
15 3
Vg+Vo /n
10 2 + +
1 𝑣𝐷𝐴𝐵1 𝑣𝐷𝐴𝐵2
5 Vg-Vo /n
0 𝑛
0 -
-1 Typical Lk current waveform -
-5
-10 -2
-15 -3
0.0099 0.00990625 0.0099125 0.00991875 Circuir for 𝑖𝑙𝑘 calculation

Time (s)
Basic operation (phase shift)
S1,S4 S2,S3 S5,S8 S6,S7 iin io

3
2
1 S1 S2 S5 S6 +
0
-1
-2
ilk Lk 1 n
-3 C R
Vg + vlk - +
VDAB1 VDAB2 + vo
vDAB1 vDAB2
200 Vo
- -
100 Vg VL
0 -
-100 S3 S4 S7 S8
-200
Ilk iIin1
in
15
10
5 Input current Llk
0
-5
-10 𝑖𝑖𝑛 (𝑡) = 𝑖𝐿𝑘 𝑡 · 𝑠𝑖𝑔𝑛(𝑣𝐷𝐴𝐵1 )
-15 + +
𝑣𝐷𝐴𝐵1 𝑣𝐷𝐴𝐵2
Ilk n·io
Io*8
𝑛
-
15 -
10 Output current
5
0
-5
𝑖𝑜 (𝑡) = 𝑖𝐿𝑘 (𝑡) · 𝑠𝑖𝑔𝑛(𝑣𝐷𝐴𝐵2 )
-10
-15
Circuir for 𝑖𝑙𝑘 calculation
0.0099 0.00990625 0.0099125 0.00991875
GSEP http://gsep.uc3m.es Time (s)

𝒗𝑫𝑨𝑩𝟏 𝒗𝑫𝑨𝑩𝟐 𝒊𝑳𝒌𝒗𝑫𝑨𝑩𝟏
Static characteristics derivation T=Tsw/2
D·T
• Perfect efficiency is assumed
1 𝑇𝑠𝑤 𝑣𝐷𝐴𝐵2
𝑃𝑜 = 𝑃𝑖 = න 𝑖𝐿𝑘 · 𝑑𝑡
𝑇𝑠𝑤 0 𝑛 Llk
ilk
• Power in source V2 is due only to current produced by

+ +
source V1 (superposition principle) 𝑣𝐷𝐴𝐵2
𝑣𝐷𝐴𝐵1 V1 V2 𝑛
1 𝑇𝑠𝑤 𝑣𝐷𝐴𝐵2 -
-
𝑃𝑜 = න ((𝑖𝐿𝑘𝑣𝐷𝐴𝐵1 + 𝑖𝐿𝑘𝑣𝐷𝐴𝐵2 ) · ) 𝑑𝑡
𝑇𝑠𝑤 0 𝑛
1 𝑇𝑠𝑤 𝑣𝐷𝐴𝐵2
𝑃𝑜 = න (𝑖𝐿𝑘𝑣𝐷𝐴𝐵1 · ) 𝑑𝑡
𝑇𝑠𝑤 0 𝑛
• Because of the waveform symmetry, power can be
referred only to half switching period
𝑡𝑜 +𝑇
1 𝑣
𝑃𝑜 = න 𝑖𝐿𝑘𝑣𝐷𝐴𝐵1 · 𝐷𝐴𝐵2 𝑑𝑡
𝑇 𝑡0 𝑛
𝒗𝑫𝑨𝑩𝟏 𝒗𝑫𝑨𝑩𝟐 𝒊𝑳𝒌𝒗𝑫𝑨𝑩𝟏
Static characteristics derivation T=Tsw/2
D·T
𝑡𝑜+𝑇
1 𝑣
𝑃𝑜 = න 𝑖𝐿𝑘𝑣𝐷𝐴𝐵1 · 𝐷𝐴𝐵2 𝑑𝑡
𝑇 𝑡0 𝑛
1 0 𝑉𝑔 𝑉𝑔 𝑇 𝑉𝑜 1 𝐷𝑇 −𝑉𝑔 𝑉𝑔 𝑇 𝑉𝑜
𝑃𝑜 = න 𝑡+ 𝑑𝑡 + න 𝑡+ 𝑑𝑡
𝑇 −(𝑇−𝐷𝑇) 𝐿𝑙𝑘 𝐿𝑙𝑘 2 𝑛 𝑇 0 𝐿𝑙𝑘 𝐿𝑙𝑘 2 𝑛
𝑉𝑜
𝑇 − 𝐷𝑇 𝑛
0 𝐷𝑇 𝐷𝑇
1 𝑉𝑔 𝑉𝑜 𝑇 𝑇
𝑃𝑜 = න 𝑡+ 𝑑𝑡 + න −𝑡 + 𝑑𝑡
𝑇 𝐿𝑙𝑘 𝑛 −(𝑇−𝐷𝑇) 2 0 2
1 𝑉𝑔 𝑉𝑜 − 𝑇 − 𝐷𝑇 2 𝑇 − 𝐷𝑇 2 𝑇
𝑃𝑜 = + (𝑇 − 𝐷𝑇) + + 𝐷𝑇
𝑇 𝐿𝑙𝑘 𝑛 2 2 2 2
𝑉𝑔 𝑉𝑔 𝑇 −𝑉𝑔 𝑉𝑔 𝑇
𝑡+ 𝑡+
𝐿𝑙𝑘 𝐿𝑙𝑘 2 𝐿𝑙𝑘 𝐿𝑙𝑘 2
1 𝑉𝑔 𝑉𝑜 𝑇 2 −1 − 𝐷2 + 2𝐷 + 1 − 𝐷 𝑇 2 −𝐷2 + 𝐷
𝑃𝑜 = +
𝑇 𝐿𝑙𝑘 𝑛 2 2
1 𝑉𝑔 𝑉𝑜 𝑇 2 𝐷 − 𝐷2 𝑇 2 −𝐷2 + 𝐷 𝑉𝑔 𝑉𝑜
𝑃𝑜 = + 𝑃𝑜 = 𝑇 𝐷(1 − 𝐷)
𝑇 𝐿𝑙𝑘 𝑛 2 2 𝐿𝑙𝑘 𝑛
Static characteristic
Input current Output current
𝑖𝑖𝑛 (𝑡) = 𝑖𝐿𝑘 𝑡 · 𝑠𝑖𝑔𝑛(𝑣𝐷𝐴𝐵1 ) 𝑖𝑜 (𝑡) = 𝑖𝐿𝑘 (𝑡) · 𝑠𝑖𝑔𝑛(𝑣𝐷𝐴𝐵2)
S1,S4 S2,S3 S5,S8 S6,S7
3
2
1 𝐼1
𝑖𝐿𝑘 𝑖𝑖 𝑛 · 𝑖𝑜
0 𝐼2
-1
-2
-3 0
VDAB1 VDAB2
Vo −𝐼2 𝐷·𝑇
200
𝐷·𝑇
100 Vg −𝐼1
0 𝑡1 𝑡2 𝑇
-100 𝑇
-200 𝑇
Ilk IIin1
in • The output average current depends only on the
15
10 input voltage
5
0
-5 𝑃𝑜 𝑇·𝐷· 1−𝐷
-10
𝐼𝑜 = = 𝑉𝑔 ·
-15
𝑉𝑜 𝑛 · 𝐿𝑘
• The input average current depends only on the
Ilk n·Io
Io*8
15
output voltage
10
5
0 𝑃𝑜 𝑇·𝐷· 1−𝐷
-5 𝐼𝑖 = = 𝑉𝑜 ·
-10
𝑉𝑔 𝑛 · 𝐿𝑘
-15
0.0099 0.00990625 0.0099125 0.00991875
GSEP http://gsep.uc3m.es Time (s) Current source behavior!
Static characteristic
Iin Io
• Output voltage (resistive load, 𝑉𝐿 = 0) S1 S2 S5 S6 +
𝑅·𝑇 ilk Lk 1 n
𝑉𝑜 = 𝐼𝑜 · 𝑅 = 𝑉𝑔 ·𝐷· 1−𝐷 C
𝑛 · 𝐿𝑙𝑘 + Vlk - R
Vg + + Vo
• Voltage ratio (normalized) VDAB1 VDAB2
- -
VL
𝑉𝑜 -
𝑀 = 𝑛 = 1 − 𝐷 · 𝐷 · 𝑘; S3 S4 S7 S8
𝑉𝑔
𝑅·𝑇
𝑘=
𝑛2 𝐿𝑙𝑘
If the load is a voltage source:

𝑉𝑔 · 𝑉𝑜 · 𝑇
𝑃𝑜 = 𝐼𝑜 · 𝑉𝑜 = · 𝐷 · 1 − 𝐷 = 𝑃𝑚𝑎𝑥 · 4 · 𝐷 · 1 − 𝐷
𝑛 · 𝐿𝑙𝑘
Static characteristic: phase shift values
• Symmetric behavior around D=0.5

• Only D<0.5 is used (lower rms currents)
𝐷 = 0.5
D(1-D)
𝐷 = 0.25 𝐷 = 0.75
D
𝐷=0 𝐷=1
Factor D(1-D)
Load is a voltage source
Static characteristic: variation of M for constant D
Inductor current D=0.25; M=0.2,0.4,…,2; constant Vg

I(L1)_01 I(L1)_02 I(L1)_03 I(L1)_04 I(L1)_05 I(L1)_06 I(L1)_07 I(L1)_08 I(L1)_09 I(L1)_10
M=2
50
-50
M=1
0.09997 0.099975 0.09998 0.099985 0.09999 0.099995 0.1

Time (s)
StaticCharacteristic_1.psimsch
M=0.2 Slopes change with M
Values of inductor current at the swtiching instant change
Static characteristic: variation of D for constant M
Inductor current M=1, M=0,5; D=0.05,0.1,…,0.5; constant Vg

I(L1)_10 I(L1)_02 I(L1)_03 I(L1)_04 I(L1)_05 I(L1)_06 I(L1)_07 I(L1)_08
60
60 60
40
40 40
20
20 20
0
0 0
-20
-20 -20
-40
-40 -40
-60
-60 -60
0.09950625 0.0995125 0.09951875 0.099525 0.09953125

0.09998 0.099984 0.099988 0.099992 Time (s)
0.099996 0.1 0.09998 0.099984 0.099988 0.099992 0.099996 0.1
Time (s) Time (s)
StaticCharacteristic_2.psimsch
Slopes are the same
Values of inductor current at the switching instants differ for diferente M values
Static characteristic: variation of D for constant R load
Inductor current and output voltage for D=0.05,0.1,…,0.5; constant Vg, Rload
100
75
50
25
-25
-50
-75
-100
Vo_01 Vo_02 Vo_03 Vo_04 Vo_05 Vo_06 Vo_07 Vo_08 Vo_09 Vo_10
600
500
400
300
200
100
0.09997 0.099975 0.09998 0.099985 0.09999 0.099995 0.1

Time (s)
Slopes change with D StaticCharacteristic_3.psimsch

M and D are linked through R value
Static characteristic: constant Vo, resistive load and Volt source load
Constant output voltage, constant output power, D=0.05,0.1,…,0.5
In the case of resistive load, input voltage is changed with D in order to keep
the output voltage at the same value
In the case of voltage source load, input voltage in changed to keep the same
output power
I(L1)_01 I(L1)_02 I(L1)_03 I(L1)_04 I(L1)_05 I(L1)_06 I(L1)_07 I(L1)_08 I(L1)_
150
150 150
100 100 100
50 50 50
0 0
0
-50 -50
-50
-100 -100
-100
-150 -150
Resistive load with constant output voltage is equivalent to voltage source load with constant output power
-150
0.09998 0.099984 0.099988 0.099992 0.099996 0.1 0.09998 0.099984 0.099988 0.099992 0.099996 0.1
Time (s) Time (s)
GSEP http://gsep.uc3m.es StaticCharacteristic_4.psimsch

0.09998 0.099984 0.099988
Time (s)
0.099992 0.099996 0.1 StaticCharacteristic_5.psimsch

M-D characteristic
As DAB has current source behavior, output voltage depend on the load
resistance (resistive load)
k parameter depend on load resistance
𝑉𝑜
𝑅·𝑇
𝑀 = 𝑛 = 1 − 𝐷 · 𝐷 · 𝑘; 𝑘=
𝑉𝑔 𝑛2 𝐿𝑙𝑘
k=100
k=50
k=20
M
k=10
Operating area for 1<M<2

and Pmin<Po<2Pmin
GSEP http://gsep.uc3m.es D

Bidirectionality
2 1 1
Iin Io
Transferred Power
S1 S2 S5 S6 +
ilk Lk 1 n
C R
Vg + Vlk - +
+
VDAB2 Vo
VDAB1
- - V
L
S3 S4 S7 S8 -
2
Phase shift D
Static characteristic: equivalent circuit
• The output average current depends only on the input voltage
𝑇·𝐷· 1−𝐷
𝐼𝑜 = 𝑉𝑔 ·
𝑛 · 𝐿𝑘
• The input average current depends only on the output voltage
𝑇·𝐷· 1−𝐷
𝐼𝑖 = 𝑉𝑜 ·
𝑛 · 𝐿𝑘
1:n
+
Vg Ii n·Io C R 𝑉𝑜
-
Ideal
Transformer
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
Switching losses
• Swtiching losses have to be minimized

• As the most common DAB implementations use MOSFET, only turn-on ZVS is
considered in detail
TURN-ON Losses TURN-OFF Losses

Hard switching
VDS
VDS
ID ID
VGS VGS
t t
ZVS ZCS
Soft switching
VDS ID VDS
ID
VGS
VGS
t t
NO Turn-on losses NO Turn-off losses
ZVS: basic switching cell with current source
+ vgs1
vDS1 C1 vgs3
S1 -
S1 turn on S3 turn on
i
Vg
vDS1
Charging C3
S3
+ Discharging C1
vDS3
vDS3 C3
-
Charging C1
• Dead time between vGS1 and vGS3 Discharging C3
• Current i is positive when S3 is turned
I i>0
on and negative when S1 is turned off
• During the dead times the current i i
charges/discharges the parasitic
capacitances of the MOSFETs (C1 and
C3)
• When S1 or S3 are turned on, the -I
corresponding capacitance is already i<0
discharged and the antiparallel diode is
conducting Turn-on S1 Turn-offS1
Turn-off S3 Turn-on S3
Checking ZVS 1
Vs1 Vs2
0.8
0.6
vgs3
Vs1 vVs2
gs1
+ 0.4
vDS1 C1 1
0.2
S1 - 0.8
0
0.6
i 0.4
VDS1 VDS2
Vg 2
0.2 1.5
0 1
MOSFET
S3 conduction
vDS1 vDS3 0.5 voltage drop
+ VDS1 VDS2
vDS3 C3 120
0
- 100 -0.5 Diode forward

80
voltage drop
-1
60 0.00495313 0.00496875 0.00498438 0.005
40
• With ZVS, when the transistor is
Time (ms)
20
turned on, its body diode is 0
-20
conducting: the forward voltage
drop in the diode can be seen in the iIa
waveforms 2
• In the practice it can be observed if 1

0
the waveforms are clean -1
-2
-3
0.005 0.0055 0.006 0.0065

Time (ms)
ZVS in a Synchronous Buck converter
HS (high side)-switch
S1 C1
S3 C3
LS (low side)-switch
Synchronous Buck converter

• Controlled switch instead free wheeling diode
• Negative current is allowed in the inductor
• If the current ripple is high enough, turn on ZVS can be achieved in both switches
• Inductor acts as a current source during switches transitions
• Sync Buck = Switching Cell + LC filter
• GaN switches: equivalent behavior to MOSFET, although they are totally different internally
Experimental waveforms: inductor current and switching cell
voltage
+
C1 vDS1
S1 -
i
Vg
S3 +
C3 vDS3
-
Synchronous Buck converter

• Controlled switch instead free wheeling diode
• Negative current is allowed in the inductor
• If the current ripple is high enough, turn on ZVS can be achieved in both switches
• Inductor acts as a current source during switches transitions
• Sync Buck = Switching Cell + LC filter
• GaN switches: equivalent behavior to MOSFET, although they are totally different internally
Transitions of LS and HS switches
Soft Diode Soft Diode

transition conduction transition conduction
Diode voltage drop
Diode voltage drop
Dead time
Dead time
HS-switch turn on: LS-switch turn on:

• Too long dead time • Too long dead time
• Soft transition • Soft transition much faster:
• Antiparallel diode turns-on higher current value during
the switching process
• Antiparallel diode turns-on
• Easy to achieve ZVS
HS-switch turn-on
HS-switch turn-on
No ZVS achieved
• Too short dead time for the current level at
the switching instant
• Uncomplete soft transition
• Significant switching losses are produced
Optimal transition
• Adjusted dead time
• Complete soft transition
• Antiparallel diode don’t conduct
Minimum dead time calculation for ZVS
+
vDS1 C1 C1 C1
S1 - Vg
i i i
Vg Vg
S3
+ + +
vDS3 C3 vDS3 C3 vDS3 C3
- - -
• First let’s assume S1 is off and • S1 still off and S3 is turned off • Once S3 is fully off, minimum
S3 is conducting (i <0) • C3 is charged to the input dead time calculation
• S1 is blocking Vg, so C1 is voltage and C1 is discharged • if current i is still negative, the
charged to the input voltage diode D1 of S1 will conduct
Minimum dead time calculation for ZVS
+
vDS1 C1 C1 C1
S1 - Vg
i i i
Vg Vg
S3
+ + +
vDS3 C3 vDS3 C3 vDS3 C3
- - -
i
Equivalent circuit for the transition (turn-on of S1)
• To achieve ZVS vDS3 has to reach Vg within the dead time tdmin +
vDS3
• Assuming current i is negative and constant during the transition C1 C3
-
−𝑖 ∆𝑣𝐷𝑆3 = 𝑉𝑔 𝐶1 + 𝐶3
∆𝑣𝐷𝑆3 = · ∆𝑡 𝑡𝑑𝑚𝑖𝑛 = · 𝑉𝑔
𝐶 ∆𝑡 = 𝑡𝑑𝑚𝑖𝑛 𝐼
𝐶 = 𝐶1 + 𝐶3
*This is the minimum time. If t is much greater than
𝑖 = −𝐼
this, losses in D1 have to be taken into account
Minimum dead time for ZVS example
Minimum dead time for ZVS check
Vgs58 Vgs67 Vgs58 Vgs67
1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
VA2 VB2 VA2 VB2

300 300 90ns
200 200
100 100
0 0
-100 -100
I9 I9
1 1
0.5 0.5
0 0
-0.5 -0.5
-1 -1
-1.5 -1.5
0.008716 0.008718 0.00872 0.008722 0.008724 0.008726 0.00872172 0.00872176 0.0087218 0.00872184 0.00872188
Time (s) Time (s)
𝐶1 + 𝐶3 250𝑝𝐹 + 250𝑝𝐹
𝑡𝑑𝑚𝑖𝑛 = · 𝑉𝑔 = · 220𝑉 = 90.2𝑛𝑠
𝐼 1.22 𝐴
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
ZVS in DAB (phase shift)
3
1 S1 S2 S5 S6 +
0
-1
ilk Lk 1 n n·ilk
C R
-2
Vg + vlk - +
+ vo
-3 vDAB2
vDAB1
VDAB1 VDAB2 - -
200 Vo -
T
100 S3 S4 S7 S8
Vg
0
-100 D·T
-200
Ilk Vlk/5 ZVS conditions:

15
10
I1 • For S1,S4: ilk>0 when they are turned on I1>0
5 • For S2,S3: ilk<0 when they are turned on -I1<0
0 I2
-5 • For S5,S8: ilk<0 when they are turned on -I2<0
-10
• For S6,S7: ilk>0 when they are turned on I2>0
-15 -I1
0.0099 0.00990625 0.0099125 0.00991875
Time (s) I1>0 ZVS in primary bridge
-I2 I2>0 ZVS in secondary bridge
Basic operation (phase shift): ZVS behavior
𝐷 = 0.5
𝐷 = 0.25
𝐷=0 Normalized average

output current
SofSWitchingExample3_DAB.psimsch
Basic operation (phase shift): ZVS behavior detail
• D=0.2 • D=0.4
• Only ZVS in one bridge (one • ZVS in both bridges (every
transition is fast, only one transition takes several
simulation time step) simulation steps)
I(L1)_02 Vlk_02/5 I(L1)_05 Vlk_05/5
10 15
10
5
5
0 0
-5
-5
-10
-10 -15
VB1_02 VB1_05
40 40
30 30
20 20
10 10
0 0
-10 -10
VB2_02 VB2_05
120 250
100 200
80
150
60
100
40
50
20
0 0
-20 -50
0.009925 0.0099275 0.00993 0.0099325 0.009925 0.0099275 0.00993 0.0099325

Time (s) Time (s)
SofSWitchingExample3_DAB.psimsch
Compare with SofSWitchingExample2_DAB.psimsch
ZVS in DAB (phase shift)
3
1 S1 S2 S5 S6 +
0
-1
ilk Lk 1 n n·ilk
C R
-2
Vg + vlk - +
+ vo
-3 vDAB2
vDAB1
VDAB1 VDAB2 - -
200 Vo -
T
100 S3 S4 S7 S8
Vg
0
-100 D·T
-200
𝑇 𝑉𝑜 𝑀−1
Ilk Vlk/5 𝐼1 = · 𝑉𝑔 − · 1 − 2𝐷 𝐷>
2 · 𝐿𝑙𝑘 𝑛 2𝑀
15
I1
10
ZVS in primary bridge
5
I2 (turn on of transistors)
0
-5
𝑇 𝑉𝑜 1−𝑀
-10 𝐼2 = · − 𝑉𝑔 · 1 − 2𝐷 𝐷>
-15 -I1 2 · 𝐿𝑙𝑘 𝑛 2
0.0099 0.00990625 0.0099125 0.00991875
Time (s) ZVS in secondary bridge
-I2 (turn on of transistors)
How to design taking into account ZVS
Input data:
• Power range (Pmin, Pmax)
• Input voltage range (Vinmin, Vinmax)
• Output voltage (regulated)
Output data
• n
• Llk
• Ensure ZVS in a given range
• D range
Graphical representation: axis (D,M)
ZVS limits
• Graphical representation of possible combinations of d and M to ensure ZVS
• ZVS can be lost for small d values, depending on the M value
• Approximation: Coss value is not taken into account. Actual boundaries can differ slightly from ideal
ones.
No ZVS for 1
primary 𝑀=
1 − 2𝐷
(leading)
bridge Always ZVS for secondary bridge
ZVS in primary bridge lost when d<0.14
𝑀 = 1.4
For each M value, d depends

𝑉𝑜
on the load (R or Io)
𝑀= 𝑛 𝑀 = 1 Always ZVS for both bridges
𝑉𝑔
Always ZVS for primary bridge
ZVS in primary bridge lost when d<0.2
𝑀 = 0.6
No ZVS for
secondary
(lagging) bridge 𝑀 = 1 − 2𝐷
Reactive power
Input total charge
Input negative charge 𝑇2 · 𝐷 · 1 − 𝐷 Output total charge
𝑄𝑖 = 𝐼𝑖 · 𝑇 = 𝑉𝑜 ·
1 𝑛 · 𝐿𝑘
𝑄𝑖− = 𝑡1𝐼1 𝑇2 · 𝐷 · 1 − 𝐷
2 𝑄𝑜 = 𝐼𝑜 · 𝑇 = 𝑉𝑔 ·
𝑛 · 𝐿𝑘
𝐼1
𝑖𝐿𝑘 𝑖𝑖 𝑛 · 𝑖𝑜
𝐼2
Output negative charge
0
1
𝐷𝑇 𝑄𝑜− = 𝑡 𝐼
−𝐼2 2 22
𝐷𝑇
−𝐼1
𝑡1 𝑡2 𝑇
𝑇
𝑡1 + 𝑡2 = 𝑑𝑇 ONLY VALID WHEN I1 >0, I2>0
𝑇
𝜆𝑜 and 𝜆𝑖 are equivalent to reactive current percentages

𝑄𝑜− 𝑄𝑖−
𝜆𝑜 = 𝜆𝑖 =
𝑄𝑜 𝑄𝑖
𝜆𝑡𝑜𝑡𝑎𝑙 = 𝜆𝑜 + 𝜆𝑖 is a measurement of reactive power and can be limited during the design
2
2𝐷 − 1 + 𝑀 2 2𝐷 − 1 𝑀 + 1
𝜆𝑡𝑜𝑡𝑎𝑙 = 𝜆𝑜 + 𝜆𝑖 = +
8𝐷 1 − 𝐷 1 + 𝑀 8𝐷 1 − 𝐷 𝑀 1 + 𝑀
Reactive power & ZVS
𝑉𝑜
𝑀= 𝑛
𝑉𝑔
No ZVS for primary
(leading) bridge
𝜆𝑡𝑜𝑡𝑎𝑙 = 50%
No ZVS for
secondary
(lagging)
bridge
𝑉𝑜
𝑀= 𝑛
𝑉𝑔
No ZVS for primary
(leading) bridge
𝜆𝑡𝑜𝑡𝑎𝑙 > 20%

(too much reactive power)
No ZVS for
secondary
(lagging)
bridge
*Based on “Análisis de arquitecturas multipuerto para la alimentación de sistemas electrónicos con múltiples flujos de Energía”, A.
Rodriguez Alonso, Tesis Doctoral, Universidad de Oviedo 2013
PSIM validation
Pmax=1000
Vonom=200
Vo_03/10/Vin1_03 Rdson1=0.1m
1.403 Rdson2=0.1m
1.402 ESRL=0.2m
1.401 L=0.299u
1.4
n=10
1.399
1.398 File D=0.4
1.397 Voltage ratio M T=10u
1.396 DeadTime=0
Coss=25p
0.5*(Io_03-Io_03*SIGN(Io_03)) 0.5*(Io_03+Io_03*SIGN(Io_03))
Rload=Vonom^2/Pmax
15 M=Rload*T/2/(n^2*L)*Dparam*(1-Dparam)
10 Vin=Vonom/(n*M)
5
0
-5
-10
-15 Output current Lambda parameter
0.5*(Iin1_03-Iin1_03*SIGN(Iin1_03)) 0.5*(Iin1_03+Iin1_03*SIGN(Iin1_03))
150
100
50
0
-50
-100 Input current Lambda parameter
0.009988 0.009992 0.009996 0.01
Time (s)
DAB_design_example2.psimsch
PSIM validation
Points obtained with values from

PSIM simulation
Curves generated with the lambda

value obtained with PSIM
simulation
Lambda curve
are not valid for
Non ZVS
condition Theoretical curve
DAB_design_example2.psimsch
Design process
n: calculated to have M=1 at nominal input voltaje

𝑅·𝑇
𝑉𝑜 = 𝐼𝑜 · 𝑅 = 𝑉𝑔 ·𝐷· 1−𝐷
𝑉𝑜
𝑅·𝑇
𝑀 = 𝑛 = 1 − 𝐷 · 𝐷 · 𝑘; 𝑘=
𝑉𝑔 𝑛2 𝐿𝑙𝑘
Reactive power: max lambda is chosen (input data)
Dmin: cross between ZVS boundary and Mmin
Dmax: cross between lambda curve and Mmax
Power range
Pmin: determined by Rmax, determines kmax
Pmax: determined by Rmin, determines kmin
𝑉𝑔 · 𝑉𝑜 · 𝑇
𝑃𝑜 = 𝐼𝑜 · 𝑉𝑜 = · 𝐷 · 1 − 𝐷 = 𝑃𝑚𝑎𝑥 𝐷 · 1 − 𝐷
Design application example (phase shift)
Specifications: Design:
• Vg=20V±20% • 𝜆𝑡𝑜𝑡𝑎𝑙 = 20%, fsw = 100 KHz
𝑀𝑚𝑎𝑥 𝑎𝑛𝑑 𝑀𝑚𝑖𝑛
• Vo=200V
• n=10 (M=1 for the nominal input voltage)
• P=1 KW
𝑉𝑜 • 𝐷m𝑎𝑥 (reactive power)=0,25
𝑀= 𝑛 𝑇·𝑅
𝑘 = 𝑛2𝐿 for 𝑃m𝑖𝑛 (𝑘 = 0.61)
6.67
𝑀
𝑉𝑔
No ZVS for primary 𝑙𝑘 𝑘𝑚𝑖𝑛 = =
(leading) bridge 𝑇·𝑅
1−𝐷 ·𝐷
𝑘 = 𝑛2𝐿 for 𝑃max (𝑘 = 6.67)
𝑙𝑘 1.25
= 6.67
1 − 0.25 0.25
𝑀𝑚𝑎𝑥 = 1.25
• From 𝑘m𝑖𝑛 , 𝐿𝑙𝑘 is calculated
2002 −5
𝜆𝑡𝑜𝑡𝑎𝑙 = 20% 𝑅 · 𝑇 1000 · 0.5 · 10
𝐿𝑙𝑘 = 2 = = 725𝑛𝐻
𝑛 𝑘 102 6,67
𝑀𝑚𝑖𝑛 = 0.83 • 𝐷min (ZVS primary bridge)=0,1 (not
No ZVS for
secondary relevant)
(lagging) • 𝐷min (ZVS secondary bridge)=0,0833
bridge
𝐷𝑚𝑖𝑛 = 0.1464 𝑀
𝑘𝑚𝑎𝑥 = =
𝐷𝑚𝑖𝑛 = 0.083 (𝑃𝑚𝑎𝑥 )
𝐷𝑚𝑎𝑥 = 0.25
1−𝐷 ·𝐷
(𝑃𝑚𝑖𝑛 )
0.83 6.67
=
1 − 0.083 0.083 0.61
𝐷
DAB_design_example2.psimsch • 𝑃min to ensure ZVS=61% 𝑃m𝑎𝑥
*Based on “Análisis de arquitecturas multipuerto para la alimentación de sistemas electrónicos con

GSEP http://gsep.uc3m.es múltiples flujos de Energía”, A. Rodriguez Alonso, Tesis Doctoral, Universidad de Oviedo 2013

• Vo=200V
• n=10 (M=1 for the nominal input voltage)
• P=1 KW
𝑉𝑜 • 𝐷m𝑎𝑥 (reactive power)=0.4281
𝑇·𝑅 5.1
𝑀= 𝑛 𝑘𝑚𝑎𝑥 = 𝑛2𝐿 for 𝑃m𝑖𝑛 (𝑃𝑚𝑖𝑛 = 10.93 = 0.46 )
𝑀
𝑉𝑔 𝑙𝑘
No ZVS for primary 𝑘𝑚𝑖𝑛 = =
(leading) bridge 1−𝐷 ·𝐷
1.25
= 5.1
1 − 0.4281 0.4281
𝑇·𝑅
𝑘𝑚𝑖𝑛 = 𝑛2𝐿 for 𝑃max (𝑘 = 5.1)
𝑀𝑚𝑖𝑛 = 1.25
𝑙𝑘 • From 𝑘m𝑖𝑛 , 𝐿𝑙𝑘 is calculated
2002 −5
𝑅 · 𝑇 1000 · 0.5 · 10
𝐿𝑙𝑘 = 2 = = 966𝑛𝐻
𝑛 𝑘 102 5.1
𝑀𝑚𝑎𝑥 = 0.83 • 𝐷min (ZVS secondary bridge)=0,0833
No ZVS for
secondary 𝑀
𝜆𝑡𝑜𝑡𝑎𝑙 = 40% 𝑘𝑚𝑎𝑥 = =
(lagging) 1−𝐷 ·𝐷
bridge
𝐷𝑚𝑖𝑛 = 0.2047 0.83 5.1
=
𝐷𝑚𝑖𝑛 = 0.083 (𝑃𝑚𝑎𝑥 ) 1 − 0.083 0.083 0.46
𝐷𝑚𝑎𝑥 = 0.4281
(𝑃𝑚𝑖𝑛 )
• 𝑃min to ensure ZVS=46% 𝑃m𝑎𝑥
𝐷
*Based on “Análisis de arquitecturas multipuerto para la alimentación de sistemas electrónicos con múltiples flujos de Energía”, A.
Rodriguez Alonso, Tesis Doctoral, Universidad de Oviedo 2013
ZVS is lost ZVS is lost
• When ZVS is lost the

efficiency dramatically falls
• Even with ZVS there are
other losses which limit the
efficiency
*Extracted from “Análisis de arquitecturas multipuerto para la alimentación de sistemas electrónicos con
múltiples flujos de Energía”, A. Rodriguez Alonso, Tesis Doctoral, Universidad de Oviedo 2013
Other modulation techniques
Other modulation schemes are used to enlarge

ZVS range, obtain ZCS and reduce rms currents
(specially at light load conditions) Simple Phase Shift φ, D =D =1
1 2
φ
V22
V V11
DD1 =11
t
DD2=1
2
Extended Phase Shift

φ φ, D , D =1
1 2
V11 V22
V
D1
D1
Advantages: t
• More possibilities to have soft switching D2
D2=1
• Lower RMS current for low power

Drawbacks: Triple Phase Shift
• Complexity φ φ, D , D
1 2
V22
V V11
C. Calderon, A. Barrado, A. Rodriguez, A. Lazaro, C. Fernandez and P. Zumel, D1
"Dual active bridge with triple phase shift by obtaining soft switching in all D1
operating range," 2017 IEEE Energy Conversion Congress and Exposition (ECCE), t
Cincinnati, OH, 2017, pp. 1739-1744. DD 2
2
0.8
Triple Phase Shift modulation 0.4
0.8
Vg1
Vg1
Vg2
Vg2
0
0.4
Goal of studying TPS: 0.8
0
0.4
Vg1
Vg3 Vg2
Vg4
- To calculate output quantities (𝑃𝑜 , 𝐼𝑜 ) 0.8

0
0.4
Vg3 Vg4
Vg1 Vg2 Vg1
- To find current value 𝑖𝐿 at switching instants (soft 0.8
0 Vg3 Vg4
0.4
switching) 0.8
0
Vg3
Vg5 β1Vg6
Vg4
0.4 Vg3 Vg4 Vg3
- To find conditions for each operation mode 0.8
0 Vg5 Vg6
(a)0.4
0.8 Vg5 Vg6
0
0.4
β2 Vg5 Vg6
0.8 Vg5
Vg7 Vg6
Vg8
0
0.4
0.8
0
0.4
Vg7 βVg8
3 Vg7 Vg8 Vg7
0.8
0
0 Vg7 Vg8
0.4 0.00066 0.000665 0.00067 0.000675
0.8
0 V11(t)
Vg7
V11 VVg8
22(t)
V22' Time (s)
0.4
0.8
40
𝝋 0.00066 0.000665 0.00067 0.000675
0 Time (s)
0.4
0.00066 0.000665 0.00067 0.000675
200 𝐃𝟏 Time (s) 𝐃𝟐
0.00066 0.000665 0.00067 0.000675
(b) 00 Time (s)
-20 Tsw
𝑇𝑠𝑤 𝑇𝑠𝑤 1 − 𝐷1
𝛽1 = · 𝐷1 𝑡1𝐿𝐻 = -40
2 2 2
iL(t)
I(L)
𝑇𝑠𝑤 𝐷1 − 𝐷2 𝑇𝑠𝑤 1 + 𝐷1
𝛽2 = · +𝜑 𝑡1𝐻𝐿 = 6
2 2 2 2
4
𝑇𝑠𝑤 𝐷1 + 𝐷2
𝛽3 = · +𝜑 𝑇𝑠𝑤 1 − 𝐷1 (c) 20
2 2 𝑡2𝐿𝐻 = 𝜑+
2 2 0
𝑇𝑠𝑤 1 + 𝐷1 -2 t2LH t2HL

𝑡2𝐻𝐿 = 𝜑+ -4 t1LH t1HL
2 2
GSEP http://gsep.uc3m.es 0.00066 0.000665
Time (s)
0.00067 0.000675

OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
DAB series resonant
Load: it can
Coupling inductor is replaced by a series resonant tank be R||C
𝐼𝑔 𝐼𝑜
Q1 Q3 1 n Q7 Q5
Lr Cr
+ +
A + 𝑖𝐿𝑟 𝑣′𝐷𝐶 𝑣𝐷𝐶 D
B 𝑣𝐴𝐵 − − C
Vg Vout
−
Q2 Q4 𝑃𝑜 Q8 Q6
𝑇𝑠
𝑣𝐴 • Three control angles
• Same philosophy as TPS
𝜑𝐴𝐵
𝑣𝐵 • Fundamental harmonic
𝜑𝐴𝐷 approximation: only harmonic at
𝑣𝐷 the switching frequency of bridge
𝜑𝐷𝐶 voltages (𝑣𝐴 , 𝑣𝐵 , 𝑣𝑐 , 𝑣𝑑 ) are
𝑣𝐶
considered
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 7, JULY 2012 Minimum Current Operation of Bidirectional Dual-Bridge Series
GSEP http://gsep.uc3m.es Resonant DC/DC Converters Luca Corradini, Daniel Seltzer, Douglas Bloomquist, Regan Zane, Dragan Maksimovic´,, and Boris Jacobson

DAB series resonant
2 2
1
𝒵𝑡𝑎𝑛𝑘 = 𝑗𝜔𝐿 + 𝑗𝜔𝐶 = 𝑗𝜔𝐿- 𝜔𝐶
𝑗 1 𝜔𝑜 1 𝜔𝑜 1
𝑍𝑡𝑎𝑛𝑘 = 𝒵𝑡𝑎𝑛𝑘 = 𝜔𝐿 − = 𝜔𝐿 − 𝜔𝑜 =
𝜔𝐶 𝜔𝑜 𝜔𝐶 𝜔𝑜 𝐿𝐶
2
2
𝐿 𝜔 𝐿𝐶 𝜔𝑜 𝐿 𝜔 𝐿 𝜔𝑜 𝐿 𝜔 𝜔𝑜 𝐿 1 𝜔𝑜
𝑍𝑡𝑎𝑛𝑘 = − = − = − 𝑍𝑡𝑎𝑛𝑘 ቚ = −𝑟 𝑟=
𝐿𝐶 𝜔𝑜 𝐶 𝜔 𝐶 𝜔𝑜 𝐶 𝜔 𝐶 𝜔𝑜 𝜔 𝜔=𝜔𝑠 𝐶 𝑟 𝜔𝑠
𝐿 1 − 𝑟2 𝑍0
𝑍𝑡𝑎𝑛𝑘 ቚ = =
𝜔=𝜔𝑠 𝐶 𝑟 𝐻0 𝑟
𝑇𝑠
𝑣𝐴
𝜑𝐴𝐵 𝐿 1 − 𝑟2
𝑣𝐵 𝑍0 = 𝐻0 𝑟 =
𝐶 𝑟
𝜑𝐴𝐷
𝑣𝐷
𝜑𝐷𝐶
𝑣𝐶

DAB series resonant
4 𝜋 − 𝜑𝐴𝐵 𝜋 𝜑𝐴𝐵 4 𝑉𝑜 𝜋 − 𝜑𝐷𝐶 𝜋 𝜑𝐷𝐶

𝑣𝐴𝐵1 (𝑡) = 𝑉𝑔 cos 𝑠𝑖𝑛 𝜔𝑡 + − 𝑣′𝐷𝐶1(𝑡) = cos 𝑠𝑖𝑛 𝜔𝑡 − 𝜑𝐴𝐷 + −
𝜋 2 2 2 𝜋 𝑛 2 2 2
4 𝜑𝐴𝐵 4 𝑉𝑜 𝜑𝐷𝐶
𝑉𝐴𝐵1 = 𝑉𝑔 sin 𝜋 𝜑𝐴𝐵
𝑉′𝐷𝐶1 = sin 𝜋 𝜑𝐷𝐶
𝜋 2 <2 − 2 𝜋 𝑛 2 <−𝜑𝐴𝐷 + 2 − 2
𝑉𝐴𝐵1
𝐼𝑡𝑎𝑛𝑘1 = 𝐼𝑡𝑎𝑛𝑘1 𝑉𝐴𝐵1 + 𝐼𝑡𝑎𝑛𝑘1 𝑉′𝐷𝐶1 𝐼𝑡𝑎𝑛𝑘1 𝑉𝐴𝐵1 = 𝑍
𝑡𝑎𝑛𝑘 <−𝜋/2
1 𝜋 𝜑𝐷𝐶 𝜋 𝜑𝐴𝐵 𝜋 𝜋 𝜑𝐷𝐶 𝜑𝐴𝐵

𝑃𝑜 = 𝑉′ ·𝐼 cos(𝛼) 𝛼 = −𝜑𝐴𝐷 + − − − + = −𝜑𝐴𝐷 + − +
2 𝐷𝐶1 𝑡𝑎𝑛𝑘1 𝑉𝐴𝐵1 2 2 2 2 2 2 2 2
𝑇𝑠
𝑣𝐴
𝜑𝐴𝐵
𝑣𝐵
𝜑𝐴𝐷
𝑣𝐷
𝜑𝐷𝐶
𝑣𝐶

DAB series resonant
4 𝜋 − 𝜑𝐴𝐵 𝜋 𝜑𝐴𝐵 4 𝑉𝑜 𝜋 − 𝜑𝐷𝐶 𝜋 𝜑𝐷𝐶

𝑣𝐴𝐵1 (𝑡) = 𝑉𝑔 cos 𝑠𝑖𝑛 𝜔𝑡 + − 𝑣′𝐷𝐶1(𝑡) = cos 𝑠𝑖𝑛 𝜔𝑡 − 𝜑𝐴𝐷 + −
𝜋 2 2 2 𝜋 𝑛 2 2 2
4 𝜑𝐴𝐵 4 𝑉𝑜 𝜑𝐷𝐶
𝑉𝐴𝐵1 = 𝑉𝑔 sin 𝜋 𝜑𝐴𝐵
𝑉′𝐷𝐶1 = sin 𝜋 𝜑𝐷𝐶
𝜋 2 <2 − 2 𝜋 𝑛 2 <−𝜑𝐴𝐷 + 2 − 2
𝑉𝐴𝐵1
𝐼𝑡𝑎𝑛𝑘1 = 𝐼𝑡𝑎𝑛𝑘1 𝑉𝐴𝐵1 + 𝐼𝑡𝑎𝑛𝑘1 𝑉′𝐷𝐶1 𝐼𝑡𝑎𝑛𝑘1 𝑉𝐴𝐵1 = 𝑍
𝑡𝑎𝑛𝑘 <−𝜋/2
1 𝜋 𝜑𝐷𝐶 𝜋 𝜑𝐴𝐵 𝜋 𝜋 𝜑𝐷𝐶 𝜑𝐴𝐵

𝑃𝑜 = 𝑉′ ·𝐼 cos(𝛼) 𝛼 = −𝜑𝐴𝐷 + − − − + = −𝜑𝐴𝐷 + − +
2 𝐷𝐶1 𝑡𝑎𝑛𝑘1 𝑉𝐴𝐵1 2 2 2 2 2 2 2 2
1 4 𝑉𝑜 𝜑𝐷𝐶 4 𝜑𝐴𝐵 𝐻0 𝑟 𝜑𝐷𝐶 𝜑𝐴𝐵

𝑃𝑜 = sin · 𝑉𝑔 sin · · sin 𝜑𝐴𝐷 + −
2𝜋 𝑛 2 𝜋 2 𝑍0 2 2
8 𝑉𝑜 𝐻0 𝑟 𝜑𝐷𝐶 𝜑𝐴𝐵 𝜑𝐷𝐶 𝜑𝐴𝐵

𝑃𝑜 = 𝑉𝑔 · sin · sin · sin 𝜑𝐴𝐷 + −
𝜋2 𝑛 𝑍0 2 2 2 2

DAB series resonant
Load: it can
𝐼𝑔 𝐼𝑜
Q1 Q3 1 n Q7 Q5
Lr Cr
+ +
A + 𝑖 𝑣′𝐷𝐶 𝑣𝐷𝐶 D
B 𝑣𝐴𝐵 − C
Vg − Vout
−
Power transferred between ports

Topology dependant
𝜑𝐴𝐵 𝜑𝐷𝐶 𝜑𝐷𝐶 − 𝜑𝐴𝐵

𝑃𝑜 = 𝑃𝑜,𝑚𝑎𝑥 sin sin sin 𝜑𝐴𝐷 +
2 2 2
8 𝑉𝑜 𝑉𝑔 𝜔0 1 𝐿𝑟 𝑟
𝑃𝑜,𝑚𝑎𝑥 = 𝐻 (𝑟) 𝑟≜ < 1, 𝜔0 ≜ , 𝑍0 ≜ , 𝐻 𝑟 ≜
𝑛 · 𝜋 2 𝑍0 0 𝜔𝑠 𝐿𝑟 𝐶𝑟 𝐶𝑟 1−𝑟 2
Tank dependant

DAB series resonant
Load: it can
𝐼𝑔 𝐼𝑜
Q1 Q3 1 n Q7 Q5
Lr Cr
+ +
Vg − Vout
−
Input and output average currents

𝑃𝑜 8 𝑉𝑔 𝜑𝐴𝐵 𝜑𝐷𝐶 𝜑𝐷𝐶 − 𝜑𝐴𝐵
𝐼𝑜 = = 𝐻 (𝑟) sin sin sin 𝜑 +
𝑉𝑜 𝑛 · 𝜋 2 𝑍0 0 2 2 𝐴𝐷
2
𝑃𝑜 8 𝑉𝑜 𝜑𝐴𝐵 𝜑𝐷𝐶 𝜑𝐷𝐶 − 𝜑𝐴𝐵
𝐼𝑔 = = 𝐻 (𝑟) sin sin sin 𝜑 +
𝑉𝑔 𝑛 · 𝜋 2 𝑍0 0 2 2 𝐴𝐷
2
Current source behavior (in steady state)!!!

DASRC with single angle control (phase shift)
Load: it can
𝐼𝑔 𝐼𝑜
Q1 Q3 1 n Q7 Q5
Lr Cr
+ +
Vg − Vout
−
Input and output average currents
𝑃𝑜 8 𝑉𝑔 𝑉𝑜 /𝑛 𝐼 8 𝑅 𝐻0 (𝑟)
𝐼𝑜 = = 𝐻 (𝑟) sin 𝜑𝐴𝐷 𝑀= = 𝑅 · 𝑛𝑜 = 𝜋2 𝑛2 sin 𝜑𝐴𝐷 = 𝑘 · sin 𝜑𝐴𝐷
𝑉𝑜 𝑛·𝜋2 𝑍0 0 𝑉𝑔 𝑍0
𝑃𝑜 8 𝑉𝑜
𝐼𝑔 = = 𝐻 (𝑟) sin 𝜑𝐴𝐷 8 𝐻0 (𝑟) 𝑅
𝑉𝑔 𝑛 · 𝜋 2 𝑍0 0 𝑘=
𝜋 2 𝑍0 𝑛2

M-D characteristic
k=6
𝑀 = 1.4 k=1.5
𝑀 = 0.6
𝜑𝐴𝐷 (𝑟𝑎𝑑)
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
ZVS limits
Graphical representation of possible combinations of d and M to ensure ZVS
ZVS can be lost for small d values, depending on the M value
No ZVS for 𝑀 = 1/𝑐𝑜𝑠 𝜑

primary
(leading)
bridge Always ZVS for secondary bridge
ZVS in primary bridge lost when 𝜑 <0.7679
𝑀 = 1.4
For each M value, 𝜑 depends

𝑉𝑜
on the load (R or Io)
𝑀= 𝑛 𝑀 = 1 Always ZVS for both bridges
𝑉𝑔
Always ZVS for primary bridge
ZVS in primary bridge lost when 𝜑<0.925
𝑀 = 0.6
No ZVS for
secondary 𝑀 = 𝑐𝑜𝑠 𝜑
(lagging) bridge
𝜑(𝑟𝑎𝑑)
Reactive power
Total charge
Negative charge 𝜋
𝑄 = න 𝐴 · sin 𝜔𝑡 − 𝛼 𝑑𝜔𝑡
𝛼
0
𝑄− = − න 𝐴 · sin 𝜔𝑡 − 𝛼 𝑑𝜔𝑡
0
𝜆 is equivalent to reactive current

𝑖𝑖 percentages
𝑄− 1 − cos(𝛼)
𝜆 = =
𝑄 2 · cos(𝛼)
𝑣 𝜔𝑡 = 𝐴 · sin(𝜔𝑡 − 𝛼)
𝛼
Input current is delayed 𝛽 with the input voltaje, while output current is delayed 𝜃 with the output
voltage
1−cos(𝛽) 1−cos(𝜃)
𝜆𝑡𝑜𝑡𝑎𝑙 = 𝜆𝑜 + 𝜆𝑖 = + 2cos(𝜃)
2cos(𝛽)
where
sin 𝜑 𝑀
8· 𝑀 + 4 · sin 𝜃
𝛽 = atan 𝜃 = atan cot 𝜑 −
8 · cos 2 𝜃 sin(𝜑)
No ZVS for 𝜆𝑡𝑜𝑡𝑎𝑙 = 50%

primary
(leading)
bridge 𝜆𝑡𝑜𝑡𝑎𝑙 = 40%
𝑉𝑜 𝜆𝑡𝑜𝑡𝑎𝑙 = 30%
𝑀= 𝑛 𝜆𝑡𝑜𝑡𝑎𝑙 = 20%
𝑉𝑔
No ZVS for
secondary
(lagging) bridge
𝜑(𝑟𝑎𝑑)
No ZVS for
primary
𝜆𝑡𝑜𝑡𝑎𝑙 > 30%
(leading)
(too much reactive power)
bridge
𝑉𝑜
𝑀= 𝑛 𝜆𝑡𝑜𝑡𝑎𝑙 = 30%
𝑉𝑔
No ZVS for
secondary
(lagging) bridge
𝜑(𝑟𝑎𝑑)
PSIM Validation

PSIM simulation
𝑉𝑜
𝑀= 𝑛
𝑉𝑔

simulation
Theoretical curve
𝜑(𝑟𝑎𝑑)
GSEP http://gsep.uc3m.es DABSRC_design_example2.psimsch

PSIM Validation

PSIM simulation
𝑉𝑜
𝑀= 𝑛
𝑉𝑔

simulation
A CORRECTION factor is used
(14% maximum deviation)
Theoretical curve
𝜑(𝑟𝑎𝑑)
GSEP http://gsep.uc3m.es DABSRC_design_example2.psimsch

Error quantification
First harmonic approximation: how much error?
Output voltage error in the actual simulation

Output voltage considering only the first
Actual waveform harmonic of the inductor current
Inductor current
First Harmonic
Output current (before output capacitor)
DABSRC_design_example2.psimsch
Design process
n: calculated to have M=1 at nominal input voltaje (not always)

8 𝑅 ∙ 𝑉𝑔
𝑉𝑜 = 𝐼𝑜 · 𝑅 = 𝐻0 𝑟 sin 𝜑
𝑛 · 𝜋 2 𝑍0
𝑉𝑜
8 𝑅
𝑀 = 𝑛 = sin 𝜑 · 𝑘; 𝑘= ∙ 𝐻0 𝑟
𝑉𝑔 𝜋2 ∙ 𝑛 2 𝑍0
Reactive power: max lambda is chosen (input data)
𝜑𝒎𝒊𝒏 : cross between ZVS boundary and Mmin
𝜑𝒎𝒂𝒙 : cross between lambda curve and Mmax
Power range
Pmin: determined by Rmax, determines kmax
Pmax: determined by Rmin, determines kmin
Desing exmaple
• Vo=200V
• L=1µH
• P=1 KW
𝑉𝑜 • n=10, r=0.7
𝑀= 𝑛 • 𝜑m𝑎𝑥 (reactive power)=1.274
𝑉𝑔 No ZVS for
primary 𝑀
(leading) 𝜆𝑡𝑜𝑡𝑎𝑙 > 30% 𝑘𝑚𝑖𝑛 = =
bridge (too much reactive power) sin(𝜑)
1.25
= 1.3
𝑀𝑀==1.25
1.25 sin 1.274
𝜆𝑡𝑜𝑡𝑎𝑙 = 20% • 𝜑min (ZVS sec bridge)=0.5934

0.83
𝑘𝑚𝑎𝑥 =
𝑀 = 0.83
𝑀 = 0.83 sin 0.5934
• 𝑃min to ensure ZVS
𝑘𝑚𝑖𝑛 1.3071
= = 0.8806
No ZVS for 𝑘𝑚𝑎𝑥 1.4843
secondary • Resonant capacitor value
(lagging) bridge
1
0.5934 1.274 𝐶=
2𝜋𝑓𝑠𝑤 2 𝐿
• Vo=200V
• L=1µH
• P=1 KW
𝑉𝑜 • n is changed (different M), r=0.7
𝑀= 𝑛 • 𝜑m𝑎𝑥 (reactive power)= 1.117
𝑉𝑔 No ZVS for
primary 𝑀
(leading) 𝜆𝑡𝑜𝑡𝑎𝑙 > 30% 𝑘𝑚𝑖𝑛 = =
(too much reactive power) sin(𝜑)
bridge
1.396
= 1.55
𝑀== 1.396
1.25 sin 1.117
𝑀
𝜆𝑡𝑜𝑡𝑎𝑙 = 20% • 𝜑min (ZVS sec bridge)=0.5934

0.8944
𝑀 = 0.8944 𝑘𝑚𝑎𝑥 = = 2.0146
𝑀 = 0.83 sin 0.46
• 𝑃min to ensure ZVS
𝑘𝑚𝑖𝑛 1.55
No ZVS for = = 0.77
secondary 𝑘𝑚𝑎𝑥 2.0146
(lagging) bridge
0.46 1.117
• Vg=20V±20% • 𝜆𝑡𝑜𝑡𝑎𝑙 = 30%,
• Vo=200V
• fsw = 77,7 KHz (high power)
• P=1 KW
𝑉𝑜 • fsw = 100 KHz (low power)
𝑀= 𝑛 • n=10, r=0.9
𝑉𝑔 No ZVS for
primary 𝜆𝑡𝑜𝑡𝑎𝑙 > 30% • 𝜑m𝑎𝑥 (reactive power)= 1.117
(leading) (too much reactive power)
bridge 𝑀
𝑘𝑚𝑖𝑛 = =
sin(𝜑)
𝑀𝑀==1.396
1.25 1.396
= 1.55
sin 1.117
• 𝜑min (ZVS sec bridge)=0.5934
𝑀 = 0.8944
𝑀 = 0.83 0.8944
𝑘𝑚𝑎𝑥 = = 2.0146
sin 0.46
No ZVS for
secondary
𝐻01 𝑟 𝑅1 = 𝐻0 2 𝑟 𝑅2
(lagging) bridge 0.9
𝐻01 𝑟 𝑅1 1 − 0. 92 4,73
𝑅2 = = 𝑅1 = 𝑅 = 3,45𝑅1
0.46 𝐻0 2 (𝑟) 0.7 1,37 1
1.117 1 − 0. 72
Changing switching frequency for low power
8 𝐻0 (𝑟) 𝑅 range, wider ZVS range is achieved
𝑘=
𝜋 2 𝑍0 𝑛2
DAB series resonant: minimum current trajectory, MCT
𝑃𝑜
Normalized power flow 𝑃 with 𝜑𝐷𝐶 =180º (secondary bridge with square
𝑜,𝑚𝑎𝑥
wave). Contour plot. Voltage source load (totally symmetric)
Zero power
𝜑𝐴𝐵 (𝑑𝑒𝑔)
boundaries
(change
direction of
power flow)
Maximum
power transfer
points 𝜑𝐴𝐵 = 180
Phase shift
𝜑𝐴𝐷 (𝑑𝑒𝑔)
operation
𝑃𝑜 𝜑𝐴𝐵 𝜑𝐷𝐶 𝜑𝐷𝐶 − 𝜑𝐴𝐵
= sin sin sin 𝜑𝐴𝐷 +
𝑃𝑜,𝑚𝑎𝑥 2 2 2

MCT(I)
𝐼𝑟𝑚𝑠,𝑚𝑎𝑥 𝜑𝐴𝐵 𝜑𝐷𝐶 𝜑𝐴𝐵 𝜑𝐷𝐶 𝜑𝐷𝐶 − 𝜑𝐴𝐵

𝐼 = sin2 + 𝑀 2 sin2 − 2𝑀 sin sin 𝑐𝑜𝑠 𝜑𝐴𝐷 +
1+𝑀 2 2 2 2 2
2 2 𝑉𝑔 𝑉𝑜
𝐼𝑟𝑚𝑠,𝑚𝑎𝑥 = 𝐻 𝑟 1+𝑀 , 𝑀=
𝜋 𝑍0 0 𝑛𝑉𝑔
𝑴=𝟏 𝑴 = 𝟎, 𝟓
𝑰
contours
𝑰 𝒓𝒎𝒔,𝒎𝒂𝒙
𝜑𝐴𝐵
𝜑𝐴𝐵
𝝋𝑫𝑪 =180º
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 7,

𝜑𝐴𝐷 𝜑𝐴𝐷
JULY 2012 Minimum Current Operation of Bidirectional Dual-
Bridge Series Resonant DC/DC Converters Luca Corradini,
Daniel Seltzer, Douglas Bloomquist, Regan Zane, Dragan
Maksimovic´,, and Boris Jacobson
Interesting areas (low rms current)
MCT(II)
𝑃𝑜 𝐼
contours with 𝜑𝐷𝐶 =180º contours with 𝜑𝐷𝐶 =180º
𝑃𝑜,𝑚𝑎𝑥 𝐼 𝑟𝑚𝑠,𝑚𝑎𝑥
Minimum RMS
current trajectory
𝑴 = 𝟎, 𝟓 𝑴 = 𝟎, 𝟓
𝜑𝐴𝐵
𝜑𝐴𝐵
Mathematical solution
to be discarded
Resonant DC/DC Converters Luca Corradini, Daniel Seltzer, Douglas Bloomquist, Regan Zane, Dragan Maksimovic´,, and Boris Jacobson
Minimum RMS (II)
𝑃𝑜 𝐼
contours with 𝜑𝐴𝐵 =180º contours with 𝜑𝐴𝐵 =180º
𝑃𝑜,𝑚𝑎𝑥 𝐼 𝑟𝑚𝑠,𝑚𝑎𝑥
Minimum RMS
current trajectory
𝑴 = 𝟏, 𝟓 𝑴 = 𝟏, 𝟓
𝜑𝐷𝐶
𝜑𝐷𝐶
Mathematical solution
to be discarded
Soft switching conditions along the minimum current trajectory
Soft switching conditions can be lost for low power following the
minimum current trajectory
▪ Trade off between conduction losses and switching losses
▪ EMI can be a concern if ZVS is lost
All the devices turn on at zero voltage if
𝑃𝑜 One angle modulation

> 1 − 𝑀2 ZVS
𝑃𝑜,𝑚𝑎𝑥 𝑃𝑜 Hard
ZVS switching
𝑃𝑜,𝑚𝑎𝑥
Hard switching in input bridge if
Minimum current
Hard
trajectory
switching
𝑃𝑜
< 𝑀(1 − 𝑀)
𝑃𝑜,𝑚𝑎𝑥
𝑀
DAB vs DABSRC
Common features:
• symmetrical structure
• soft-switching
• step-up/stepdown
DASRC additional features:

• the resonant capacitor can filter the dc current and limit fault currents under
abnormal operating conditions
• due to the resonant property, DBSRCs provide more flexibility for the
converter design and power control
Summary
DAB can be configured with different coupling elements (reactive)

▪ L, leakage inductance of the transformer is used
▪ Resonant tank
Current source behavior
▪ Easy paralleling
Soft switching is a concern
▪ Wide ZVS or ZCS operation range has to be ensured
Different modulations are possible
▪ Phase shift or single angle operation
▪ TPS or the equivalent in the resonant
▪ Many operation modes appear
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
Bidirectional converter comparison
K. L. J⊘rgensen, M. C. Mira, Z. Zhang and M. A. E. Andersen, "Review of high efficiency bidirectional dc-dc topologies with high
voltage gain," 2017 52nd International Universities Power Engineering Conference (UPEC), Heraklion, 2017, pp. 1-6.
Eff
Eff Step step Conf/Journ
Ref Topology Power down up Vlow Vhigh Gain Fsw Nb SW Year al
[4] Isolated Dual Active Bridge 256 88 88 12.8 400 31.25 200 4 2015 IECON
Isolated Dual Active Bridge
[16] 10000 93.9 93.9 50 400 8 100 20 2016
Converter with Tap Changer Conf
[19] Isolated Full Bridge Boost 6000 97.8 96.5 30 800 26.67 40 8 2013 Conf
Isolated Resonant Two Inductor
[23] 2000 96 96 10 400 40 20 4 2006
Boost Converter IET Journal
[24] Full Bridge with CLLC Tank 500 96 96 48 400 8.33 - 8 2010 TIE
[25] Half Bridge and Push-Pull 100 90 86.6 55 400 7.27 100 4 2000 TPEL
Resonant Half Bridge Buck with
[30] 200 95.6 96.3 24 200 8.33 50 4 2015
Current Doubler TIE
Cascaded Buck/Boost and Series
[33] 5000 96.5 - 200 700 3.5 - 10 2014
Resonant Converter ECCE
Two-Stage Isolated dc-dc
[35] Converter with Current Ripple 2000 98 98 18 300 16.67 90 6 2012
Reduction Technique TIE
Other DAB alternatives
Bidirectional LLC and DAB
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
DAB-PS Average model
Starting point: average model of DAB with PS modulation

▪ Linearization and perturbation
▪ Input quantities (independent variable): d and Vg
1:n
𝑇·𝐷· 1−𝐷
𝐼𝑜 = 𝑉𝑔 · 𝑛·𝐿𝑘
Vg Ii n·Io C R
𝑇·𝐷· 1−𝐷
𝐼𝑖 = 𝑉𝑜 ·
𝑛 · 𝐿𝑘
Ideal transformer
Input current Output current

𝑖𝑖𝑛 = 𝑖𝐿𝑘 · 𝑠𝑖𝑔𝑛(𝑣𝐷𝐴𝐵1) 𝑖𝑜𝑢𝑡 = 𝑖𝐿𝑘 · 𝑠𝑖𝑔𝑛(𝑣𝐷𝐴𝐵2)
𝐼1 𝑛 · 𝑖𝑜
𝑖𝐿𝑘 𝑖𝑖
𝐼2
−𝐼2 𝑑𝑇
𝑑𝑇
−𝐼1
𝑡1 𝑡2 𝑇
𝑇
𝑇
DAB-PS small signal model
𝑖𝑖𝑎 𝑖𝑖𝑜
1:n
Average
Vg 𝑖I𝑖𝑎i n·I𝑖o𝑖𝑜 C R model
𝑇·𝑑· 1−𝑑 𝑇·𝑑· 1−𝑑

𝑖𝑖𝑎 = 𝑉𝑜 · 𝑖𝑜𝑎 = 𝑉𝑔 · 𝑛·𝐿𝑘
𝑛 · 𝐿𝑘
Linearization
𝜕𝑖𝑖𝑎 𝜕𝑖𝑖𝑎 𝜕𝑖𝑜𝑎 𝜕𝑖𝑜𝑎 and
𝑖Ƹ𝑖𝑎 = 𝑑መ + 𝑣ො𝑜 = 𝑔𝑖𝑑 𝑑መ + 𝑔𝑖𝑣𝑜 𝑣ො𝑜 𝑖Ƹ𝑜𝑎 = 𝑑መ + 𝑣ො𝑔 = 𝑔𝑜𝑑 𝑑መ + 𝑔𝑜𝑣𝑖 𝑣ො𝑔 perturbation
𝜕𝑑 𝜕𝑣𝑜 𝜕𝑑 𝜕𝑣𝑔
𝑣ො𝑔
+ Small signal
C R 𝑣ො 𝑜
𝑔𝑖𝑑 𝑑መ 𝑔𝑖𝑣𝑜 𝑣ො𝑜 𝑔𝑜𝑑 𝑑መ 𝑔𝑜𝑣𝑖 𝑣ො𝑔 - model
Gains
𝑉𝑜2 1 − 2𝐷 𝑉𝑜 𝑉𝑜 𝑉𝑜 1 − 2𝐷 𝑉𝑜 depending on
𝑔𝑖𝑑 = = 𝑔𝑜𝑑 𝑔𝑖𝑣𝑜 = 𝑔𝑜𝑑 = 𝑔𝑜𝑣𝑖 =
𝑉𝑔 1 − 𝐷 𝐷𝑅 𝑉𝑔 𝑉𝑔 𝑅 1 − 𝐷 𝐷𝑅 𝑉𝑔 𝑅 the operating
point
DAB-PS Average model
DAB PS average small signal lossless model

▪ First order: the responsible for the dynamics is the output filter
▪ Depends on the operation point
▪ Similar to DCM behavior
▪ Control to output and line to control transfer functions are proportional
𝑅
𝑣ො𝑜 = (𝑔𝑜𝑑 · 𝑑መ + 𝑔𝑜𝑣𝑖 𝑣ො𝑔 )
𝑅𝐶𝑠 + 1
+
𝑣ො𝑔 C R 𝑣ො 𝑜
𝑔𝑖𝑑 𝑑መ 𝑔𝑖𝑣𝑜 𝑣ො𝑜 𝑔𝑜𝑑 𝑑መ 𝑔𝑜𝑣𝑖 𝑣ො𝑔 -
𝑉𝑜2 1 − 2𝐷 𝑉𝑜 𝑉𝑜 𝑉𝑜 1 − 2𝐷 𝑉𝑜
𝑔𝑖𝑑 = = 𝑔𝑜𝑑 𝑔𝑖𝑣𝑜 = 𝑔𝑜𝑑 = 𝑔𝑜𝑣𝑖 =
𝑉𝑔 1 − 𝐷 𝐷𝑅 𝑉𝑔 𝑉𝑔 𝑅 1 − 𝐷 𝐷𝑅 𝑉𝑔 𝑅
DAB Average model
Bode plot
𝑅
𝑣ො𝑜 = 𝑔𝑜𝑑 · 𝑑መ
𝑅𝐶𝑠 + 1
Converter parameters
Filtro C
C1=470uF;
Parametros del convertidor
Vo=254;
D=0.25;
R=134;
Vi=20
n=8
Lk=1.23uH
f = 100k
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
DAB model with input and output filters
+
𝑔𝑖𝑑 𝑑መ 𝑔𝑖𝑣𝑜 𝑣ො𝑜 𝑔𝑜𝑑 𝑑መ 𝑔𝑜𝑣𝑖 𝑣ො𝑔 -
Input source Model of the switching cell +

Output filter + load
coupling inductor & transformer
Input Output +
C R 𝑣ො 𝑜
filter 𝑔𝑜𝑑 𝑑መ
filter
𝑣ො𝑔 𝑔𝑖𝑑 𝑑መ 𝑔𝑖𝑣𝑖 𝑣ො𝑔 𝑔𝑜𝑣𝑖 𝑣ො𝑔 -
C
DAB Average model with pi output filter
Pi output filter can be necessary for EMI requirements
Filtro PI Parametros del convertidor

C1=470e-6; Vo=254;
C2=470e-6; D=0.25;
L=10e-6; R=134;
Vi=20
n=8
Lk=1.23uH
DAB Average model with output pi filter
𝑖Ƹ𝑜𝑎
+ 𝐿𝑜 L 𝑅𝐿𝑜 +
𝑣ො𝑔 C1 𝑣ො 𝑜1 C2 R 𝑣ො 𝑜
𝑔𝑖𝑑 𝑑መ 𝑔𝑖𝑣𝑜 𝑣ො𝑜 𝑔𝑜𝑑 𝑑መ 𝑔𝑜𝑣𝑖 𝑣ො𝑔 - -
ESR of inductor L 𝑍𝑒𝑞

𝑍2 = 𝐿𝑜 · 𝑠 + 𝑅𝐿𝑜 𝑍2
𝑅 · 1ൗ𝑠𝐶 + +
𝑖Ƹ𝑜𝑎
𝑍1 = 1ൗ𝑠𝐶1 𝑍3 = 2
𝑅 + 1ൗ𝑠𝐶 𝑍1 𝑣ෝ 𝑜1 𝑍3 𝑣ෝ 𝑜
2
- -
𝑖෡ 𝑜𝑎 = 𝑔𝑜𝑑 · 𝑑መ + 𝑔𝑜𝑣𝑖 𝑣ො𝑔
𝑍1 · 𝑍2 + 𝑍3
𝑍𝑒𝑞 = 𝑍1 ∥ 𝑍2 + 𝑍3 =
𝑍1 + 𝑍2 + 𝑍3
𝑣ො𝑜1 = 𝑖෡ 𝑜𝑎 𝑍𝑒𝑞 = 𝑍𝑒𝑞 𝑔𝑜𝑑 · 𝑑መ + 𝑔𝑜𝑣𝑖 𝑣ො𝑔
𝑍3 𝑍3 𝑍3 ·𝑍1
𝑣ො𝑜 = 𝑣ො𝑜1 = 𝑍𝑒𝑞 𝑔𝑜𝑑 · 𝑑መ + 𝑔𝑜𝑣𝑖 𝑣ො𝑔 = 𝑔𝑜𝑑 · 𝑑መ + 𝑔𝑜𝑣𝑖 𝑣ො𝑔
𝑍2 +𝑍3 𝑍2 +𝑍3 𝑍1 +𝑍2 +𝑍3
DAB Average model with output pi filter
▪ Additional poles due to pi filter

▪ Control to output and line to output transfer functions are proportional
𝑍3 · 𝑍1
𝑣ො𝑜 = 𝑔𝑜𝑑 · 𝑑መ + 𝑔𝑜𝑣𝑖 𝑣ො𝑔
𝑍1 + 𝑍2 + 𝑍3
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
DAB Average model with input LC filter
%filtro de salida %parametros

C1=470e-6; Vo=254; %filtro de entrada
C2=470e-6; D=0.25; Cin=47e-6;
L=10e-6; R=134; Lin=10e-6;
Rlpi=0.1; Vi=20; Rin=0.1;
n=8
Lk=1.23uH
Input filter design considerations
From “Fundamental of Power Electronics” Erickson, Maksimovic

• “The input filter elements affect all transfer functions of the converter, including the
control-to-output transfer function Gvg(s), the line-to-output transfer function Gvg(s),
and the converter output impedance Zout(s). Moreover, the influence of the input filter
on these transfer functions can be quite severe.”
• “If the crossover frequency of the regulator feedback loop is near to or greater than the
resonant frequency of the input filter, then the loop phase margin will become negative
and instability will result.”
DAB with input LC filter: the extra element theorem
Extra Element Theorem to calculate the modified control to output

function with the input filter
1 𝑍𝑜 (𝑠) Output impedance of input filter
2 𝐺𝑣𝑑 𝑠 ቚ Original transfer function, before addition

𝑍𝑜 𝑠 =0 of input filter
3 𝑍𝐷 (𝑠) Converter input impedance, with the
control variable set to zero
4 𝑍𝑁 (𝑠) Converter input impedance, with the
output nulled to zero
𝑍𝑜 (𝑠) 𝑍𝐷 (𝑠)=𝑍𝑖 𝑠 ȁ𝑑
1+ 𝑠 =0
EET 𝑍𝑁 (𝑠)
𝐺𝑣𝑑 𝑠 = 𝐺𝑣𝑑 𝑠 ቚ
𝑍𝑜 𝑠 =0 𝑍 (𝑠) 𝑍𝑁 (𝑠)= 𝑍𝑖 𝑠 ቚ
1+ 𝑜 null
𝑍𝐷 (𝑠) 𝑣 𝑠 0
1 𝑍𝑜 (𝑠) Output impedance of input filter
2 𝐺𝑣𝑑 𝑠 ቚ Original transfer function, before addition

+ L
+
𝑔𝑖𝑑 𝑑መ 𝑔𝑖𝑣𝑜 𝑣ො𝑜1 𝑔𝑜𝑑 𝑑መ 𝑔𝑜𝑣𝑖 𝑣ො𝑔 - -
𝑍𝑜 𝑠 = 𝑍𝑓 = 𝑍𝐿𝑓 ȁȁ𝑍𝐶𝑓
𝑍3
𝐺𝑣𝑑 𝑠 ቚ = 𝑔𝑜𝑑 · 𝑍𝑒𝑞 . = 𝑔𝑜𝑑 · 𝑍
𝑍𝑜 𝑠 =0 𝑍2 + 𝑍3
3 𝑍𝐷 (𝑠) Converter input impedance, with the

control variable set to zero
𝑖𝑖𝑎
+ L
+
𝑔𝑖𝑑 𝑑መመ 𝑔𝑖𝑣𝑜 𝑣ො𝑜1 𝑔𝑜𝑑 𝑑መመ 𝑔𝑜𝑣𝑖 𝑣ො𝑔 - -
𝑔𝑖𝑑 𝑑 𝑔𝑜𝑑 𝑑
𝑣ො𝑜 = 𝑔𝑜𝑣𝑖 𝑣ො𝑔 𝑍 𝑖Ƹ𝑖𝑎 = 𝑔𝑖𝑣𝑜 𝑔𝑜𝑣𝑖 𝑣ො𝑔 𝑍
𝑣ො𝑔 𝑣ො𝑔 1
𝑍𝐷 = 𝑖Ƹ = 𝑔 ො𝑔
=
𝑖𝑎 𝑖𝑣𝑜 𝑔𝑜𝑣𝑖 𝑣 𝑍 𝑔 𝑖𝑣𝑜 𝑔𝑜𝑣𝑖 𝑍
4 𝑍𝑁 (𝑠) Converter input impedance, with the

output nulled to zero
𝑖𝑖𝑎
+ L
+
𝑔𝑖𝑑 𝑑መ 𝑔𝑖𝑣𝑜 𝑣ො𝑜 𝑔𝑜𝑑 𝑑መ 𝑔𝑜𝑣𝑖 𝑣ො𝑔 - -
−𝑔𝑜𝑣𝑖
መ 𝑔𝑜𝑣𝑖 𝑣ො𝑔 = 0
𝑔𝑜𝑑 𝑑+ 𝑑መ = 𝑣ො
𝑔𝑜𝑑 𝑔
−𝑔𝑜𝑣𝑖 𝑣ො𝑔 𝑣ො𝑔 𝑔𝑜𝑑

𝑖Ƹ𝑖𝑎 = 𝑔𝑖𝑑 𝑑መ = 𝑔𝑖𝑑 𝑣ො 𝑍𝑁 = = =−
𝑔𝑜𝑑 𝑔 𝑖Ƹ𝑖𝑎 𝑔𝑖𝑑 −𝑔𝑜𝑣𝑖 𝑣ො𝑔 𝑔𝑖𝑑 𝑔𝑜𝑣𝑖
𝑔 𝑜𝑑
𝑍𝑜 𝑠 = 𝑍𝑓 1 𝑍𝑜 (𝑠) Output impedance of input filter

𝑍3
𝐺𝑣𝑑 𝑠 ቚ = 𝑔𝑜𝑑 𝑍𝑒𝑞 2 𝐺𝑣𝑑 𝑠 ቚ Original transfer function, before addition
𝑍𝑜 𝑠 =0 𝑍2 + 𝑍3
ෞ
𝑣 1
𝑍𝐷 𝑠 =
𝑔
= 3 𝑍𝐷 (𝑠) Converter input impedance, with the
𝑖෢
𝑖𝑎 𝑍 · 𝑔𝑖𝑣𝑜 · 𝑔𝑜𝑣𝑖 control variable set to zero
ෞ
𝑣𝑔 −𝑔𝑜𝑑 4 𝑍𝑁 (𝑠) Converter input impedance, with the
𝑍𝑁 (𝑠)= =
𝑖෢
𝑖𝑎 𝑔𝑖𝑑 . 𝑔𝑜𝑣𝑖 output nulled to zero
𝑍3
𝑍 = 𝑍𝑒𝑞
𝑍2 + 𝑍3
𝑍𝑓
𝑍𝑜 (𝑠) 1 + −𝑔𝑜𝑑
𝑣
ෞ𝑜 1+ 𝑔𝑜𝑑 − 𝑍𝑓 𝑔𝑖𝑑 𝑔𝑜𝑣𝑖
𝑍𝑁 (𝑠) 𝑔𝑖𝑑 . 𝑔𝑜𝑣𝑖
𝐺𝑣𝑑1 𝑠 = = 𝐺𝑣𝑑 𝑠 ቚ = 𝑔𝑜𝑑 𝑍 =𝑍
𝑑መ 𝑍𝑜 𝑠 =0 𝑍 (𝑠)
1+ 𝑜
𝑍𝑓 1 + 𝑍𝑓 𝑍 · 𝑔𝑖𝑣𝑜 · 𝑔𝑜𝑣𝑖
𝑍𝐷 (𝑠) 1+ 1
𝑍 · 𝑔𝑖𝑣𝑜 · 𝑔𝑜𝑣𝑖
DAB with input LC filter: circuit analysis
Transfer function including input filter (Option 2)

𝑍2
𝑍𝑓
𝑖෠ 𝑜𝑎 + +
+
+ 𝑖Ƹ𝑖𝑎 DAB
𝑣ො𝑜 = 𝑍 𝑖Ƹ𝑜𝑎 𝑣ො𝑔 ’ 𝑣ො𝑖 𝑍1 𝑣ෝ 𝑜1 𝑍3 𝑣ො𝑜
Converter
- - -
𝑣ො𝑜 = 𝑍 𝑔𝑜𝑑 𝑑መ + 𝑔𝑜𝑣𝑖 𝑣ො𝑖
𝑣ො𝑖 =𝑣ො𝑔 ′ − 𝑖Ƹ𝑖𝑎 𝑍𝑓 𝑍𝑒𝑞 = 𝑍2 + 𝑍3 ԡ𝑍1

𝑍3
𝐿𝑒𝑡 ′ 𝑠 𝑐𝑜𝑛𝑠𝑖𝑑𝑒𝑟 𝑣ො𝑔 ′ = 0 𝑍 = 𝑍𝑒𝑞 .
𝑍2 + 𝑍3
𝑣ො𝑜 = 𝑍 𝑔𝑜𝑑 𝑑መ + 𝑔𝑜𝑣𝑖 −𝑖𝑖𝑎 Ƹ 𝑍𝑓
𝑣ො𝑜 = 𝑍 𝑔𝑜𝑑 𝑑መ −𝑔𝑜𝑣𝑖 𝑍𝑓 𝑔𝑖𝑑 𝑑መ + 𝑔𝑖𝑣𝑜 𝑉෡𝑜
𝑣ො𝑜 𝑔𝑜𝑑 −𝑔𝑜𝑣𝑖 · 𝑔𝑖𝑑 · 𝑍𝑓

𝐺𝑣𝑑2 𝑠 = =𝑍
𝑑መ 1 + 𝑔𝑜𝑣𝑖 · 𝑔𝑖𝑣𝑜 · 𝑍 · 𝑍𝑓
DAB with input LC filter: comparison
Comparison of Gvd applying EET (G) Comparison of theoretical Gvd and

and Gvd applying circuit analysis (Gvd) simulated Gvd with PSIM
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
DAB with input and output filters and parasitics
Example based on F. Krismer and J. W. Kolar, "Accurate Small-Signal Model for the Digital Control of an
Automotive Bidirectional Dual Active Bridge," in IEEE Transactions on Power Electronics, vol. 24, no.
12, pp. 2756-2768, Dec. 2009.
//CONVERTIDOR
n=24
Rlk=1/n^2 //FILTRO DE SALIDA
//FILTRO DE ENTRADA L=31u Cf2=3.3u
Cf1=1000u Lk =L/n^2 Lf2a=20u
Lf1=100n f = 100k Rf2a=10m
RLf1=0.1 Vi=12V Lf2b=10u
Vo=349 Rf2b=3.1
d=0.3 Cdc2=220u
Additional parasitics are considered: ESR of output filter inductor and ESR
of DAB coupling inductor Llk
𝑍2
𝑍𝑓 𝑅𝐿𝑘
+ +
+ + Average model of
𝑖෢
𝑜𝑎
+
෢′𝑔
𝑣 𝑣ෝ 𝑖1 𝑖෢
𝑖𝑎 𝑣ෝ 𝑖 lossless DAB 𝑍1 𝑣ෝ 𝑜1 𝑍3 𝑣ෝ 𝑜
- converter
- - -
𝑍𝑒𝑞
Output filter and load in steady state
𝑅2 1 − 𝐷 · 𝐷 · 𝑇 · 𝑉𝑔
𝑅𝑒𝑞 = 𝑅2 +𝑅𝑐 𝑉𝑜1 = 𝑅𝑒𝑞
𝑛 · 𝐿𝑘
+ +
𝑖𝑜𝑎 Rc is de load
𝑣ෝ 𝑜1 𝑅𝑐 𝑣ෝ 𝑜
- -
𝑉𝑖 1
𝑅𝑒𝑞
= 𝑅𝑖 = 2
𝐼𝑖𝑎 1−𝐷 ·𝐷·𝑇
𝑅𝑒𝑞
𝑛 · 𝐿𝑘
𝑉𝑖 1
= 𝑅𝑖 = 2
𝐼𝑖𝑎 1−𝐷 ·𝐷·𝑇
𝑅𝑒𝑞
𝑛 · 𝐿𝑘
𝑅𝑓 𝑅𝐿𝑘
+ +
+
𝑉𝑔 𝑉𝑖1 𝑖𝑖𝑎 𝑉𝑖 𝑅𝑖
- -
𝑅𝑖 Voltage at the input of ideal converter model

𝑉𝑖 = 𝑉𝑔
𝑅𝑖 + 𝑅𝑓 + 𝑅𝐿𝑘
𝑅𝑖 + 𝑅𝐿𝑘 Voltage at the input of the converter. This voltage can be

𝑉𝑖1 = 𝑉𝑔
𝑅𝑖 + 𝑅𝑓 + 𝑅𝐿𝑘 considered constant if the input capacitor is high enough.
Summarizing in steady state 𝑍2

𝑍𝑓 𝑅𝐿𝑘
+ +
𝑖෢
𝑜𝑎
+
෢′𝑔
𝑣 𝑣ෝ 𝑖1 𝑖෢
- converter
- - -
𝑅𝑒𝑞 = 𝑅2 +𝑅𝑐 𝑍𝑒𝑞

1
𝑅𝑖 = 2 1 − 𝑑 . 𝑑. 𝑇. 𝑉𝑖 1 − 𝑑 . 𝑑. 𝑇. 𝑉𝑜1
1−𝐷 𝐷·𝑇 𝑖𝑜𝑎 = 𝑖 𝑖𝑎 =
𝑅𝑒𝑞 𝑛. 𝐿𝑘 𝑛. 𝐿𝑘
𝑛 · 𝐿𝑘
𝑅𝑖
𝑉𝑖 = 𝑉𝑔
𝑅𝑖 + 𝑅𝐿𝑘
𝑉𝑖1 = 𝑉𝑔
1 − 𝐷 𝐷 · 𝑇 · 𝑉𝑖 𝑅𝑐
𝑉𝑜1 = 𝑅𝑒𝑞 𝑉𝑜 = 𝑉
𝑛 · 𝐿𝑘 𝑅2 + 𝑅𝑐 𝑜1
𝑍2
Small signal 𝑍𝑓 𝑅𝐿𝑘
+ +
𝑖෢
𝑜𝑎
+
෢𝑔
𝑣′ 𝑣ෝ 𝑖1 𝑖෢
- converter
- - -
𝑍3 𝑍𝑒𝑞
𝑍 = 𝑍𝑒𝑞
𝑍2 + 𝑍3
𝑣
ෞ𝑜 𝑔𝑜𝑑 −𝑔𝑜𝑣𝑖 𝑔𝑖𝑑 · 𝑍𝑓
=𝑍·
𝑑መ 1 + 𝑔𝑜𝑣𝑖 𝑔𝑖𝑣𝑜 𝑍 · 𝑍𝑓
(1 − 2𝐷) 𝑉𝑜1 1 − 2𝐷
𝑔𝑜𝑑 = 𝑇 · 𝑉𝑖 =
𝑛𝐿𝑘 1 − 𝐷 𝐷𝑅𝑒𝑞
(1 − 2𝐷) 𝑉𝑜1
𝑔𝑖𝑑 = 𝑇 · 𝑉𝑜1 = 𝑔𝑜𝑑
𝑛𝐿𝑘 𝑉𝑖
1−𝐷 ·𝐷·𝑇 𝑉𝑜1

𝑔𝑜𝑣𝑖 = 𝑔𝑜𝑣𝑖 = =
𝑛𝐿𝑘 𝑉𝑖 𝑅𝑒𝑞
Result including a time delay td=1/(2*fsw): 𝑝ℎ𝑎𝑠𝑒 = 𝑝ℎ𝑎𝑠𝑒 − 𝑡𝑑 ∗ 𝑓 ∗ 360
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
Resonant DAB small signal model
𝑖𝑔
1:n 𝑖𝑜
Vg 𝑖I𝑔i n·Io𝑖 C R Average

𝑜 model
8 𝑉𝑔 𝜑𝐴𝐵 𝜑𝐷𝐶 𝜑𝐷𝐶 − 𝜑𝐴𝐵

𝑖𝑜 = 𝐻 (𝑟) sin sin sin 𝜑 +
𝑛 · 𝜋 2 𝑍0 0 2 2 𝐴𝐷
2
8 𝑉𝑜 𝜑𝐴𝐵 𝜑𝐷𝐶 𝜑𝐷𝐶 − 𝜑𝐴𝐵 Linearization
𝑖𝑔 = 𝐻 (𝑟) sin sin sin 𝜑 +
𝑛 · 𝜋 2 𝑍0 0 2 2 𝐴𝐷
2 and
perturbation
+
𝑣ො𝑔 C R 𝑣ො 𝑜 Small signal
𝑔𝑖4 𝜔
ෝ 𝑔𝑖5 𝑣ො𝑜 𝑔𝑜5 𝑣ො𝑔 𝑔𝑜4 𝜔
ෝ - model
𝐴𝐷 𝑔𝑖2 𝜑ෞ
𝑔𝑖1 𝜑ෞ 𝐴𝐵 𝑔𝑖3 𝜑ෞ
𝐷𝐶 𝑔𝑜3𝜑ෞ 𝐴𝐵 𝑔𝑜1 𝜑ෞ
𝐷𝐶 𝑔𝑜2 𝜑ෞ 𝐴𝐷
𝜕𝑖𝑔 𝜕𝑖𝑜
𝑔𝑖3 = 𝜑ෞ 𝑔𝑜4 = 𝜔
ෝ
𝜕𝜑𝐷𝐶 𝐷𝐶 𝜕𝜔
Resonant DAB transfer function
If only 𝜔 is perturbated (frequency control)
𝑔𝑜4 𝜔
ෝ
+
𝑔𝑖4 𝜔
ෝ -
𝜕𝑖𝑔 𝜕𝑖𝑜
𝑔𝑖4 = 𝜔
ෝ 𝑔𝑜4 = 𝜔
ෝ
𝜕𝜔 𝜕𝜔
𝑅
𝑣ො𝑜 = 𝑔 ·𝜔ෝ
𝑅𝐶𝑠 + 1 𝑜4
Unexpected resonance appears
Control to output transfer function. Switching frequency changes
Interaction between the perturbation

frequency and the resonance
When the switching frequency is perturbates, a

modulated signal is generated
Side bands of the voltage applied to the

resonant tank can excite the resonance
𝑓𝑠𝑖𝑑𝑒 ≈ 𝑓𝑠𝑤 − 𝑓𝑝𝑒𝑟𝑡𝑢𝑟𝑏
When 𝑓𝑠𝑖𝑑𝑒 = 𝑓𝑜 output voltage is increased
In the simulation, resonance frequency 𝑓𝑜 is

excite for different values of 𝑓𝑝𝑒𝑟𝑡𝑢𝑟𝑏
Summary
Averaging techniques can be applied to DAB (non resonant)

▪ Dynamics is provided by external elements (output filter and eventually
input filter)
▪ The effect of additional elements (output and input filters) can be
assessed using a circuital approach
Resonant DAB exhibits a different behavior
▪ Averaging techniques used in DAB PS can be applied, but only low
frequency behavior is predicted
▪ Resonance effect appear as the signal applied to the resonant tank is a
modulated signal
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
Discrete-time modeling of the converter. Introduction
Method applicable to converters with constant frequency DPWM that can

be modelled in the state space
A transfer function in the discrete domain is obtained, which takes into
account
▪ Delays
▪ Ripple (no small alias assumption is required)
COMPENSATOR DPWM PLANT

VOUT
VREF C(z) GDPWM Gvd(z)
“d”
-
GADC GSENSOR
ADC SENSOR
“Digital Control of High-Frequency Switched-Model

Power Converters” Corradini et al., IEEE Press, 2015
Example: voltage-controlled buck converter
Comparison of the averaged model 𝐺𝑣𝑢 (𝑠) and the discrete-time model 𝐺𝑣𝑢 (𝑧)
Similar magnitudes (small alias satisfied) 𝐺𝑣𝑢 † 𝑠 : corrected averaged
Only differences close to Nyquist freq. due to aliasing model including the delay
Phase lag due to Phase lag corrected

time delay by not totally
Analysis of the switching instant on the performed designs
V
• Example of closed loop control of a buck converter

• The steady-state average output voltage depends on
the sampling instant due to the undersampling
• An alias is introduced at DC Discrete
control
Example: current-controlled buck converter
Comparison of the averaged model 𝐺𝑖𝑢 (𝑠) and the discrete-time model
𝐺𝑖𝑢 † 𝑠 : corrected averaged
𝐺𝑖𝑢 (𝑧) model including the delay
The high frequency predictions

improve considering the delay
An extra phase lag is predicted by the discrete-time model due to the modulation delay
Significant differences at low frequencies:
• The continuous-time averaged model predicts a zero at the origin.
• The discrete-time model predicts a nonzero value because of the aliasing effects due to sampling,
which manifest at dc
Sampled current at different instants
Buck converter with current source load
Current averaged by a 2nd filter
• The perturbation of the duty cycle produces a

perturbation in the output voltage
• The current ripple in the inductor also changes, but
the average value remains constant Duty cycle
• As the average value do not take into account the
ripple, the response is a zero at the origin
• Changing the sampling instant changes the low
frequency gain
Sampled current
Inductor current
Buck converter with current source load
• The perturbation of the duty cycle produces a

perturbation in the output voltage
• The current ripple in the inductor also changes, but
the average value remains constant
• As the average value do not take into account the
ripple, the response is a zero at the origin
• Changing the sampling instant changes the low
frequency gain
Review: state space model of a Boost converter
State space model of a Boost converter

▪ Inductor ESR is considered
▪ CCM is assumed
𝑖𝐿 L rL
+
Vg C 𝑣𝑜 Ro
-
𝑑𝒙
Output vector = 𝐴 · 𝒙 𝑡 + 𝐵 · 𝒗(𝑡) Input vector
𝑑𝑡
𝒚 = 𝐶 · 𝒙 𝑡 + 𝐸 · 𝒗(𝑡)
State vector
𝑖𝐿 𝑡
𝒙 𝑡 = 𝒗 𝑡 = 𝑣𝑔 𝑡
𝑣𝑜 𝑡
1 0 𝐸=0
𝐶=𝐼=
0 1
State space model of a Boost converter red=switch on
black=switch off
𝑖𝐿 L rL 𝑖𝐿 L rL
+ +
Vg Ro Vg C Ro
C 𝑣𝑜 𝑣𝑜
- -
𝑖𝐿 𝑡
𝒙 𝑡 =
𝑣𝑜 𝑡
𝑑𝑖𝐿 𝑣𝑔 𝑡 − 𝑟𝐿 𝑖𝐿 𝑡 − 𝑣𝑜 (𝑡)
𝑑𝑖𝐿 𝑣𝑔 𝑡 − 𝑟𝐿 𝑖𝐿 𝑡 =
= 𝑑𝑡 𝐿
𝑑𝑡 𝐿
𝑑𝑣𝐶 𝑑𝑣𝑜 𝑣𝐶 (𝑡) 𝑑𝑣𝐶 𝑖𝐿 𝑡 𝑣𝑜 (𝑡)
= =− = −
𝑑𝑡 𝑑𝑡 𝑅𝑜 𝐶 𝑑𝑡 𝐶 𝑅𝑜 𝐶
𝑟𝐿 𝑟𝐿 1
− 0 1 − − 1
𝑑𝒙 𝐿 𝑑𝒙 𝐿 𝐿
= 1 𝒙 𝑡 + 𝐿 𝑣𝑔 (𝑡) = 1 1 𝒙 𝑡 + 𝐿 𝑣𝑔 (𝑡)
𝑑𝑡 0 − 𝑑𝑡
0 − 0
𝑅𝑜 𝐶 𝐶 𝑅𝑜 𝐶
𝑑𝒙 𝑑𝒙
= 𝐴1 · 𝒙 𝑡 + 𝐵1 · 𝑣𝑔 (𝑡) = 𝐴0 · 𝒙 𝑡 + 𝐵0 · 𝑣𝑔 (𝑡)
𝑑𝑡 𝑑𝑡
State-space averaging
▪ The converter state-space equations are written considering the PWM
control signal 𝑐 𝑡 , which is binary (1 or 0)
▪ Moving average is applied to obtain large signal state-space model. Duty
cycle signal 𝑑 𝑡 (continuous) appear
𝑑𝒙
= 𝑐 𝑡 · 𝐴1 · 𝒙 𝑡 + 𝐵1 · 𝑣𝑔 + 𝑐 ′ (𝑡) 𝐴0 · 𝒙 𝑡 + 𝐵0 · 𝑣𝑔
𝑑𝑡
𝒚 = 𝑐 𝑡 · 𝐶1 · 𝒙 𝑡 + 𝑐′ 𝑡 · 𝐶0 · 𝒙 𝑡
𝑡0 +𝑇/2
moving average operator 𝑥 𝑡 𝑇 ≜න 𝑥 𝜏 𝑑𝜏
𝑡0 −𝑇/2
𝑑ഥ
𝒙
= 𝑑 𝑡 · 𝐴1 + 𝑑 ′ (𝑡) · 𝐴0 · 𝒙
ഥ 𝑡 + 𝐵 · 𝑣𝑔 (𝑡)
𝑑𝑡
𝑐 ′ (𝑡) = 1 − 𝑐 𝑡
ഥ=𝒙
𝒚 ഥ 𝑡
𝑑 ′ (𝑡) = 1 − 𝑑 𝑡
Averaged model
Averaged model
𝑑ഥ
𝒙
= 𝑑 𝑡 · 𝐴1 + 𝑑 ′ (𝑡) · 𝐴0 · 𝒙
ഥ 𝑡 + 𝐵 · 𝑣𝑔 (𝑡)
𝑑𝑡
ഥ=𝒙
𝒚 ഥ 𝑡
Steady State Operating Point: needed to linearize in the vicinity of this point
𝑑ഥ𝒙
=0 0 = 𝐷 · 𝐴1 + 𝐷′ · 𝐴0 · 𝑿 + 𝐷 · 𝐵1 + 𝐷′ · 𝐵0 · 𝑽
𝑑𝑡
𝑑 𝑡 =𝐷
𝑑′ 𝑡 = 𝐷′ 0=𝐴·𝑿+𝐵·𝑽
𝑟 𝐷′ 𝑿 = −𝐴−1 · 𝐵 · 𝑽
− 𝐿𝐿 −𝐿
𝐴 ≜ 𝐷 · 𝐴1 + 𝐷′ · 𝐴0 = 𝐷′ 1 𝒀=𝑿
−𝑅
𝐶 𝑜𝐶
1
𝐵 ≜ 𝐷 · 𝐵1 + 𝐷′ · 𝐵0 = 𝐵 = 𝐿
0
𝐶 ≜ 𝐷 · 𝐶1 + 𝐷′ · 𝐶0 = 𝐼
Small signal model

▪ Linear model in the vicinity of the operating point
▪ Control signal 𝑑መ appears
𝑑ഥ
𝒙 ෡ + 𝐷′ · 𝐴0 · (ෝ
ෝ≜𝒙
𝒙 ഥ 𝑡 −𝑿 = 𝑑መ + 𝐷 · 𝐴1 + 𝑑′ ෝ+𝑽
𝒙 + 𝑿) + 𝐵 · 𝒗
𝑑𝑡
𝑑መ ≜ 𝑑ҧ 𝑡 − 𝐷
ഥ=
𝒚 ෡ + 𝐷′ · 𝐶0 · (ෝ
𝑑መ + 𝐷 · 𝐶1 + 𝑑′ 𝒙 + 𝑿)
ෝ≜𝒗
𝒗 ഥ 𝑡 −𝑽
𝑑ෝ
𝒙
𝐹 ≜ 𝐴1 𝑿 -𝐴0 𝑿 ෝ + 𝐹 · 𝑑መ + 𝐵 · 𝒗
= 𝐴·𝒙 ෝ
𝐺 ≜ 𝐶1 𝑿 - 𝐶0 𝑿 = 0 𝑑𝑡
ෝ =𝐼·𝒙
𝒚 ෡
ෝ+𝐺·𝒅
Using the Laplace transformation

ෝ 𝑠
𝒚
𝑊 𝑠 ≜ = 𝐶 𝑠𝐼 − 𝐴 −1 𝐹 + 𝐺
ෝ=𝐴·𝒙
𝑠·𝒙 ෡+𝐵·𝒗
ෝ+𝐹·𝒅 ෝ 𝑑መ 𝑠
෡+𝐸·𝒗 ෝ 𝑠
𝒚
ෝ =𝐼·𝒙
𝒚 ෝ+𝐺·𝒅 ෝ 𝑊𝐷 𝑠 ≜ = 𝐶 𝑠𝐼 − 𝐴 −1 𝐵 + 𝐸
ෝ 𝑠
𝒗
State space model of a Buck converter
State space small signal model in the Laplace domain

▪ All transfer function referring state variables are obtained
ෝ 𝑠
𝒚 −1 𝐹 −1 𝐹
𝑊 𝑠 ≜ = 𝐶 𝑠𝐼 − 𝐴 + 𝐺 = 𝑠𝐼 − 𝐴
𝑑෠ 𝑠
𝑅𝑜 𝐶
𝑉𝑜 1+𝑠 2
𝑖Ƹ𝐿 𝑠 2·
𝐺𝑖𝑑 ≜ 𝑟𝐿 + 𝐷′2 𝑅𝑜 ∆(𝑠)
𝑑መ 𝑠
𝑊 𝑠 = = 𝑟𝐿 𝐿
𝑣ො𝑜 𝑠 𝑉𝑜 1 − ′2 1 − 𝑠 ′2
𝐺𝑣𝑑 ≜ 𝐷 𝑅𝑜 𝐷 𝑅𝑜 − 𝑟𝐿
𝑑መ 𝑠 𝐷′ 1 + 𝑟𝐿 ∆(𝑠)
𝐷′2 𝑅𝑜
𝑟𝐿 𝑅𝑜 𝐶 + 𝑟𝐿 𝐿𝐶 1
𝐿
∆ 𝑠 ≜ 1 + 𝑠 ′2 𝑟 + 𝑠 2 ′2
𝐷 𝑅𝑜 1 + 𝐿 𝐷 1 + 𝑟𝐿
′2
𝐷 𝑅𝑜 𝐷′2 𝑅𝑜
ෝ 𝑠
𝒚 ෝ 𝑠
𝒚 −1 𝐵 −1 𝐵
𝑊𝐷 𝑠 ≜ = = 𝐶 𝑠𝐼 − 𝐴 + 𝐸 = 𝑠𝐼 − 𝐴
ෝ 𝑠
𝒗 𝑣
ෞ𝑔 𝑠
State space model of a Buck converter
…if 𝑟𝐿 = 0 a much more familiar model appears
ෝ 𝑠
𝒚 −1 −1
𝑊 𝑠 ≜ 𝑑෠ = 𝐶 𝑠𝐼 − 𝐴 𝐹 + 𝐺 = 𝑠𝐼 − 𝐴 𝐹
𝑠
𝑅𝑜 𝐶
𝑖Ƹ𝐿 𝑠 𝑉𝑜 1 + 𝑠 2
𝐺𝑖𝑑 ≜ 2 · ′2
𝑑መ 𝑠 𝐷 𝑅𝑜 ∆(𝑠)
𝑊 𝑠 = = 𝐿
𝑣ො𝑜 𝑠 1 − 𝑠
𝐺𝑣𝑑 ≜ 𝑉𝑜 𝐷′2 𝑅𝑜
𝑑መ 𝑠
𝐷′ ∆(𝑠)
𝐿 2 𝐿𝐶
∆ 𝑠 ≜ 1+𝑠 + 𝑠
𝐷′2 𝑅𝑜 𝐷′2
ෝ 𝑠
𝒚 ෝ 𝑠
𝒚 −1 𝐵 −1 𝐵
𝑊𝐷 𝑠 ≜ = = 𝐶 𝑠𝐼 − 𝐴 + 𝐸 = 𝑠𝐼 − 𝐴
ෝ 𝑠
𝒗 𝑣
ෞ𝑔 𝑠
Bode plot
%Converter specifications
1 Vg=12;
Vo=24;
L=31e-6;
rl=50e-3;
C=33e-6;
P=20;
R=Vo^2/P;
fsw=100e3;
D=1-Vg/Vo;
T=1/fsw;
td=(D+0.2)*T;
%State Spapce matrices
2
A1=[-rl/L 0; 0 -1/(R*C)];
A2=[-rl/L -1/L; 1/C -1/(R*C)];
B1=[1/L ; 0];
B2=[1/L ; 0];
3 %Continous model
As=D*A1+(1-D)*A2;
Bs=D*B1+(1-D)*B2;
Cs=eye(2);
Ds=0;
Xops=[P/Vg; Votrue];
Fops=(A1-A2)*Xops;
Gops=0;
Smodel=ss(As,Fops,Cs,Ds);
Xs=tf(Smodel);
Bode plot Continous time model
PSIM Simulation
𝑣ො𝑜 𝑠 𝑖𝐿Ƹ 𝑠
𝐺𝑖𝑑 ≜
Magnitude (dB)
𝐺𝑣𝑑 ≜
Magnitude (dB)
𝑑መ 𝑠 𝑑መ 𝑠
Phase (deg)
Phase (deg)
Frequency (Hz) Phase (deg) Magnitude (dB) Frequency (Hz)
+ Error in Gvd
* Error in Gid
GSEP http://gsep.uc3m.es Frequency (Hz)

Summary
State Space model

▪ It is a continuous time model
▪ It does not consider the ripple information in a switching period or any
different value of the variable along a switching period. Small alias
assumption is needed to generate model for digital control
▪ It consider the successive states of the converter
Facts
▪ Accurate discrete model must be take into account the value of the
variable at the sampling instant
▪ Information of the internal states could be relevant for the model
Question
▪ Could be a discrete model based on the state space procedure ?
Discrete-time modeling of the converter. Introduction
Steps 𝑑𝒙
= 𝐴 · 𝒙 𝑡 + 𝐵 · 𝒗(𝑡)
𝑑𝑡
▪ Obtaining the state space model of the converter
➢ For each sub circuit, obtain the equation of the state 𝑦 = 𝐶 · 𝒙 𝑡 + 𝐸 · 𝒗(𝑡)
variables and its derivative
➢ State variables are typically the inductor currents and the
capacitor voltages in the circuit
➢ Output variables have also to be defined
▪ Applying perturbations
➢ Obtain the matrix which describes the propagation of a
perturbation in the state vector
➢ Obtain the matrix which describes the propagation of the
perturbation of the control signal (e.g. d)
▪ Obtaining the difference equation in the state space
▪ Obtaining the z-domain model of the converter
➢ Each output variable implies a transfer function
Discrete-time modeling fundamentals
𝑿 Sampling
instants
𝑡𝑑
𝑇𝑠
𝐷 · 𝑇𝑠 S0 S1 S0 S1
𝑿 State vector at sampling instants

S0
states 𝑇𝑠 Switching/sampling instants
S1
𝐷 Steady state control signal value
2
ෝ[𝑘]
𝒙 3
1
Sampling
ෝ1 [𝑘 + 1]
𝒙 instants
𝑡𝑑
𝐷 · 𝑇𝑠 S0 S1 S0 S1
S0 ෝ[𝑘]
𝒙 State small signal perturbation
states
S1
ෝ1 [𝑘 + 1]
𝒙 State small signal perturbation propagated along a period
ෝ1 𝑘 + 1 = 𝜱 · 𝒙
𝒙 ෝ𝑘
State perturbation is propagated

𝜱= 𝑒 𝐴0 𝑇𝑠 −𝑡𝑑 𝑒 𝐴1 𝐷𝑇𝑠 𝑒 𝐴0 𝑡𝑑−𝐷𝑇𝑠 thourgh the different states
3 2 1
3
ෝ2 [𝑘 + 1]
𝒙
ෝ[𝑘]
𝒙
Sampling
ෝ1 [𝑘 + 1]
𝒙 instants
𝑡𝑑
𝐷 · 𝑇𝑠 S0 S1 S0 S1
𝑑 𝑘 − 1 · 𝑇𝑠 𝑑 𝑘 · 𝑇𝑠 𝑑 𝑘 + 1 · 𝑇𝑠
𝑢ො 𝑘 = 𝑑መ 𝑘 · 𝑇𝑠
S0
states 𝑢ො 𝑘 Control small signal perturbation
S1
ෝ2 [𝑘 + 1]
𝒙 State perturbation due to control propagated up to the end of the period
𝑋↓ Steady state vector at the instant when control perturbation is applied
ෝ2 𝑘 + 1 = 𝜸 · 𝑢ො 𝑘
𝒙
𝜸 = 𝑒 𝐴0 𝑇𝑠 −𝑡𝑑
𝐴1 𝑋↓ + 𝐵1 𝑉 − 𝐴0 𝑋↓ + 𝐵0 𝑉 𝑇𝑠 State perturbation is propagated only
through some states
3 State perturbation due to control
perturbation
ෝ2 [𝑘 + 1]
𝒙
ෝ[𝑘]
𝒙
Sampling
ෝ1 [𝑘 + 1]
𝒙 instants
𝑡𝑑
𝐷 · 𝑇𝑠 S0 S1 S0 S1
𝑑 𝑘 − 1 · 𝑇𝑠 𝑑 𝑘 · 𝑇𝑠 𝑑 𝑘 + 1 · 𝑇𝑠
𝑢ො 𝑘 = 𝑑መ 𝑘 · 𝑇𝑠
ෝ 𝑘+1 = 𝜱·𝒙
𝒙 ෝ 𝑘 + 𝜸 · 𝑢ො 𝑘 𝜹 = 𝑪𝟎 If sampling occurs during S0
ෝ 𝑘 =𝜹·𝒙
ෝ𝑘 𝜹 = 𝑪𝟏 If sampling occurs during S1
𝒚
𝑖Ƹ𝐿𝑙𝑘 𝑧
−1 𝜸 𝐺𝑖𝑑 ≜
ෝ 𝑧 =𝜱·𝒙
𝑧·𝒙 ෝ 𝑧 + 𝜸 · 𝑢ො 𝑧 z-transform ෝ(𝑧) = 𝑧 · 𝑰 − 𝜱
𝒙 · 𝑢(𝑧)
ො = 𝑢 𝑧 · 𝑢(𝑧)
ො
𝐺𝑣𝑑 ≜
ෝ 𝑧 =𝜹·𝒙
𝒚 ෝ𝑧
ෝ 𝑧 = 𝜹·𝒙
𝒚 ෝ(𝑧)
𝑪𝟎 = 𝑪𝟏 = 𝑰

Model implementation (Matlab)
%Converter specifications %State Spapce matrices
1 Vg=12; 2
Vo=24; A1=[-rl/L 0; 0 -1/(R*C)];
L=31e-6; A2=[-rl/L -1/L; 1/C -1/(R*C)];
rl=50e-3; B1=[1/L ; 0];
C=33e-6; B2=[1/L ; 0];
P=20;
R=Vo^2/P;
fsw=100e3;
D=1-Vg/Vo;
T=1/fsw;
td=(D+0.2)*T;
3 %Continous model 4 %Discrete Model

As=D*A1+(1-D)*A2;
Bs=D*B1+(1-D)*B2; Xdown=[Ildown ; Vodown];
Cs=eye(2); PHI=expm(A2*(T-td))*expm(A1*D*T)*expm(A2*(-
Ds=0; D*T+td));
gamma=expm(A2*(T-td))*(A1*Xdown+B1*Vo-
Xops=[P/Vg; Votrue]; (A2*Xdown+B2*Vo))*T;
Fops=(A1-A2)*Xops;
Gops=0; z=tf('z',Tsamp);
Xz=inv(z*eye(2)-PHI)*gamma;
Smodel=ss(As,Fops,Cs,Ds);
Xs=tf(Smodel);
Model comparison: simulation scheme
Discrete time model of a boost converter
Discrete time model

PSIM Simulation
Continous time model
Magnitude (dB)
Magnitude (dB)
Phase (deg)
Phase (deg)
Frequency (Hz) Frequency (Hz)
Dicrete time model of a boost converter: comparison vs simulation
+ Error in Gvd(z) + Error in Gvd(s)

* Error in Gid(z) * Error in Gid(s)
In this case the
simulation includes the
sampling of the duty
Magnitude (dB)
cycle control signal

Phase (deg)
Frequency (Hz) Frequency (Hz)
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
Discrete-time modeling of the DAB
Steps
▪ Obtaining the state space model of the converter:
➢ Phase shift is considered, sampling at the rising slope of 𝑉𝐷𝐴𝐵2
➢ For each subcircuit, obtain the equation of the state variables and its
derivative → 4 subcircuits
𝑖
➢ State variables: inductor current and output voltage 𝒙 = 𝐿
𝑣𝑐
at the sampling instants
➢ Output variable: state variables 𝑪𝟎 = 𝑪𝟏 = 𝑰 ෝ[𝑘] = 𝒙
𝒚 ෝ[𝑘]
▪ Applying perturbations
➢ Obtain 𝜱 (propagation of a perturbation in the state vector) numerical approach
➢ Obtain 𝜸 (propagation of the perturbation of d) with Matlab
▪ Obtaining the difference equation in the state space
▪ Obtaining the z-domain model of the converter
➢ Each output variable implies a transfer function
𝑖𝐿𝑙𝑘
Ƹ 𝑧
𝐺𝑖𝑑 ≜
−1 𝜸 𝑢ො 𝑧
ෝ(𝑧) = 𝑧 · 𝑰 − 𝜱
𝒙 · 𝑢(𝑧)
ො = · 𝑢(𝑧)
ො
𝑣ො𝑜 𝑧
𝐺𝑣𝑑 ≜
𝑢ො 𝑧
1
DAB discrete model: state space model 1 0
-1
-2
-3 𝑇
VDAB1 VDAB2
200 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇
100 1 2 3 4
0
-100
-200
Ilk Vlk/5
15
10
5
0
-5
Sampling
-10 instants
-15
0.0099 0.00990625 0.0099125 0.00991875

Time (s)
𝑣𝑐 𝑣𝑐 𝑑𝑖𝐿 𝑑𝑖𝐿 −1
𝑣𝐿 = 𝑣𝑔 − 𝑣𝑔 − = 𝐿 0 1
𝑛 𝑛 𝑑𝑡 𝑑𝑡 = 𝑛𝐿 𝑖𝐿
+ 𝐿 𝑣𝑔
𝑖𝐿 𝑣𝑐 𝑖𝐿 𝑣𝑐 𝑑𝑣𝑐 𝑑𝑣𝑐 1 1 𝑣𝑐
𝑖𝑐 = − − =𝐶 − 0
𝑛 𝑅 𝑛 𝑅 𝑑𝑡 𝑑𝑡 𝑛𝐶 𝑅𝐶
𝑨𝟏 𝑩𝟏
1
-1
-2
-3 𝑇
VDAB1 VDAB2
200 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇
100 1 2 3 4
0
-100
-200
Ilk Vlk/5
15
10
5
0
-5
Sampling
-10 instants
-15
0.0099 0.00990625 0.0099125 0.00991875

Time (s)
𝑣𝑐 𝑣𝑐 𝑑𝑖𝐿 𝑑𝑖𝐿 −1
𝑣𝐿 = −𝑣𝑔 − −𝑣𝑔 − = 𝐿 0 1
𝑛 𝑛 𝑑𝑡 𝑑𝑡 = 𝑛𝐿 𝑖𝐿 −
+ 𝐿 𝑣𝑔
𝑖𝐿 𝑣𝑐 𝑖𝐿 𝑣𝑐 𝑑𝑣𝑐 𝑑𝑣𝑐 1 1 𝑣𝑐
𝑖𝑐 = − − =𝐶 − 0
𝑨𝟐 𝑩𝟐
1
-1
-2
-3 𝑇
VDAB1 VDAB2
200 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇
100 1 2 3 4
0
-100
-200
Ilk Vlk/5
15
10
5
0
-5
Sampling
-10 instants
-15
0.0099 0.00990625 0.0099125 0.00991875

Time (s)
𝑣𝑐 𝑣𝑐 𝑑𝑖𝐿 𝑑𝑖𝐿 1
𝑣𝐿 = −𝑣𝑔 + −𝑣𝑔 + = 𝐿 0 1
𝑛 𝑛 𝑑𝑡 𝑑𝑡 = 𝑛𝐿 𝑖𝐿 −
+ 𝐿 𝑣𝑔
𝑖𝐿 𝑣𝑐 𝑖𝐿 𝑣𝑐 𝑑𝑣𝑐 𝑑𝑣𝑐 −1 1 𝑣𝑐
𝑖𝑐 = − − − − =𝐶 − 0
𝑨𝟑 𝑩𝟑
1
-1
-2
-3 𝑇
VDAB1 VDAB2
200 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇
100 1 2 3 4
0
-100
-200
Ilk Vlk/5
15
10
5
0
-5
Sampling
-10 instants
-15
0.0099 0.00990625 0.0099125 0.00991875

Time (s)
𝑣𝑐 𝑣𝑐 𝑑𝑖𝐿 𝑑𝑖𝐿 1
𝑣𝐿 = 𝑣𝑔 + 𝑣𝑔 + = 𝐿 0 1
𝑛 𝑛 𝑑𝑡 𝑑𝑡 = 𝑛𝐿 𝑖𝐿
+ 𝐿 𝑣𝑔
𝑖𝐿 𝑣𝑐 𝑖𝐿 𝑣𝑐 𝑑𝑣𝑐 𝑑𝑣𝑐 −1 1 𝑣𝑐
𝑖𝑐 = − − − − =𝐶 − 0
𝑨𝟒 𝑩𝟒
1
DAB discrete model: state space model 0
-1
-2
-3 𝑇
VDAB1 VDAB2
200 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇
𝑨𝟏 = 𝑨𝟐 100 1 2 3 4
𝑨𝟑 = 𝑨𝟒 0
-100
𝑩𝟐 = 𝑩𝟑 𝐷2 = 𝐷; 𝐷1 = 1 − 𝐷 ; -200
𝑇 = 0.5/𝑓𝑠𝑤
𝑩𝟏 = 𝑩𝟒 15
Ilk Vlk/5
10
5
𝑨𝟏 𝑩𝟏 0 𝑨𝟐 𝑩𝟐
-5
𝑑𝑖𝐿 −1 𝑑𝑖
-10 𝐿 −1
0 1 -15 0 1
𝑑𝑡 = 𝑛𝐿 𝑖𝐿 𝑑𝑡 0.0099 𝑛𝐿 𝑖 𝐿 −
+ 𝐿 𝑣𝑔 = 0.00990625
+ 0.00991875
0.0099125
𝐿 𝒗𝒈
𝑑𝑣𝑐 1 1 𝑣𝑐 𝑑𝑣𝑐 1 1 𝑣𝑐
Time (s)
− 0 − 0
𝑑𝑡 𝑛𝐶 𝑅𝐶 𝑑𝑡 𝑛𝐶 𝑅𝐶
𝑑𝑖𝐿 1 𝑑𝑖𝐿 1
0 1 0 1
𝑑𝑡 = 𝑛𝐿 𝑖𝐿 − 𝑑𝑡 = 𝑛𝐿 𝑖𝐿
+ + 𝐿 𝒗𝒈
𝑑𝑣𝑐 −1 1 𝑣𝑐 𝐿 𝒗𝒈 𝑑𝑣𝑐 −1 1 𝑣𝑐
− 0 − 0
𝑑𝑡 𝑛𝐶 𝑅𝐶 𝑑𝑡 𝑛𝐶 𝑅𝐶
𝑨𝟑 𝑩𝟑 𝑨𝟒 𝑩𝟒
1
-1
-2
-3 𝑇
VDAB1 VDAB2
200 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇
𝑨𝟏 = 𝑨𝟐 100 1 2 3 4
𝑨𝟑 = 𝑨𝟒 0
-100
𝑩𝟐 = 𝑩𝟑 𝐷2 = 𝐷; 𝐷1 = 1 − 𝐷 ; -200
𝑇 = 0.5/𝑓𝑠𝑤
𝑩𝟏 = 𝑩𝟒 15
Ilk Vlk/5
10
5
0
-5
Sampling
𝜱 = 𝑒 𝐴4 𝐷2𝑇 𝑒 𝐴3 𝐷1 𝑇 𝑒 𝐴2 𝐷2 𝑇 𝑒 𝐴1 𝐷1𝑇 -10
-15
instants
0.0099 0.00990625 0.0099125 0.00991875

Time (s)
𝜱 = 𝑒 𝐴4 𝐷𝑇
𝑒 𝐴4 1−𝐷 𝑇
𝑒 𝐴2 𝐷𝑇
𝑒 𝐴2 1−𝐷 𝑇
𝜱 = 𝑒 𝐴4𝑇 𝑒 𝐴2 𝑇
1
-1
-2
Propagation of control signal perturbation -3
VDAB1 VDAB2
𝑇
▪ In this case 𝑉𝐷𝐴𝐵2 is fixed and 𝑉𝐷𝐴𝐵1 moves when 200 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇

d changes 100 1 2 3 4
▪ Control signal variation occurs twice in a 0
switching cycle -100
▪ Gamma matrix has two terms -200
▪ 𝑋↓4 is the state vector (𝑖𝐿 𝑎𝑛𝑑 𝑣𝑜 ) at instant 2 Ilk Vlk/5
15
10
▪ 𝑋↓2 is the state vector (𝑖𝐿 𝑎𝑛𝑑 𝑣𝑜 ) at instant 1 5

0
-5
Sampling
-10 instants
-15
0.0099 0.00990625 0.0099125 0.00991875

Time (s)
𝜸 = 𝑒 𝐴4 𝐷·𝑇
𝐴4 − 𝐴3 )𝑋↓4 + (𝐵4 − 𝐵3 )𝑉𝑔 𝑇+
+𝑒 𝐴4 𝐷·𝑇
𝑒 𝐴3 (1−𝐷)·𝑇
𝑒 𝐴2 𝐷·𝑇
𝐴2 − 𝐴1 )𝑋↓2 + (𝐵2 − 𝐵1 )𝑉𝑔 𝑇
𝜸 = 𝑒 𝐴4 𝐷·𝑇
− 𝑒 𝐴4 𝑇 𝑒 𝐴2 𝐷·𝑇
2 · 𝐵4 · 𝑉𝑔 · 𝑇
DAB discrete model: state space model
Final model
𝜱 = 𝑒 𝐴4𝑇 𝑒 𝐴2 𝑇
𝜸 = 𝑒 𝐴4 𝐷·𝑇 − 𝑒 𝐴4 𝑇 𝑒 𝐴2 𝐷·𝑇 2 · 𝐵4 · 𝑉𝑔 · 𝑇
𝐺𝑖𝑑 ≜
−1 𝜸 𝑢ො 𝑧
ෝ(𝑧) = 𝑧 · 𝑰 − 𝜱
𝒙 · 𝑢(𝑧)
ො = · 𝑢(𝑧)
ො
𝑣ො𝑜 𝑧
𝐺𝑣𝑑 ≜
𝑢ො 𝑧
ෝ 𝑧 =𝒙
𝒚 ෝ(𝑧)
DAB discrete model: state space model
% x1=inductor current
% x2=output voltage
T=0.5*1/fsw; %semiperiodo
Tsamp=1/fsw;
Vo= R*Vg*(T)*D*(1-D)/(L*n);
I1pos=1/n*T/(2*L)*(2*Vo/n*D+Vg-Vo/n);
I1neg=-I1pos;
%Discrete model
A1=[0 -1/(n*L); 1/(n*C) -1/(R*C)];

A2=[0 -1/(n*L); 1/(n*C) -1/(R*C)];
A3=[0 1/(n*L); -1/(n*C) -1/(R*C)];
A4=[0 1/(n*L); -1/(n*C) -1/(R*C)];
B1=[1/L ; 0];
B2=[-1/L ; 0];
B3=[-1/L ; 0];
B4=[1/L ; 0];
Xdown4=[I1neg ; Vo];
Xdown2=[I1pos ; Vo];
PHI=expm((A4+A2)*T)
gamma=expm(A4*D*T)*((A4-A3)*Xdown4+(B4-B3)*Vg)*T/Nr+expm(A4*D*T)*expm(A3*(1-D)*T)*expm(A2*D*T)*((A2-
A1)*Xdown2+(B2-B1)*Vg)*T/Nr;
z=tf('z',Tsamp);
Xz=inv(z*eye(2)-PHI)*gamma;
zpk(Xz)
bode(Xz)
DAB discrete model: bode plot
Bode plot of the system
𝑖𝐿𝑙𝑘
Ƹ 𝑧
𝐺𝑖𝑑 ≜
𝑢ො 𝑧
𝑣ො𝑜 𝑧
𝐺𝑣𝑑 ≜
𝑢ො 𝑧
DAB discrete model: bode plot
Comparison between discrete and continuous time model

▪ Delays are taken into account
▪ Magnitude difference at high frequency du to aliasing is taken into
account
Blue: discrete model

Orange: continous model
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
Resonant DAB discrete model VDAB1 VDAB2
𝑇
40 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇
1 2 3 4
20
𝑖𝐿 -20
+ -40
+ +𝑣𝑐𝑟- +𝑣𝐿 - 𝑣𝑐
𝑣𝑔
-
- VL+VCr IL
1:n
300
200
100
0
-100
-200
-300
0.02290039 0.02291016
Time (s)
𝑣𝑐 𝑣𝑐 𝑑𝑖𝐿 𝑑𝑖𝐿 −1 1
𝑣𝐿 + 𝑣𝑐𝑟 = 𝑣𝑔 − 𝑣𝑔 − − 𝑣𝑐𝑟 = 𝐿 0 −
𝑛 𝑛 𝑑𝑡 𝑑𝑡 𝑛𝐿 𝐿 1
1 −1 𝑖𝐿
𝑖𝐿 𝑣𝑐 𝑖𝐿 𝑣𝑐 𝑑𝑣𝑐 𝑑𝑣𝑐
𝑖𝑐 = − − =𝐶 = 0 𝑣𝑐 + 𝐿 𝑣𝑔
𝑛 𝑅 𝑛 𝑅 𝑑𝑡 𝑑𝑡 𝑛𝐶 𝑅𝐶 𝑣𝑐𝑟 0
𝑑𝑣𝑐𝑟 1 0
𝑖𝐿 𝑑𝑣𝑐𝑟 0 0
= 𝑑𝑡 𝐶𝑟
𝐶𝑟 𝑑𝑡
𝑇
40 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇
1 2 3 4
20
𝑖𝐿 -20
+ -40
𝑣𝑔
-
- VL+VCr IL
1:n
300
200
100
0
-100
-200
-300
0.02290039 0.02291016
Time (s)
𝑣𝑐 𝑣𝑐 𝑑𝑖𝐿 −1 1
𝑣𝐿 + 𝑣𝑐𝑟 = −𝑣𝑔 − −𝑣𝑔 − − 𝑣𝑐𝑟 = 𝐿 𝑑𝑖𝐿
𝑛 𝑛 𝑑𝑡 0 −
𝑑𝑡 𝑛𝐿 𝐿 1
1 −1 𝑖𝐿 −
𝑖𝐿 𝑣𝑐 𝑖𝐿 𝑣𝑐 𝑑𝑣𝑐 𝑑𝑣𝑐 𝐿 𝑣
𝑖𝑐 = − − =𝐶 = 0 𝑣𝑐 + 𝑔
= 𝑑𝑡 𝐶𝑟
𝐶𝑟 𝑑𝑡
𝑇
40 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇
1 2 3 4
20
𝑖𝐿 -20
+ -40
𝑣𝑔
-
- VL+VCr IL
1:n
300
200
100
0
-100
-200
-300
0.02290039 0.02291016
Time (s)
𝑣𝑐 𝑣𝑐 𝑑𝑖𝐿 1 1
𝑣𝐿 + 𝑣𝑐𝑟 = −𝑣𝑔 + −𝑣𝑔 + − 𝑣𝑐𝑟 = 𝐿 𝑑𝑖𝐿
−1 −1 𝑖𝐿 −
𝑖𝐿 𝑣𝑐 𝑖𝐿 𝑣𝑐 𝑑𝑣𝑐 𝑑𝑣𝑐 𝐿 𝑣
𝑖𝑐 = − − − − =𝐶 = 0 𝑣𝑐 + 𝑔
= 𝑑𝑡 𝐶𝑟
𝐶𝑟 𝑑𝑡
𝑇
40 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇
1 2 3 4
20
𝑖𝐿 -20
+ -40
𝑣𝑔
-
- VL+VCr IL
1:n
300
200
100
0
-100
-200
-300
0.02290039 0.02291016
Time (s)
𝑣𝑐 𝑣𝑐 𝑑𝑖𝐿 1 1
𝑣𝐿 + 𝑣𝑐𝑟 = 𝑣𝑔 + 𝑣𝑔 + − 𝑣𝑐𝑟 = 𝐿 𝑑𝑖𝐿
−1 −1 𝑖𝐿
𝑖𝐿 𝑣𝑐 𝑖𝐿 𝑣𝑐 𝑑𝑣𝑐 𝑑𝑣𝑐
𝑖𝑐 = − − − − =𝐶 = 0 𝑣𝑐 + 𝐿 𝑣𝑔
= 𝑑𝑡 𝐶𝑟
𝐶𝑟 𝑑𝑡
𝑇
40 𝐷2 𝑇 𝐷1 𝑇 𝐷2 𝑇 𝐷1 𝑇
1 2 3 4
20
𝑨𝟏 = 𝑨𝟐 -20
𝑨𝟑 = 𝑨𝟒 -40
VL+VCr IL
𝑩𝟐 = 𝑩𝟑 𝐷2 = 𝐷; 𝐷1 = 1 − 𝐷 ; 300
𝑇 = 0.5/𝑓𝑠𝑤
𝑩𝟏 = 𝑩𝟒 200
100
0
𝑨𝟏 𝑩𝟏 -100 𝑨𝟐 𝑩𝟐
𝑑𝑖𝐿 −1 1 𝑑𝑖𝐿-200 −1 1
0 − -300 0 −
𝑑𝑡 𝑛𝐿 𝐿 1 𝑑𝑡 𝑛𝐿 𝐿 1
1 −1 𝑖𝐿 1 0.02290039
−1 𝑖𝐿0.02291016
−
𝑑𝑣𝑐 𝑑𝑣𝑐
= 0 𝑣𝑐 + 𝐿 𝑣𝑔 = 0 Time𝑣(s)𝑐 + 𝐿 𝑣
𝑔
𝑑𝑡 𝑛𝐶 𝑅𝐶 𝑣𝑐𝑟 0 𝑑𝑡 𝑛𝐶 𝑅𝐶 𝑣𝑐𝑟 0
𝑑𝑣𝑐𝑟 1 0 𝑑𝑣𝑐𝑟 1 0
0 0 0 0
𝑑𝑡 𝐶𝑟 𝑑𝑡 𝐶𝑟
𝑑𝑖𝐿 1 1 𝑑𝑖𝐿 1 1
0 − 0 −
𝑑𝑡 𝑛𝐿 𝐿 1 𝑑𝑡 𝑛𝐿 𝐿 1
−1 −1 𝑖𝐿 − −1 −1 𝑖𝐿
𝑑𝑣𝑐 𝐿 𝑣 𝑑𝑣𝑐
= 0 𝑣𝑐 + 𝑔 = 0 𝑣𝑐 + 𝐿 𝑣𝑔
𝑑𝑡 𝑛𝐶 𝑅𝐶 𝑣𝑐𝑟 0 𝑑𝑡 𝑛𝐶 𝑅𝐶 𝑣𝑐𝑟 0
𝑑𝑣𝑐𝑟 1 0 𝑑𝑣𝑐𝑟 1 0
0 0 0 0
𝑑𝑡 𝐶𝑟 𝑑𝑡 𝐶𝑟
𝑨𝟑 𝑩𝟑 𝑨𝟒 𝑩𝟒
Resonant DAB discrete model
• When the switching (sampling) frequency is changed, the resonance

appear at different frequency
• Same pattern than in

continuous model
with frequency
modulation
• Probably, same reason
Resonant DAB discrete model
• Comparison with simulation when switching frequency changes
fsw=80KHz fsw=100KHz fsw=110KHz fsw=90KHz

60
40
20
-20
fsw=80KHz fsw=100KHz fsw=110KHz fsw=90KHz
200
150
100
50
0
-50
-100
-150
100 1000 10000 100000
GSEP http://gsep.uc3m.es Frequency (Hz)

Model validation with PSIM
• Parasitics have been

considered (Rdson and
winding ESR)
• No dead time has been
considered
𝑓𝑝𝑒𝑎𝑘 = 𝑓𝑠𝑤 - 𝑓𝑜
Remarkable matching
Dead time effect: simulation
• When dead time is

considered, resonance
peak reaches a lower
magnitude
• The influence on the
phase can be neglected
GSEP http://gsep.uc3m.es 171

Lab test
Ii n
4
2
0
-2
Icarga
6
4
2
0
-2
-4
I(Lr)
4
0
-4
0.00525 0.005275 0.0053 0.005325 0.00535

T i me (s)
Steady state operation is validated

Lab test: change on swtiching frequency
When the switching

frequency changes 10
KHz, the resonance
peak changes in the
same amount

Lab test: change on dead time
Dead time
value affects
the magnitude
of the
resonance
peak, but not
the phase

Lab test: model vs. Measurement (transfer function)
Model and
meaurements match
in phase, and in
magnitude there are
some difference
probably due to the
dead time
consideration

DABSRC discrete model: summary
• The presented procedure provides a discrete ime

𝐺𝑖𝑑 ≜
𝑢ො 𝑧
model for the DABSRC converter, taking into ෝ
𝒙(𝑧) = 𝑧 · 𝑰 − 𝜱 −1
𝜸 · 𝑢(𝑧)
ො =
𝑣ො𝑜 𝑧
· 𝑢(𝑧)
ො
𝐺𝑣𝑑 ≜
𝑢ො 𝑧
account parasitic elements.
• The discrete time model predicts the behabiour

of the converter in the whole frequency range,
including the resonance peak appearing at a
frequency difference between the switching and
tank resonance frequencies.
• Dead time has to be considered to provide a

more accurate model, since it affects the
magnitude of the resonance peak

DAB discrete model. Conclusions
Discrete model procedure generates directly the transfer function in the z

domain.
▪ Suitable for design compensator in the z domain
▪ No small alias is needed
▪ Delays are inherently modeled
Additional elements can be included

▪ The procedure is the same
▪ Parasitics or other elements interfacing the bridges can be modeled
Resonant DAB can be modeled using this technique

▪ Resonance due to interaction between the perturbation signal and the
resonance tank can be predicted
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
Methodology to design a digital compensator
CONTINUOUS MODEL OF THE PLANT DISCRETE MODEL OF THE PLANT
2
CONTINUOUS COMPENSATOR
3
1
DISCRETE COMPENSATOR
Paths 2 and 3 are desirable
When discretizing the analog compensator…
>> Type-3 analog regulator
2
𝑠 H =
2 · 𝜋 · 𝑓𝑖 1+
2 · 𝜋 · 𝑓𝑧
𝐻 𝑠 = · 2
𝑠 𝑠 7.286e-06 s^2 + 0.3217 s + 3551
1+
2 · 𝜋 · 𝑓𝑝 ---------------------------------
1.508e-11 s^3 + 7.766e-06 s^2 + s
Continuous-time transfer function.
>> Zero order hold discretization ZOH:

Hz = Phase loss
0.6148 z^2 - 0.9129 z + 0.3284
-------------------------------------
z^3 - 1.152 z^2 + 0.1581 z - 0.005797
Sample time: 1e-05 seconds
>> Tustin with prewarping (cross-over frequency)

Hzp =
0.5692 z^3 - 0.3429 z^2 - 0.5467 z + 0.3654

-------------------------------------------
z^3 - 0.7485 z^2 - 0.2357 z - 0.01581
Sample time: 1e-05 seconds Tustin:

Higher order
Compensator calculation procedure
Digital Pulse
Width Power converter
Output voltage Discrete Time
Modulator control to output
reference Error signal Compensator delay
DPWM Duty cycle (plant) Output
vref + e d Voltage
C(ω) e -jω ·τ del ay
GDPWM0 Gvd(ω)
- vo
C(z) z=ejωt
GADC0 GS(ω)
A/D converter Sensor

static gain
Uncompensated loop gain 𝑇𝑈 𝜔 = 𝐺𝑃𝑊𝑀0 · 𝑒 −𝑗𝜔·𝜏𝑑𝑒𝑙𝑎𝑦 𝐺𝐴𝐷𝐶0 𝐺𝑣𝑑 𝜔 𝐺𝑆 𝜔
Loop gain (compensated) 𝑇 𝜔 = 𝑇𝑈 𝜔 𝐶 𝜔
Compensator is calculated from que cross-over frequency an phase margin

specification
Cross over frequency condition 𝑇𝑈 𝜔 · 𝐶 𝑒 𝑗𝜔𝜏 = 1 = 0 𝑑𝐵 𝑖𝑓 𝜔 = 𝜔𝑐 = 2𝜋 · 𝑓𝑐
Phase margin condition

𝑎𝑟𝑔 𝑇𝑈 𝜔𝑐 · 𝐶 𝑒 𝑗𝜔𝑐 𝜏 = −𝜋 + 𝑃𝑀
Discrete PI
PI
Transfer 𝑑 𝑧 𝑧 − 𝑒 −2𝜋·𝑓𝑧 ·𝜏 𝑧 − 𝑟𝑧 1 − 𝑟𝑧 𝑧 −1
𝐶𝑃𝐼 𝑧 = =𝐾 =𝐾 =𝐾
function 𝑒(𝑧) 𝑧−1 𝑧−1 1 − 𝑧 −1
Difference 𝑑 𝑛 = 𝑑 𝑛 − 1 + 𝐾 · 𝑒 𝑛 − 𝐾 · 𝑟𝑧 · 𝑒[𝑛 − 1]
equation
sin 𝜔𝑐 𝜏
𝑟𝑧 = cos 𝜔𝑐 𝜏 −
Zero location sin 𝜔𝑐 𝜏
tan 𝑃𝑀 − 𝜋 − 𝑎𝑟𝑔 𝑇𝑈 𝑗𝜔𝑐 + atan
cos 𝜔𝑐 𝜏 − 1
Discrete PID
PID
𝑑 𝑧 𝑧 − 𝑟𝑧1 𝑧 − 𝑟𝑧2 1 − 𝑟𝑧1 𝑧 −1 1 − 𝑟𝑧2 𝑧 −1

𝐶𝑃𝐼𝐷2 𝑧 = =𝐾 = 𝐾
𝑒(𝑧) 𝑧−1 𝑧 1 − 𝑧 −1
Transfer
function 𝑟𝑧1 = 𝑒 −2𝜋𝑓𝑧1𝜏 𝑟𝑧2 = 𝑒 −2𝜋𝑓𝑧2𝜏
Difference 𝑑 𝑛 = 𝑑 𝑛 − 1 + 𝐾 · 𝑒 𝑛 − 𝐾 𝑟𝑧1 + 𝑟𝑧2 · 𝑒 𝑛 − 1 + 𝐾(𝑟𝑧1 · 𝑟𝑧2 ) · 𝑒[𝑛 − 2]

equation
sin 𝜔𝑐 𝜏
𝑟𝑧 = cos 𝜔𝑐 𝜏 −
1 sin 𝜔𝑐 𝜏
tan 2 𝑃𝑀 − 𝜋 − 𝑎𝑟𝑔 𝑇𝑈 𝑗𝜔𝑐 + atan + 𝜔𝑐 𝜏
cos 𝜔𝑐 𝜏 − 1
Zero location
(𝑓𝑧1 = 𝑓𝑧2 ) 1
𝑟𝑧 = 𝑒 −2𝜋𝑓𝑧 𝜏 𝐾= 2
𝑒𝑗𝜔𝑐 ·𝜏−𝑒−2𝜋𝑓𝑧 𝜏
𝑇𝑈 𝜔𝑐
𝑒𝑗𝜔𝑐 𝜏 −1 · 𝑒𝑗𝜔𝑐 𝜏
Other ways to determine the relationship between fz1 and fz2 are possible
Compensator calculation procedure
Not all combinations of PM and fc are feasible
OK Unstable / Conditionally Stable Effective PM or fc different from spected
Performance Space
All feasible combinations of fc and PM are ploted in the fc,PM axis
Non feasible
specification are
identified
Performance Space
Additional constraint can be considered to assess the feasible solutions,

as limit cycle conditions depending on the compensator design
▪ Integral gain condition
▪ Gain margin condition
Performance Space
The performance space with the best solution can be identified

▪ Simpler solution are preferred (PI)
▪ Tie-break condition are based on trasnient response
Discrete PI parallel form
PI regulator, separated form can be realized as the addition of the three

terms (parallel realization)
𝐾𝑖 + 𝑑𝑖 𝑘
𝑧 −1
𝑒𝑘 𝑑𝑝 𝑘
𝐾𝑝 + 𝑑𝑘
𝑑 𝑧 𝑧 − 𝑟𝑧 1 − 𝑟𝑧 · 𝑧 −1
𝐻 𝑧 = =𝐾· =𝐾 𝐾𝑖 + 𝐾𝑝 = 𝐾
𝑒(𝑧) 𝑧−1 1 − 𝑧 −1
𝑑 𝑧 𝐾𝑖
𝐻 𝑧 = = −1
+ 𝐾𝑝 𝐾𝑝 = 𝐾 · 𝑟𝑧
𝑒(𝑧) 1 − 𝑧
“Digital Control of High-Frequency Switched Mode Power Converters” Corradini et al. Wiley 2015
PID forms
PID regulator, calculated with the frequency response approach (zero-gain form)
𝑑[𝑘] = 𝑑[𝑘 − 1] + 𝐾 · 𝑒[𝑘] − 𝐾 · 2 · 𝑟𝑧 · 𝑒[𝑘 − 1] + 𝐾 · 𝑟𝑧2 · 𝑒[𝑘 − 2]
𝑑 𝑧 𝑧 − 𝑟𝑧 2 1 − 𝑟𝑧 · 𝑧 −1 2
𝐻 𝑧 = =𝐾· =𝐾
𝑒(𝑧) 𝑧−1 ·𝑧 1 − 𝑧 −1
PID regulator, separated form (integral, proportional and derivative parts)

𝑑𝑖 𝑘 = 𝑑𝑖 𝑘 − 1 + 𝐾𝑖 · 𝑒[𝑘]
𝑑 𝑘 = 𝑑𝑖 𝑘 + 𝑑𝑝 𝑘 + 𝑑𝑑 [𝑘] 𝑑𝑝 𝑘 = 𝐾𝑝 · 𝑒[𝑘]
𝑑𝑑 𝑘 = 𝐾𝑑 · 𝑒 𝑘 + 𝑒([𝑘 − 1]
𝑑 𝑧 𝐾𝑖
𝐻 𝑧 = = −1
+ 𝐾𝑝 + 𝐾𝑑 · 1 − 𝑧 −1
𝑒(𝑧) 1 − 𝑧
𝐾𝑖 + 𝐾𝑝 + 𝐾𝑑 = 𝐾
𝐾𝑝 + 2 · 𝐾𝑑 = 2 · 𝐾 · 𝑟𝑧
𝐾𝑑 = 𝐾 · 𝑟𝑧2
Discrete PID parallel form
PID regulator, separated form can be realized as the addition of the three
terms (parallel realization)
𝐾𝑖 + 𝑑𝑖 𝑘
𝑧 −1
𝑒𝑘 𝑑𝑝 𝑘
𝐾𝑝 + 𝑑𝑘
+- 𝐾𝑑
𝑑𝑑 [𝑘]
𝑧 −1
Very suitable for implementation, lower rounding effects and easier

signal sizing
“Digital Control of High-Frequency Switched Mode Power Converters” Corradini et al. Wiley 2015
Design verification: cosimulation
VHDL impementation can be cosimulated with PSIM-Modelsim
Cosimulation results
Power stage response is obtained in PSIM

▪ Example: DAB PS in closed loop controlled with a PI compensator
Vout
175
150
125
100
75
50
25
0
V36
40
38
36
34
32
30
0 0.005 0.01 0.015 0.02

Time (s)
Cosimulation results
Control stage response is obtained in ModelSim

▪ All internal signals can be monitored
▪ Debbuging is possible
Effect of the quantization in the limit cycling
• Modulator quantization step: it determines the quantization step in

the controlled quantity (e.g. phase shift)
• ADC quantization step: it determines the maximum error in the
controlled quantity which is not reduced by the system
• Problem: high ADC resolution and low modulator resolution. The
system can see a larger error that is able to reduce, producing
oscillations (limit cycling)
DC-DC
Converter
ADC
Modulator Digital compensator
dn=b0en+…+
a1dn-1+… FPGA
DSP
Limit cycling example
Buck converter in closed loop. Small reference steps are applied
Average output voltage equals the reference,

but low frequency oscillations appear
Example: unlimited ADC resolution (i)
Example: unlimited ADC resolution and limited DPWM resolution (system

with integrator)
The systems oscillates to reach the desired average value of the
controlled quantity
Due to quantization, the Possible values of the
nearest possible values of Output voltage output voltage in
d
“d” are steady state
0.5
0.375
0.25
The desired operating

0.125 point is achieved for Desired average value of the output voltage
this specific value of
“d”
001 010 011 100 Possible values of the duty cycle t
Condition 1: quantization steps
At least one possible value of the output voltage must be in every

quantization interval of the ADC
d·Gvd_0
Desired operating point (reference) ADC error (vo-vref)
5.05 Error=+1 LSB
5
𝐺𝐷𝐶 · 𝑞𝐷𝑃𝑊𝑀 Error=0 LSB 𝑞𝐴𝐷𝐶
4.95
4.90 Error=-1 LSB

Possible values
of the duty cycle
001 010 011 100
• 𝐺𝐷𝐶𝑐𝑜𝑛𝑣 · 𝐺𝐷𝐶𝑠𝑒𝑛𝑠𝑜𝑟 · 𝐺𝐷𝐶𝑚𝑜𝑑 = DC gain of the
Condition 1 power converter, sensing chain and modulator
• 𝑞𝐷𝑃𝑊𝑀 = DPWM quantization step
𝐺𝐷𝐶𝑐𝑜𝑛𝑣 · 𝐺𝐷𝐶𝑠𝑒𝑛𝑠𝑜𝑟 · 𝐺𝐷𝐶𝑚𝑜𝑑 · 𝑞𝐷𝑃𝑊𝑀 < 𝑞𝐴𝐷𝐶 • 𝑞𝐴𝐷𝐶 = ADC quantization step (including sensor
DC gain)
Example to illustrate limit cycling condition 1
Limit cycling due to condition 1
Possible values in the ADC
Reference
Possible values in the

output of the converter, in
same scale than the ADC
output
Reference is changing
between impossible values of
the output
System self-adjusts the

average output voltage to
the right value, but low
frequency oscillation occurs
Condition 2: regulator integral gain
The smallest error variation produces a correction as a function of the

regulator and compensator.
The condition is similar to condition 1 as it refers to steady state
Plant, sensor and modulator DC gain
Condition 2 Regulator integral gain
0 < 𝐺𝐷𝐶 · 𝐾𝐼 < 1
𝑏3 𝑧 3 + 𝑏2 𝑧 2 + 𝑏1 𝑧 + 𝑏0 σ 𝑏𝑖
𝐾𝐼 = lim 𝑧 − 1 𝐻 𝑧 = lim 𝑧 − 1 =
𝑧→1 𝑧→1 𝑎3 𝑧 3 + 𝑎2 𝑧 2 + 𝑎1 𝑧 + 𝑎0 σ 𝑛 · 𝑎𝑖
𝑎3 𝑧 3 + 𝑎2 𝑧 2 + 𝑎1 𝑧 + 𝑎0
= 𝑎3 𝑧 2 + 𝑎3 + 𝑎2 𝑧 + 𝑎3 + 𝑎2 + 𝑎1
𝑧−1
Other quantization dynamic effects
System quantizers (ADC y DPWM) introduce error modeled as

perturbations
System dynamics should avoid oscillations due to these perturbations
One of the dynamic conditions to avoid limit cycling refers to gain margin
Condition 3
Gain margin should be high enough 2

to compensate the gain introduced 4
𝐺𝑀 >
by DPWM and ADC quantization 𝜋
𝐺𝑀 > 4,2 𝑑𝐵 + 20 log(𝛼)
Summary of the limit cycling conditions
❑ C1 deals with resolution.

Condition 1
Solutions:
❑ Increasing of the effective
𝐺𝐷𝐶𝑐𝑜𝑛𝑣 · 𝐺𝐷𝐶𝑠𝑒𝑛𝑠𝑜𝑟 · 𝐺𝐷𝐶𝑚𝑜𝑑 · 𝑞𝐷𝑃𝑊𝑀 < 𝑞𝐴𝐷𝐶 DPWM
– Higher clock frequency
– Phase shifted clocks
Condition 2 – Ditthering
– SD modulators
0 < 𝐺𝐷𝐶𝑐𝑜𝑛𝑣 · 𝐺𝐷𝐶𝑠𝑒𝑛𝑠𝑜𝑟 · 𝐺𝐷𝐶𝑚𝑜𝑑 · 𝐾𝐼 < 1 ❑ Decreasing of ADC
resolution near the desired
value (dead zone)
Condition 3
𝐺𝑀 > 4,2 𝑑𝐵 + 20 log(𝛼)
C2&C4 deals with regulator
design. Solution: regulator
 = 0.5 Margin factor in the practice redesign
Example of Limit Cycles (C1) in a DAB converter
DAB converter operating in closed loop is simulated with different

quantization parameters
Transients are induced to change slightly the operation point
Limit cycles are observed once the system reaches the steady state
Interesting quantities: output voltage, phase shift and error
Example of Limit Cycles (C1) in a DAB converter
DAB converter operating in closed loop is simulated with different

quantization parameters
Transients are induced to change slightly the operation point
Limit cycles are observed once the system reaches the steady state
Interesting quantities: output voltage, phase shift and error
Control loop
Modulator
Example of Limit Cycles (C1)
Limit cycling condition 1 not met: poor PWM resolution (8 bits)
𝐺𝐷𝐶 · 𝐺𝐷𝐶𝑠𝑒𝑛𝑠𝑜𝑟 · 𝐺𝐷𝐶𝑚𝑜𝑑 · 𝑞𝐷 < 𝑞𝐴𝐷𝐶
𝑅·𝑇
𝑉𝑜 = 𝐼𝑜 · 𝑅 = 𝑉𝑔 ·𝐷· 1−𝐷
𝜕𝑉𝑜 𝑅·𝑇 𝑉𝑜 1 − 2𝐷
𝐺𝐷𝐶 = = 𝑉𝑔 · 1 − 2𝐷 =
𝜕𝐷 𝑛 · 𝐿𝑙𝑘 𝐷 1−𝐷
1 − 2 · 0.2
𝐺𝐷𝐶 = 110 = 412.5
0.2 · 0.8
1 1 1
1 412.5 · · >
𝐺𝐷𝐶𝑚𝑜𝑑 = 1 𝐺𝐷𝐶𝑠𝑒𝑛𝑠𝑜𝑟 = 120 256 256
120
1 1
𝑞𝐷 = = Condition 1 is not met, limit cycling appear
2𝑁𝐷 256
2 2
𝑞𝐴𝐷𝐶 = =
2𝑁𝐴𝐷𝐶 512
1.ii Limit cycling
Limit cycling is not avoided
Vsense0 Vref0
1.2
1
0.8
0.6
0.4
0.2
0
Vdm
0.4
0.3
0.2
0.1
Verror0
1
0.8
0.6
0.4
0.2
0
-0.2
0 0.005 0.01 0.015 0.02

Time (s)
1.ii Limit cycling
Limit cycling condition 1 is met: high resolution modulator
𝐺𝐷𝐶 · 𝐺𝐷𝐶𝑠𝑒𝑛𝑠𝑜𝑟 · 𝑞𝐷 < 𝑞𝐴𝐷𝐶
𝑅·𝑇
𝑉𝑜 = 𝐼𝑜 · 𝑅 = 𝑉𝑔 ·𝐷· 1−𝐷
𝜕𝑉𝑜 𝑅·𝑇 𝑉𝑜 1 − 2𝐷
𝐺𝐷𝐶 = = 𝑉𝑔 · 1 − 2𝐷 =
𝜕𝐷 𝑛 · 𝐿𝑙𝑘 𝐷 1−𝐷
1 − 2 · 0.2
𝐺𝐷𝐶 = 110 = 412.5
0.2 · 0.8
1 1 1
1 412.5 · · <
𝐺𝐷𝐶𝑠𝑒𝑛𝑠𝑜𝑟 = 120 1024 256
120
1 1 Condition 1 is met, limit cycling appear
𝑞𝐷 = =
2𝑁𝐷 1024
2 2
𝑞𝐴𝐷𝐶 = = = 3.9𝑚𝑉
2𝑁𝐴𝐷𝐶 512
When the output voltage produces a 0 error, the duty cycle does not oscillate
Different example: buck converter in closed loop

PID compensator with high cross over frequency: high integral gain
Simulation without amplitude quantization
System corrections are fast due to the compensator
As there is no effective amplitude quantization, there are no limit cycle
Duty cycle signal is constant after the transient
Quantization blocks are added. Condition 2 is not met
0 < 𝐺𝐷𝐶 · 𝐾𝐼 < 1
15 29
· · 553.145 − 966.51 + 422.195 = 6.622
10 210
𝐺𝐷𝐶𝑐𝑜𝑛𝑣 =15
𝐺𝐷𝐶𝐴𝐷𝐶 = 2𝑁𝐴𝐷𝐶
𝐺𝐷𝐶𝑚𝑜𝑑 = 1/2𝑁𝑃𝑊𝑀 𝐺𝐷𝐶𝑠𝑒𝑛𝑠𝑜𝑟 =1/10
Condition 2 is not met. Limit cycling are appears

ADC and DPWM meet the condition 1
Compensator is redesigned in order to achieve a different integral gain,

by selecting a lower cross-over frequency
Design 2 (lower integral gain)
Original design
1.ii Limit cycling
Compensator is redesigned in order to achieve a different integral gain, by

selecting a lower cross-over frequency
0 < 𝐺𝐷𝐶 · 𝐾𝐼 < 1
29
15 · 10 · 90.4505 − 166.797 + 76.8962 = 0.412
2
❑Limit cycles dissapear
❑Quantization effects are visible during the transients
OUTLINE
2. Basics on ZVS
3. DAB design
2. DABSRC design
1. Fundamentals
Introduction
Modularization provides
+ Iin Iout +
DC
▪ Better performance: Vin Vout
- DC -
➢ use of lower voltages switches (lower losses), even
MOSFETs instead IGBT DC
➢ Smaller conversion ratios can improve efficiency DC
➢ Possibility of interleaving
DC
▪ Standardization of components (better DC
manufacturing)
+ 3·Iin Iout +
DC
▪ Possibility of a desired level of redundancy Vin/3 Vout
- DC -
…but there are some key points
DC
▪ Control of units in order to achieve power, voltage
DC
and current sharing, and warranty ZVS
DC
DC
Introduction
Exploring ISOP connection of DAB

converters
▪ Control strategy + Iin Iout +
DC
Vin Vout
▪ Systematic approach to design the - DC -
controller
DC
DC
DC
DC
DAB in ISOP connection
T1 T2 T5 T6
+ ESRL Lk1
1 n1 +
vi1 C Rvo
Ci
ISOP connection DAB converter -
-
• Same input current 𝑇·𝐷1 · 1−𝐷1 T3 T4 T7 T8
• Same output voltage 𝐼𝑖 = 𝑉𝑜 · 𝑛·𝐿𝑘1
T1b T2b T5b T6b
+ ESRL Lk2
1 n2
vi2
Vi Ci
-
Ideally the ratio input current/output

T3b T4b T7b T8b
voltage of each module must be the
same
𝑇·𝐷1 · 1−𝐷1 𝑇·𝐷2 · 1−𝐷2 𝑇·𝐷3 · 1−𝐷3
= = T5c
𝑛1 𝐿𝑘1 𝑛2 𝐿𝑘2 𝑛3 𝐿𝑘3 T1c T2c T6c
ESRL Lk3
+ 1 n3
vi3 Ci
-
T3c T4c T7c T8c
DAB in ISOP connection
T1 T2 T5 T6
+ ESRL Lk1
1 n1 +
vi1 C Rvo
Ci
ISOP connection DAB converter -
-
• Same input current 𝑇·𝐷1 · 1−𝐷1 T3 T4 T7 T8
• Same output voltage 𝐼𝑖 = 𝑉𝑜 · 𝑛·𝐿𝑘1
T1b T2b T5b T6b
+ ESRL Lk2
1 n2
vi2
Vi Ci
-
Ideally the ratio input current/output

T3b T4b T7b T8b
voltage of each module must be the
same
𝑇·𝐷1 · 1−𝐷1 𝑇·𝐷2 · 1−𝐷2 𝑇·𝐷3 · 1−𝐷3
= = T5c
𝑛1 𝐿𝑘1 𝑛2 𝐿𝑘2 𝑛3 𝐿𝑘3 T1c T2c T6c
ESRL Lk3
+ 1 n3
vi3 Ci
Actual converters: input voltage distribution -
𝑇·𝐷1 · 1−𝐷1
can be very sensitive to 𝐿𝑘1
T3c T4c T7c T8c
Distribution of input voltage in actual prototype
D1=0.2 D1=0.21 D1=0.2

D2=0.2 D2=0.2 D2=0.206
D3=0.2 D3=0.2 D3=0.2
V1 V3 V2norm V1norm V2norm V1norm V2norm V1norm

V3norm V3norm V3norm
=0.2
1,25 1,25 1,25
D1=D2=D3=0.2 D2=D3=0.2 D1=D3=0.2
1,2 1,2 1,2
D1=0,21 D2=0,206
Norm.Input voltages (V)

1,15 1,15 1,15
1,1 1,1 1,1
1,05 1,05 1,05
1 1 1
0,95 0,95 0,95
0,9 0,9 0,9
0,85 0,85 0,85
0,8 0,8 0,8
0,75 0,75 0,75
100 0 50 100 0 50 100 0 50 100
ltage (V) Total Input voltage (V) Total Input voltage (V) Total Input voltage (V)
(b) (c) (d)
Distribution of input voltage in actual prototype
Input voltage mismatch=1,01%

I(L1) I(L2) I(L3) Vin1 Vin2 VP25
3 Inductance mismatch=0,16%
2
iLk1
1
iLk3
0 iLk2
-1
-2
-3 Input voltage mismatch=10%

I(L1)_(DAB_PZ_3Modulos) I(L2)_(DAB_PZ_3Modulos)
Inductance mismatch=1,6% I(L3)_(DAB_PZ_3Modulos) Vin1_(DAB_PZ_3Modulos) Vin2_(DA
3
2
iLk3
iLk2 iLk1
1
-1
-2 Loss of
ZVS
-3
0.008636 0.00864 0.008644
Time (s)
Control approach
Goal
▪ Keeping an almost uniform input voltage distribution among modules
Strategy
▪ Small signal modeling of DAB ISOP
▪ Analysis of model and loops proposal
Small signal model of DAB
T1 T2 T5 T6
ESRL Lk iL1 n +
+ + VL - C R
Vo
Vi Vp + -
- Vs
-
T3 T4 T7 T8
+ 𝑖෡𝑜 = 𝑔𝑜𝑑 · 𝑑መ + 𝑔𝑜𝑣𝑖 · 𝑣ෝ𝑖

+ ii io
vi - C R vo 𝑖෡𝑖 = 𝑔𝑖𝑑 · 𝑑መ + 𝑔𝑖𝑣𝑜 · 𝑣
ෞ𝑜
-
Small signal model of ISOP DAB
T1 T2 T5 T6
ii io
+ ESRL Lk1
1 n1
+
vi1 C R ic1
- Ci + ii1 io1 C R vo
Ci vi1
T3 T4 T7 T8 -
-
ic2
+ io2
vi + ii2
- Ci vi2
-
T1b T2b T5b T6b
+ ESRL Lk2 ic3

1 n2
vi2 + io3
Ci ii3
Vi - Ci vi3
-
T3b T4b T7b T8b
T1c T2c T5c T6c

ESRL Lk3
+ 1 n3
vi3 Ci
-
T3c T4c T7c T8c
Output voltage
vo/d1 (model)
50
𝑖෢ ෡
Magnitude (dB)
𝑜 𝑗 = 𝑔𝑜𝑑 · 𝑑𝑗 + 𝑔𝑜𝑣𝑖 · 𝑣
ෞ𝑖𝑗 40
30
𝑖෢ መ
𝑖 𝑗 = 𝑔𝑖𝑑 · 𝑑𝑗 + 𝑔𝑖𝑣𝑜 · 𝑣
ෞ𝑜 20
ii io 10
ic1 + + 0
ii1 io1 vo 10 100 1000 10000
Ci vi1 C R frequency (Hz)
-
-
ic2 vo/d1 (model)
+
vi +
- Ci vi2 ii2 io2 0
10 100 1000 10000
-
-50
Phase (deg)
ic3 -100
+
vi3 ii3 io3
Ci -150
-
-200
frequency (Hz)
𝑅
𝑣ො𝑜 = · 𝑔𝑜𝑑 · 𝑑መ1 + 𝑑መ 2 + 𝑑መ 3 + 𝑔𝑜𝑣𝑖 · 𝑣ො𝑖1 + 𝑣ො𝑖2 + 𝑣ො𝑖3
𝑅𝐶𝑠 + 1
Input voltage of each module
𝑖෢ ෡
𝑜 𝑗 = 𝑔𝑜𝑑 · 𝑑𝑗 + 𝑔𝑜𝑣𝑖 · 𝑣
ෞ𝑖𝑗
60
50 vin1/d2 (model) vin2/d2 (model)
𝑖෢ መ
𝑖 𝑗 = 𝑔𝑖𝑑 · 𝑑𝑗 + 𝑔𝑖𝑣𝑜 · 𝑣
ෞ𝑜 40
Magnitude (dB)
30
ii io 20
ic1 + + 10
ii1 io1 vo 0
Ci vi1 C R -10
-
- -20
-30
ic2 10 100 1000
frequency (Hz)
10000
+
vi +
- Ci vi2 ii2 io2 150
- 100
50
ic3
+ 0
ii3 io3
Phase (deg)
Ci vi3 -50
- -100
-150
1 1 𝑔𝑖𝑑
𝑣ො𝑖1 = · · 𝑔 · 𝑑መ1 + 𝑑መ 2 + 𝑑መ 3 − 𝑔𝑖𝑑 · 𝑑መ1 = · −2 · 𝑑መ1 + 𝑑መ 2 + 𝑑መ 3
𝐶𝑖 𝑠 3 𝑖𝑑 3 · 𝐶𝑖 𝑠 -200
-250 vin1/d2 (model) vin2/d2 (model)
-300
10 100 1000 10000
frequency (Hz)
Small signal model of DAB ISOP
d1 vi1 Three control variables:

d1, d2 and d3
DAB
d2 vi2
ISOP
d3 vo Three controlled quantities:
vo, vi1 and vi2
𝑔𝑖𝑑
𝐴 𝑠 =
3𝐶𝑖 . 𝑠
d1 vi1
𝑣ො𝑖1 −2𝐴 𝑠 𝐴 𝑠 𝐴 𝑠 𝑑መ1
DAB
d2 vi2 𝑣ො𝑖2 = 𝐴 𝑠 −2𝐴 𝑠 𝐴 𝑠 𝑑መ 2
ISOP 𝑣ො𝑜 𝐺𝑣𝑑 𝑠 𝐺𝑣𝑑 𝑠 𝐺𝑣𝑑 𝑠 𝑑መ 3
d3 vo
H(s)
𝑅
𝐺𝑣𝑑 (𝑠) = ·𝑔
𝑅𝐶𝑠 + 1 𝑜𝑑
Each controlled quantity depends on the three control variables at the

same time
How can we calculate compensator and study stability?
d1 vi1
DAB 𝑣ො𝑖2 = 𝐴 𝑠 −2𝐴 𝑠 𝐴 𝑠 𝑑መ 2
d2 vi2
d3 vo
H(s)
With a matrix H(s) diagonal…
𝑣ො𝑖1 𝐻1 𝑠 0 0 𝑑መ1
𝑣ො𝑖2 = 0 𝐻2 𝑠 0 𝑑መ 2
𝑣ො𝑜 0 0 𝐻3 𝑠 𝑑መ 3
… the system will be much easier to calculate: three SISO systems….but it

isn’t
d1 vi1
d2 vi2
d3 vo
H(s)
Strategy : decompose H(s) as the product of a diagonal matrix D(s) and
another one Y(s).
3𝐴(𝑠) 0 0
𝐻 𝑠 =𝐷 𝑠 ·𝑌 𝑠 = 0 3𝐴(𝑠) 0 · 𝑌(𝑠)
0 0 3𝐺𝑣𝑑(𝑠)
Matrix D(s) is proposed by observation of H(s).
Decoupling control loops
d1 vi1
d2 vi2
d3 vo
H(s)
Strategy “change of variable”: the control variable are not d1, d2, d3, but a
new ones called x1, x2 and x3.
𝑑መ1 𝑥ො1
𝑌(𝑠) 𝑑መ 2 = 𝑥ො2
𝑑መ 3 𝑥ො3
𝑣ො𝑖1 𝑑መ1 𝑑መ1 𝑥ො1

𝑣ො𝑖2 = 𝐻 𝑠 𝑑መ 2 = 𝐷 𝑠 · 𝑌 𝑠 𝑑መ 2 = 𝐷 𝑠 · 𝑥ො2
𝑣ො𝑜 𝑑መ 3 𝑑መ 3 𝑥ො3
Decoupling control loops
x1 vi1
DAB 𝑣ො𝑖1 3𝐴(𝑠) 0 0 𝑥ො1
x2 ISOP vi2 𝑣ො𝑖2 = 0 3𝐴(𝑠) 0 𝑥ො2
𝑣ො𝑜 0 0 3𝐺𝑣𝑑(𝑠) 𝑥ො3
(modified)
x3 vo
Result: the MIMO system with

3·A(s) coupled transfer functions has been
x1 vi1
transformed into 3 SISO systems
x2 3·A(s) vi2
Compensators can be calculated
x3 3·Gvd(s) vo easily
Calculation of compensators
vi/3 Compensators are

C1(s) 3·A(s) vi1 calculated with this block
x1
diagram using standard
techniques…
vi/3
C1(s) 3·A(s) vi2 …but x1, x2 and x3 are not
x2
the control signals to
apply to the actual
vo_ref modules
C3(s) 3·Gvd(s) vo
x3
We need to recover d1, d2
and d3
Recovering original control signals
2 1 1
− 𝑑መ1
3 3 3 𝑥ො1 −1 0 1 𝑥ො1
1 2 1
𝑌(𝑠) = 𝐷 𝑠 −1
·𝐻 𝑠 = −3 𝑑መ 2 = 𝑌 𝑠 −1 𝑥ො2 = 0 −1 1 𝑥ො2
3 3
1 1 1 𝑑መ 3 𝑥ො3 1 1 1 𝑥ො3
3 3 3
-
Very simple operations to recover d1, x1
d2 and d3 are needed +
d1
-
The control variables x1, x2 and x3 are x2 d2
+
linear combinations of d1, d2 and d3
+ d3
+
+
x3
Final control scheme
vi/3 d1
C1(s) -
x1
+
vi1
vi/3
C1(s) - DAB
x2 vi2
+ d2 ISOP
+ vo
vo_ref +
C3(s) +
x3 d3
Final control scheme

- Compensators for input voltage loop have the same transfer function
- Generation of d1, d2 and d3 is easy (only additions)
Application example
Analog
3 DAB converter
ADC
ISOP
3X8 Driving signals Converted

data
VHDL controller
Digital
Applicability of the proposed method
60 vin1/d2 (measured) vin1/d2 (model)
50 vin2/d2 (measured) vin2/d2 (model)
vin3/d2 (measured)
40
vo/d1 (measured) vo/d1 (model)
Magnitude (dB)
30
60 20
Magnitude (dB)
50
10
40
0
30
-10
20
10 -20
0 -30
10 100 1000 10000 10 100 1000 10000
frequency (Hz)
frequency (Hz)
200
vo/d1 (measured) vo/d1 (model) 150
0 100
10 100 1000 10000 50
-50
Phase (deg)
Phase (deg)
-100
-50
-150
-100
-200 -150
-250 -200 vin1/d2 (measured) vin1/d2 (model)

frequency (Hz) vin2/d2 (measured) vin2/d2 (model)
-250
vin3/d2 (measured)
-300
10 100 1000 10000
frequency (Hz)
Experimental measurements. Input Volt. distribution
Analog
Analog 3 DAB
3 DAB converter ADC
converter ISOP
ISOP
3X8 Driving signals
3X8 Driving signals
VHDL
VHDL controller
controller
Digital
Digital
Experimental measurements. Input Volt. distribution
Conclusions
• ISOP of DAB converters has been explored

▪ Input voltages should be controlled to ensure a
proper operation
▪ DAB ISOP is a MIMO systems: control loops are
coupled
• Decoupling control loops allows the calculation of

compensators using standard techniques
• Digital controller has been designed and validated
in a lab prototype
Very very reduced bibliography
[1] A. Rodríguez, A. Vázquez, D. G. Lamar, M. M. Hernando, and J. Sebastián, “Different Purpose Design
Strategies and Techniques to Improve the Performance of a Dual Active Bridge With Phase-Shift
Control,” IEEE Trans. Power Electron., vol. 30, no. 2, pp. 790–804, 2015
[2] C. Calderon et al., “General Analysis of Switching Modes in a Dual Active Bridge with Triple Phase
Shift Modulation,” Energies , vol. 11, no. 9. 2018.
[3] F. Krismer and J. W. Kolar, “Closed Form Solution for Minimum Conduction Loss Modulation of DAB
Converters,” IEEE Trans. Power Electron., vol. 27, no. 1, pp. 174–188, 2012.
[4] F. Krismer and J. W. Kolar, “Accurate Small-Signal Model for the Digital Control of an Automotive
Bidirectional Dual Active Bridge,” IEEE Trans. Power Electron., vol. 24, no. 12, pp. 2756–2768, 2009.
[5] L. Corradini, D. Seltzer, D. Bloomquist, R. Zane, D. Maksimović, and B. Jacobson, “Minimum Current
Operation of Bidirectional Dual-Bridge Series Resonant DC/DC Converters,” IEEE Trans. Power
Electron., vol. 27, no. 7, pp. 3266–3276, 2012.
[6] P. Zumel et al., “Modular Dual-Active Bridge Converter Architecture,” IEEE Trans. Ind. Appl., vol. 52,
no. 3, 2016.
[7] F. Krismer, “Modeling and optimization of bidirectional dual active bridge DC-DC converter
topologies,” ETH, 2010.
[8] A. Rodriguez Alonso, “Analisis de arquitecturas multipuerto para la alimentacion de sistemas electronicos con
multiples flujos de energia,” Universidad de Oviedo, 2013.
[9] Daniel Seltzer, “Modeling and Control of the Dual Active Bridge Series Resonant Converter” University of Colorado
Boulder, 2014.
Se han realizado cambios en las siguientes transparencias:
• 121: aumento de rz en ecuación en diferencias
• 29: aumento de 2 en ecuación de Potencia, y cambio de formato en
tabla
• 21: cambio de “d” por “D” en la ecuación
• 46: intercambio de “Mmin” y “Mmax”
• 59,61,63,64,65,66: aumento de “(rad)” en el eje horizontal
• 62: cambio en ecuación de 𝑄+ por 𝑄
• 68: aumento de R en ecuación de Vo y en k se ha eliminado Vg
• 69,70 : aumento de fondo amarillo en zona de zvs
• 97: aumento de 𝑣ො 𝑜1 en el primer circuito
• 142 phi expression
Nuevas diapositivas segunda parte:
- 126
- 137, 138
- 145, 146, 147,148
- 162-164
- 194-215
- Se ha eliminado al antigua 161

Modeling The DAB Converter - V10

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The Dual Active Bridge Converter

• Two active bridges operating with

 High number of components, including a transformer

0.0099 0.00990625 0.0099125 0.00991875 Circuir for 𝑖𝑙𝑘 calculation

S1,S4 S2,S3 S5,S8 S6,S7 iin io

U C 3 M The DAB converter 8

• Perfect efficiency is assumed

• Power in source V2 is due only to current produced by

• Output voltage (resistive load, 𝑉𝐿 = 0) S1 S2 S5 S6 +

If the load is a voltage source:

• Symmetric behavior around D=0.5

Inductor current D=0.25; M=0.2,0.4,…,2; constant Vg

0.09997 0.099975 0.09998 0.099985 0.09999 0.099995 0.1

Inductor current M=1, M=0,5; D=0.05,0.1,…,0.5; constant Vg

0.09950625 0.0995125 0.09951875 0.099525 0.09953125

0.09997 0.099975 0.09998 0.099985 0.09999 0.099995 0.1

Slopes change with D StaticCharacteristic_3.psimsch

100 100 100

GSEP http://gsep.uc3m.es StaticCharacteristic_4.psimsch

U C 3 M The DAB converter 17

Operating area for 1<M<2

U C 3 M The DAB converter 18

• The output average current depends only on the input voltage

• The input average current depends only on the output voltage

• Swtiching losses have to be minimized

TURN-ON Losses TURN-OFF Losses

- 100 -0.5 Diode forward

• In the practice it can be observed if 1

0.005 0.0055 0.006 0.0065

Synchronous Buck converter

Synchronous Buck converter

Soft Diode Soft Diode

Diode voltage drop

HS-switch turn on: LS-switch turn on:

VA2 VB2 VA2 VB2

Ilk Vlk/5 ZVS conditions:

𝐷=0 Normalized average

0.009925 0.0099275 0.00993 0.0099325 0.009925 0.0099275 0.00993 0.0099325

For each M value, d depends

𝜆𝑜 and 𝜆𝑖 are equivalent to reactive current percentages

𝜆𝑡𝑜𝑡𝑎𝑙 > 20%

Points obtained with values from

Curves generated with the lambda

n: calculated to have M=1 at nominal input voltaje

Reactive power: max lambda is chosen (input data)

Dmin: cross between ZVS boundary and Mmin

Dmax: cross between lambda curve and Mmax

Pmin: determined by Rmax, determines kmax

Pmax: determined by Rmin, determines kmin

*Based on “Análisis de arquitecturas multipuerto para la alimentación de sistemas electrónicos con

U C 3 M The DAB converter 46

ZVS is lost ZVS is lost

• When ZVS is lost the

Other modulation schemes are used to enlarge

Extended Phase Shift

• Lower RMS current for low power

- To calculate output quantities (𝑃𝑜 , 𝐼𝑜 ) 0.8

𝑇𝑠𝑤 1 + 𝐷1 -2 t2LH t2HL

U C 3 M The DAB converter 50

U C 3 M The DAB converter 52

U C 3 M The DAB converter 53

4 𝜋 − 𝜑𝐴𝐵 𝜋 𝜑𝐴𝐵 4 𝑉𝑜 𝜋 − 𝜑𝐷𝐶 𝜋 𝜑𝐷𝐶

1 𝜋 𝜑𝐷𝐶 𝜋 𝜑𝐴𝐵 𝜋 𝜋 𝜑𝐷𝐶 𝜑𝐴𝐵