HIGH VOLTAGE GAIN BUCK-BOOST DC-DC CONVERTER BASED ON

THREE-STATE SWITCHING CELL

Jefferson M. de Sousa1, George Harrison A. Bastos1, René P Torrico-Bascopé1, Cícero M.T. Cruz1
1
Federal University of Ceará, Department of Electrical Engineering, Fortaleza – Ceará, Brazil
e-mail: jeffersonmaia2121@gmail.com, ghdab@yahoo.com.br, rene@dee.ufc.br , cicero@dee.ufc.br

Abstract – This paper presents a generic and particular
topology of high voltage gain DC-DC Buck-Boost
converter based on Multi-State Switching Cell (MSSC).
To achieve the high voltage gain in the classic Buck-Boost
converter using MSSC, a secondary winding was added
converter, a generic single-phase version and its particular
single-phase version, shown in Fig. 2 (a) and (b),
respectively, are studied in this paper.
a

to the transformer and to its terminals are connected Multiphase

S1 S2 S3 Sn
controlled or non-controlled rectifiers in series. Adding + Autotransformer
Vi
rectifiers reduces the voltage stress across the switches, -
N

permitting the use of low on-resistance RDS(on) MOSFETs, N Main

L Cell
thereby improving the efficiency of the converter. In c N

order to check the operation principle, qualitative

analysis, quantitative analysis, design procedure, and N
experimental results from a prototype of output power Ro Co
+ S1' S2' S3' Sn'
Po = 1kW, input voltage Vi = 48V and output voltage Vo
= 400V are presented.
Multi-State Switching Cell-MSSC b

Keywords – High voltage gain DC-DC Buck-Boost (a)

a
converter, Three-state switching cell. S1 S2 S3 Sn
Multiphase
+ Transformer
I. INTRODUCTION Vi
-
Main
L Cell
Modern applications such as photovoltaic systems, fuel
cells systems, and small wind systems, have in its structure c

low voltages (12Vdc – 48Vdc) due to presence of back-up S1' S2' S3' Sn'
C1
batteries. These low voltages should be raised to (300 Vdc-
400 Vdc) to feed voltage source inverters, power LED b
reflectors, and others applications. For the later purpose, the
classical Boost or Buck-Boost converters are not a good Sa11 Sa12 Sa13 Sa1n
choice, because for a very high duty cycle, the output diode C2
conducts a very short time during each commutation cycle, Multiplier
thus resulting in serious reverse recovery problems and an Cell

increase of the output diode rating [1]. An alternative might

be the use of Boost or Buck-Boost converters in cascade, but Ro Co
+
C3 Sa11' Sa12' Sa13' Sa1n'
this solution deals with lower efficiency, due to the amount
of power processing stages. To overcome this disadvantage,
some solutions using step-up converters capable of operating
with high voltage gain ratio are proposed and analyzed in the
literature [2]-[7]. Saj1 Saj2 Saj3 Sajn

To make the current division through components, the C(j+2)

Multi-State Switching Cell (MSSC) has been an alternative Multiplier

widely used and studied in [8]-[13]. The MSSC applied to Cell

the Buck-Boost converter is shown in Fig. 1.(a), and its static

gain is similar to that presented by the conventional Buck- C(j+3) Saj1' Sai2´ Saj3´ Sajn´

Boost converter. With this behavior is not possible to achieve

a high voltage gain. To improve this characteristic, secondary j=number of multiplier cells
windings are added to the autotransformer and connected to (b)
its output rectifiers as shown in Fig. 1.(b). Both topologies Fig. 1. DC-DC Buck-Boost converter based on MSSC with: (a)
have bidirectional characteristic, such that they can be used limited voltage gain, and (b) high voltage gain.
in systems with energy regeneration, such as electric vehicles
(EVs). To understand the operating principle of the proposed

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 II. PROPOSED CONVERTER UNDER ANALISYS The particular topology shown in Figure 2.(b) is
composed by: input voltage source Vi; controlled switches
A. Generic and Particular Topologies S1 and S2; rectifier diodes D1-D4; high frequency
The DC-DC Buck-Boost converter based on Three-State transformer Tr with three-windings – Np1, Np2 and Ns1;
Switching Cell (TSSC) in its generic and particular versions storage inductor L; voltage multiplier capacitors C1-C3; DC
are shown in Fig. 2.(a) and (b), respectively. The main bus filter capacitor Co, and the equivalent load resistor Ro.
advantages of this circuit are: the inductor L operates with The capacitors C1-C3 should be of polyester or
twice the switching frequency, allowing weight and volume polypropylene type, because of their low series resistance
reduction; input current for charging the inductor L is and reduced losses. The electrolytic capacitor Co with high
divided between switches S1 and S2, reducing the capacitance is essential for the DC bus.
conduction losses. As drawbacks, the converter does not
operate appropriately for duty cycle (D) lower than 0.5 due B. Qualitative Analysis
to magnetic induction problems of the transformer Tr; and In order to perform the qualitative analysis of the
input current is continuous with small AC ripple. Despite the converter, the following assumptions are made: steady state
limitation of the duty cycle, the converter does not present operation, operation in continuous conduction mode (CCM),
faults during soft-start. duty cycle greater than 0.5, transformer magnetizing current
S1 S2 null and ideal semiconductors. The operation stages for one
Single-Phase
+ Transformer switching period and their corresponding waveforms are
Vi - L Np1 shown in Fig. 3 and Fig. 4, where Ts is the switching period
of the controlled switches.
Np2 First interval (to-t1): In this interval, switches S1 and S2
+ C1 S3 S4 are turned-on, and diodes D1, D2, D3 and D4 are reverse
biased. The energy provided by source Vi is stored in the
inductor L, and no energy transference occurs to the load.
Vo S5
The capacitors C1, C2, C3 and Co feed the load resistor Ro.
+ C2 The interval finishes when switch S2 is turned-off. The
Ro Co topological circuit of this interval is shown in Fig. 3.(a). The
Ns1
differential equation of the inductor current during this
interval is given by (1).
S6
C3
-
diL
Vi − L =0 (1)
dt
S(2j+3)
Second interval (t1-t2): The switch S1 remains turned-on
C(j+2)
Nsn
and the switch S2 remains turned-off. The diodes D2 and D3
are forward biased. On the other hand, the diodes D1 and D4
are reverse biased. The energy stored in the inductor L
C1 C(j+3)
S(2j+4)
during the previous interval is transferred to the load resistor
Ro and the capacitors C1, C2 and Co. This interval ends
j=number of multiplier cells
when switch S2 receives a gate signal. The topological
(a) circuit of this interval is shown in Fig. 3.(b). The differential
Ii iS1 iS2
equation of the inductor current during this interval is given
Single-Phase S1 + S2 +
Transformer vS1 vS2
by (2).
Vi +
- - vp1 + ip1 - -
L Np1
Io iL Vi ⎛ D ⎞ diL
- vL +
ip2
⎜1 − ⎟−L =0 (2)
Np2 2 ⎝ 1− D ⎠ dt
+
C1 D1 D2
Tr
Third interval (t2-t3): This interval is similar to the first
Vo iD1 iD2
interval, where switches S1 and S2 are turned-on, and diodes
D3
+ D1, D2, D3 and D4 are reverse biased. As in the first
Ro Co
-
C2 interval, the energy is stored in the inductor L only. The
Ns1 iD3
topological circuit of this interval is shown in Fig. 3.(c).
- vs1 +
is1 Fourth interval (t3-t4): The switch S2 remains turned-on,
C3 D4
and switch S1 remains turned-off. The diodes D1 and D4 are
-
forward biased, whereas D2 and D3 are reverse biased. The
iD4 energy stored in the inductor L during the previous interval is
(b) transferred to the load resistor Ro and to the capacitors C1,
Fig. 2. High voltage gain DC-DC Buck-Boost converter based on C3 and Co. The topological circuit of this interval is shown
TSSC: (a) generic topology; (b) particular topology. in Fig. 3.(d).

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 DTs
S1 S2
Single-Phase
+ vGS1 (D-0.5)Ts (1-D)Ts
Vi Transformer
- L Np1
vGS2 t
Np2
+ D1 iL t
C1 D2

Vo iP1 t
D3
+
Ro Co C2 iP2 t
Ns1

is1 t

- C3 D4
t
vS1
(a) First Interval. iS1 VS1
IS1
S1 S2
Single-Phase vS2 t
+ iS2 VS2 IS2
Vi Transformer
- L Np1
t
iD1
Np2
+ D1
C1 D2
t
iD2
Vo
t
D3 iD3
+
Ro Co C2
t
Ns1
iD4

t0 t1 t2 t3 t4 t
- C3 D4

Fig. 4. Theoretical waveforms of the proposed converter in CCM.

(b) Second Interval.
S1 S2 B. Static Gain of the Proposed Converter in CCM
Single-Phase
Vi + Transformer
In this section, the static gain (Gv) of the proposed
- L Np1 converter, which consists of the relationship between the
total output voltage and the input voltage as a function of the
Np2
+
D1 D2
duty cycle and the transformer turns ratio, (a), is presented.
C1
The total output voltage is composed by the sum of the
Vo voltages across the capacitors C1, C2 and C3, as shown in
+
D3
(3).
Ro Co C2
Ns1
Vo = VC1 + VC 2 + VC 3 (3)

- C3 D4
The voltage across the capacitor C1 is equal to output
voltage of the classic Buck-Boost converter, given by (4).
(c) Third Interval.
S1 S2 D
Single-Phase VC1 = Vi (4)
Vi +
- L
Transformer
Np1
(1 − D )

+
Np2 The voltage across capacitors C2 and C3 are equal and
C1 D1 D2
given by (5).
Vo
D3
N s (Vi + VC1 ) (V + V )
Ro Co
+
C2 VC 2 = VC 3 = = a i C1 (5)
Ns1 Np 2 2

- C3 D4 Substituting (4) and (5) in (3) and making some

mathematical manipulation, the static gain is given by (6).
(d) Fourth Interval.
Fig. 3. Operating intervals of the proposed converter in CCM. VO ( D + a )
GV = = (6)
Vi (1 − D )

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 The curves corresponding to (6), taking the transformer
turns ratio, (a), as a parameter are shown in Fig. 5. The maximum reverse voltage across the diodes D1 and
D2, without considering overshoot, is given by (12).

⎛ D ⎞
VD1( PIV ) = VD 2( PIV ) = Vi ⎜⎜ 1 + ⎟⎟ (12)
⎝ (1 − D ) ⎠

The maximum voltage across the rectifier diodes D3 and

D4, without considering overshoot, are given by (13).

a
VD 3( PIV ) = VD 4( PIV ) = Vi (13)
(1 − D )
IV. EXPERIMENTAL RESULTS
Fig. 5. Static gain curves for proposed converter in CCM.

III. THEORETICAL ANALISYS
In this section, considering the CCM operation of the
converter with a duty cycle greater than 0.5, the main
equations are presented as follows.
In order to verify the operation and evaluate the
performance of the proposed converter, a prototype with
specifications shown in Table I was assembled. The
components used in the prototype are listed in Table II. Fig.
6 shows a picture of the assembled prototype.

A. Inductor Design. TABLE I

Using (1) and the time interval during the first interval, the Design Specifications
Po= 1 kW: output power
inductance value for a current ripple on the inductor is equal
Vi=48 V: input voltage
to (7). Vo= 400 V: output voltage
fs=25 kHz : switching frequency
Vi ( 2 D − 1)
L= (7)
2 fs ΔI L TABLE II
Prototype Components
Inductor L L = 143µH; NL = 18 Turns
B. Capacitor Design. NEE-65/33/26 (Thornton)
Considering that the voltage ripple is small, the average δ = 1.83mm (gap)
voltage across the capacitors C1, C2, C3 and Co are given by Switches S1 and S2 IRFP 4768
(4), (5) and (6). The capacitance of each capacitor can be Diodes D1, D2, D3 and 30CTH03
D4
calculated using (8), (9) and (10) for a given limit of the
Filter Capacitors C1, C2 2x2.2μF/400V
voltage ripple across each capacitor (∆VC1, ∆VC2, ∆VC3, and C3
∆VCo), and average output current Io. DC Bus Filter Capacitor 470μF/450V
Co
High Frequency Np1 = Np2 = 16 Turns;
I o ( 2 D − 1) transformer Ns1=32
C1 ≥ (8) NEE - 65/33/26 (Thornton)
2 f s ΔVC1
For an output power of 600 W, several waveforms were
Io D obtained, and are descripted from top to bottom of each
C 2 = C3 ≥ (9) figure as follows.
f s ΔVC 2 Fig. 7 shows the gate-to-source voltages of switches S1
and S2, and current through inductor L. The inductor current
has low ripple with twice the switching frequency. Therefore,
I o ( 2 D − 1)
Co ≥ (10) to implement the control loop crossover, the frequencies
2 f s ΔVCo must be defined considering twice the switching frequency.
Fig. 8 presents the gate-to-source voltage of switches S1
and S2, drain-to-source voltage of switch S1, and current
C. Voltage Across Semiconductors.
through the transformer primary winding (Ip1). The
The maximum voltage across the switches S1 and S2,
maximum voltage across switches S1 and S2 is limited to
without considering overshoot, is given by (11).
170 V. Thus, the switches have less than half of the total
output voltage when turned-off.
⎛ D ⎞ Fig. 9 shows the gate-to-source voltages of switches S1
VS1max = VS 2 max = Vi ⎜⎜1 + ⎟⎟ (11)
⎝ (1 − D ) ⎠
and S2, and voltage and current in the transformer primary
winding (Vp1 and Ip1).

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 Fig. 10 shows voltage and current of the transformer
secondary winding (vs1 and is1). The experimental current
waveform is different to the theoretical waveform due to the
leakage inductance of the transformer.
Finally, Fig. 11 presents the efficiency of the converter as
a function of the output power.

Capacitor
Co Inductor

Transformer Tr
Input
Switches S1
Capacitors Fig. 9. Measured gate-to-source voltages vGS1 and vGS2, voltage
and S2
and current of the transformer primary winding vp1 and ip1
(CH1:20V/div.; CH2:20V/div.; CH3:10A/div.; CH4:50V/div.;
10µs/div.).

Fig. 6. Picture of the prototype.

Fig. 10. Measured voltage and current of the transformer secondary

Fig. 7. Measured gate-to-source voltages vGS1 and vGS2, and winding vs1 and is1. (CH3:5A/div.; CH4:10A/div.; 10µs/div.).
current through the inductor iL. (CH1:20V/div.; CH2:20V/div.;
CH3:5A/div.; 10µs/div.).

Fig. 8. Measured gate-to-source voltages vGS1 and vGS2, drain-to- Fig. 11. Efficiency of the converter as a function of the output
source voltage vS1, and primary current through transformer power
primary winding ip1. (CH1:20V/div.; CH2:20V/div.;
CH3:10A/div.; CH4:50V/div.; 10µs/div.)

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 IV. CONCLUSIONS
In this paper, a high voltage gain DC-DC Buck-Boost
converter based on TSSC was proposed. In order to develop
the topology, a secondary winding was coupled to the high
frequency transformer of the traditional TSSC, and a voltage
doubler rectifier was connected to its terminals. Qualitative
and quantitative analysis using the specifications and
considerations in Table I were carried out for the proposed
converter.
In a classic Buck-Boost converter, the maximum voltage
across the switch is equal to the sum of the input voltage and
the output voltage, whereas in the proposed converter with
high voltage gain, the maximum voltage across the switches
is lower than half of the total output voltage during turn-off.
This allows the use of low on-resistance RDS(on) MOSFETs,
and as consequence, the conduction losses (P = I2R) are
reduced, and the efficiency is improved. Another advantage
observed is the current sharing through the converter devices,
due to this fact, a larger power can be processed. The
drawbacks are the need to develop a symmetrical layout, and
provide symmetrical Pulse Width Modulation (PWM)
signals to avoid current unbalance through the devices; and
the duty cycle should be greater than 0.5. It is important to
clarify that lower values of the duty cycle do not cause any
failure in the semiconductors, the only limitation appears
when inducing voltage in the secondary winding of the
transformer, preventing the increase of the output voltage.
ACKNOLEDGEMENTS
The authors would like to thank the Energy Conditioners
Laboratory of the Department of Electrical Engineering of
the Federal University of Ceará.
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