energies

Article
Design and Implementation of a Control Method for
GaN-Based Totem-Pole Boost-Type PFC Rectifier in
Energy Storage Systems
Nguyen-Nghia Do 1, * , Bing-Siang Huang 1 , Nhat-Truong Phan 1 , Tan-Tung Nguyen 1 ,
Jian-Hong Wu 1 , Yu-Chen Liu 2 and Huang-Jen Chiu 1
1 Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology,
Taipei 10607, Taiwan; d10502205@mail.ntust.edu.tw (B.-S.H.); d10802808@mail.ntust.edu.tw (N.-T.P.);
nttung.ntust@gmail.com (T.-T.N.); applehong529@gmail.com (J.-H.W.); hjchiu@mail.ntust.edu.tw (H.-J.C.)
2 Department of Electrical Engineering, National ILAN University, Yilan 260, Taiwan; ycliu@niu.edu.tw
* Correspondence: dnnghiantust@gmail.com; Tel.: +886-978-447-395




Received: 29 September 2020; Accepted: 27 November 2020; Published: 29 November 2020


Abstract: With the unceasing advancement of wide-bandgap (WBG) semiconductor technology,

the minimal reverse-recovery charge Qrr and other more powerful natures of WBG transistors enable
totem-pole bridgeless power factor correction to become a dominant solution for energy storage
systems (ESS). This paper focuses on the design and implementation of a control structure for a
totem-pole boost PFC with newfangled enhancement-mode gallium nitride field-effect transistors
(eGaN FETs), not only to simplify the control implementation but also to achieve high power quality
and efficiency. The converter is designed to convert a 90–264-VAC input to a 385-VDC output for a
2.6-kW output power. Lastly, to validate the methodology, an experimental prototype is characterized
and fabricated. The uttermost efficiency at 230 VAC reaches 99.14%. The lowest total harmonic
distortion in the current (ITHD) at high line condition (230 V) attains 1.52% while the power factor
gains 0.9985.

Keywords: totem-pole power factor correction; energy storage systems (ESS); digital control;
gallium nitride (GaN)-based; current harmonic distortion mitigation; efficiency and power
quality improvement

1. Introduction
The grid-tied energy storage system has been one of the most prevailing technological approaches
for better harnessing the power generated from “clean” and “green” energy of natural resources,
reducing carbon footprints, and providing resiliency to the grid [1–8]. The system can accumulate
excess energy into battery packs and feed the stored energy from battery packs back into the utility
grid whenever needed by handling power converters. The change in the electric power from a form
to another form of DC/DC, DC/AC and AC/DC converters occurs while the reliability, flexibility,
stability, efficiency and power quality ought to be still secured [3,4,9,10]. Of all AC/DC converters,
the totem-pole boost-type power factor correction (PFC) rectifier has been a promising candidate for
ESS applications thanks to superior benefits of bidirectional energy flow capability, high flexibility in
control and the least device number [11,12]. Accordingly, as described in Figure 1, an interface with
the totem-pole boost-type PFC rectifier is able to construct a bidirectional interconnection of ESS and
the grid, thereby taking advantage of the photovoltaic panels and wind turbines as well as enhancing
the performance of the entire system [13].

Energies 2020, 13, 6297; doi:10.3390/en13236297 www.mdpi.com/journal/energies

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Figure 1. The totem-pole power factor correction (PFC) rectifier in energy storage systems.
Figure 1. The totem-pole power factor correction (PFC) rectifier in energy storage systems.
Owing to slow body diode reverse-recovery charge, the typical super junction metal-oxide-
Owing to
semiconductor slow body
field-effect diode reverse-recovery
transistor (MOSFET)-basedcharge, totem-polethe typical super
bridgeless PFCjunction
has been metal-oxide-
restricted to
semiconductor field-effect transistor (MOSFET)-based totem-pole bridgeless
critical-conduction mode operation (CRM) [14–17]. Even though operating in CRM with a soft-switching PFC has been restricted
to critical-conduction
method mode operation (CRM) [14–17].
can achieve valley/zero-voltage-switching Even though operating initCRM
or zero-current-switching, with a soft-for
is unappealing
switching method can achieve valley/zero-voltage-switching
higher power applications due to high zero-current-detection subcircuit cost, high EMI noise or zero-current-switching, it is and
unappealing for higher power applications due to high zero-current-detection
high input current ripple. By exploiting more advanced figure-of-merits (FOM) of fast switching subcircuit cost, high
EMI noise and high input current ripple. By exploiting more advanced figure-of-merits (FOM) of fast
WBG power electronic devices such as SiC MOSFETs and GaN FETs to substitute the Si power
switching WBG power electronic devices such as SiC MOSFETs and GaN FETs to substitute the Si
semiconductors, the WBG device-based totem-pole bridgeless PFC rectifier has become practical for
power semiconductors, the WBG device-based totem-pole bridgeless PFC rectifier has become
continuous conduction mode operation and improved the power density for the system [11,18–28].
practical for continuous conduction mode operation and improved the power density for the system
One of the modified versions of the totem-pole bridgeless PFC is implemented with a full-bridge
[11,18–28]. One of the modified versions of the totem-pole bridgeless PFC is implemented with a full-
configuration in synchronous
bridge configuration rectification
in synchronous mode, comprising
rectification mode, comprising active H-bridge switches
active H-bridge (Q1 , Q(Q
switches 2 , 1Q,Q 3 2and
,
Q4Q ),3which reduces the power dissipation when compared to the equivalent
and Q4), which reduces the power dissipation when compared to the equivalent diodes [25,28]. diodes [25,28]. These four
active
These switches constructing
four active two switching
switches constructing twolegs perform
switching voltage
legs performstep-up function
voltage step-upand line rectification.
function and line
Asrectification.
shown in Figure 1, two fast 650 V eGaN FETs, which are opted
As shown in Figure 1, two fast 650 V eGaN FETs, which are opted for this for this work, play thework,
same play role as
boost converters, whereas two low resistance Silicon MOSFETs are
the same role as boost converters, whereas two low resistance Silicon MOSFETs are placed toplaced to exterminate conducting
diodes. Correspondingly,
exterminate conducting the power
diodes. conduction path
Correspondingly, theembraces one fast switch
power conduction path and one slow
embraces one switch
fast
without
switchrelated
and onediode
slow drop
switchtowithout
ameliorate thediode
related efficiency.
drop to ameliorate the efficiency.
Similar
Similartotomost
most of the thebridgeless
bridgeless topologies,
topologies, it is it is evident
evident that anthat an inherent
inherent challenge challenge
of the totem- of the
pole boostboost
totem-pole PFC is PFCtheisconspicuous
the conspicuous common-mode
common-mode (CM) noises, especially
(CM) noises, a pounding
especially current spike
a pounding current
at the
spike zero-crossing
at the zero-crossing interval
intervalof AC
of ACvoltage, which
voltage, whichsignificantly aggravates
significantly aggravatesthe the
current
current lineline
quality,
quality,
such as total harmonic distortion (THD) and power factor (PF) [29–32].
such as total harmonic distortion (THD) and power factor (PF) [29–32]. The high current harmonic The high current harmonic
distortion
distortion woulddestructively
would destructivelyaffectaffectthethe grid
grid as
as well
well as as the
theother
otherelectrical
electricalequipment
equipment connecting
connecting to to
thethe grid,
grid, whilethe
while thelowlowpower
powerfactor
factorwould
would provoke
provoke the the energy
energyextravagance.
extravagance.AsAs is is
known,
known, thethe Si Si
MOSFET is modeled as an ideal switch with a body diode and a parasitic
MOSFET is modeled as an ideal switch with a body diode and a parasitic capacitor. Aside from the capacitor. Aside from the
cause of the abrupt alteration in the duty cycle, the zero-crossing distortion rooted by the poor reverse
cause of the abrupt alteration in the duty cycle, the zero-crossing distortion rooted by the poor reverse
recovery characteristic of the body diode and sudden discharge of the parasitic output capacitance of
recovery characteristic of the body diode and sudden discharge of the parasitic output capacitance of
the slow speed leg upper switch Q3 (from positive to negative half-cycle transition point) or lower
the slow speed leg upper switch Q3 (from positive to negative half-cycle transition point) or lower
switch Q4 (from negative to positive half-cycle transition point) when the corresponding fast leg
switch Q4 (from negative to positive half-cycle transition point) when the corresponding fast leg active
active switch turns on. For example, during the swap from negative to positive mains half-line cycle
switch turns on. For example, during the swap from negative to positive mains half-line cycle of the
of the input voltage, GaN FET Q2 becomes the active switch in the high-frequency leg. Since input
input voltage, GaN FET Q2 becomes the active switch in the high-frequency leg. Since input voltage
Energies 2020, 13, 6297 3 of 18

Energies 2020, 13, x FOR PEER REVIEW 3 of 18

is approximately zero, in order to output voltage reaches 385 V, Q2 has the widest duty while Q4
voltage is approximately zero, in order to output voltage reaches 385 V, Q2 has the widest duty while
was blocking 385 V during the negative half of the AC line cycle. For this reason, when Q2 turns
Q4 was blocking 385 V during the negative half of the AC line cycle. For this reason, when Q2 turns
on, the charge stored in the parasitic output capacitance of Q4 will incur a positive current spike on
on, the charge stored in the parasitic output capacitance of Q4 will incur a positive current spike on
thethe
input inductor.
input inductor. ToTogradually
graduallydischarge
dischargethe theparasitic
parasitic output capacitanceofofthe
output capacitance theslow-speed
slow-speed legleg
Si Si
MOSFET,
MOSFET, the soft-start technique with multiple gate pulses of increasing small duty ratio is applied at
the soft-start technique with multiple gate pulses of increasing small duty ratio is applied
zero-crossing
at zero-crossingarea area
[33].[33].
In In
order
order to circumventthe
to circumvent therequirements
requirementson on power
power performance
performance and andobstacles
obstaclessurrounding
surrounding thethe
bidirectional
bidirectional inductor
inductorcurrent, lacking
current, a bridge
lacking rectifier
a bridge and the
rectifier and function interchange
the function among among
interchange switches,
a new control
switches, structure
a new is proposed
control structure iswith the harmony
proposed with the inharmony
both firmware
in bothand hardware
firmware andto expeditetothe
hardware
control algorithm
expedite the controlandalgorithm
implementation. This paper This
and implementation. is organized into five sections.
paper is organized Section Section
into five sections. 2 gives a
2 gives control
proposed a proposed control architecture
architecture of the individual
of the individual blocks over blocks over the totem-pole
the totem-pole PFC converter
PFC converter topology.
topology.
In Section 3, In Section 3,
firmware firmware considerations
considerations on the
on the control controlof
strategy strategy of the converter
the converter are presented
are presented in detail.
in detail.
Section 4 shows Section 4 shows theresults,
the experimental experimental results,the
encompassing encompassing the measured
measured waveforms, waveforms,
converter efficiency,
PF converter
and THDefficiency, PF and
in the current THDdifferent
under in the current underFinally,
conditions. differentconclusions
conditions.andFinally, conclusions
remarks are drawnand in
remarks
Section 5. are drawn in Section 5.

2. Proposed
2. Proposed ControlStructure
Control Structure

2.1.2.1. Block
Block Diagram
Diagram
TheThe block
block diagramofofthe
diagram theproposed
proposed control
control system
system for
for the
the totem-pole
totem-polePFC PFCrectifier,
rectifier,which
whichis is
displayed in Figure 2, consists of major parts: power stage and sensing circuit, digital signal
displayed in Figure 2, consists of major parts: power stage and sensing circuit, digital signal processor processor
(DSP)
(DSP) controller
controller block
block andand auxiliary
auxiliary logiclogic circuit.
circuit. Each Each
blockblock is described
is described in more indetail
moreindetail in the
the following
following sections. Four signals, including the line voltage sensing signal, the neutral voltage
sections. Four signals, including the line voltage sensing signal, the neutral voltage sensing signal, sensing
thesignal, thecurrent
inductor inductor currentsignal
sensing sensing
andsignal and the
the output outputsensing
voltage voltagesignal,
sensingare
signal, are acquired
acquired from thefrom
power
the power stage circuit by the signal conditioning and sensing circuits to feed to the digital control
stage circuit by the signal conditioning and sensing circuits to feed to the digital control block.
block.

Figure 2. Simplified block diagram of the proposed structure.

Figure 2. Simplified block diagram of the proposed structure.
Energies 2020, 13, 6297 4 of 18

KAC , KI and KOUT denote the gain of the mains voltage sensing circuit, the gain of the current
sensing circuit, and the gain of the output voltage sensing circuit, respectively. Because the measurement
range of analog-to-digital (ADC) pins within DSP is from 0 to 3.3 V, the sensing signals are scaled in
order not to be greater than the maximum value of 2.5 V. For this tolerance purpose, KAC , KI and KOUT
should be limited by
2.5
KAC ≤ √ (1)
2VAC_MAX
where IRMS_MAX is the maximum root-mean-square value of the input current

2.5
KI ≤ √ (2)
2IRMS_MAX

where IRMS_MAX is the maximum root-mean-square value of the input current

2.5
KOUT ≤ (3)
VOUT_MAX

2.2. Power Stage and Sensing Circuit

2.2.1. Power Stage

The power stage of the totem-pole bridgeless PFC rectifier contains a pair of GaN FETs (Q1 , Q2 )
that switches at PWM frequency and a pair of regular MOSFETs (Q3 , Q4 ) that operates at line frequency.
Apart from EMI filtering and inrush circuit, two diodes (D1 , D2 ) are added in front of the PFC choke to
cope with the huge current for the load capacitance pre-charge. The topology operates in two modes
depending on the polarity of the AC voltage, where each fast-speed leg switch must perform either
master or slave mission as displayed schematically in Figure 3.
During the positive semi-period of the input voltage, Q4 is in ON–state and Q3 is in OFF–state:
upper fast-speed leg switch Q1 , lower fast-speed leg switch Q2 and power inductor LP form a boost
DC/DC stage where Q2 acts as a master switch and Q1 acts as slave switch. The operating states when
the input AC voltage is positive are illustrated in Figure 3a,b. When the main switch Q2 is ON with
t = (0, DTs ) (where D is the duty cycle and Ts is the switching period), the current flows from the
choke LP to Q4 through Q2 and back to neutral. The load is charged by the output capacitor at the
same time in this half-line cycle. When Q2 is open and Q1 is closed with t = (DTs , Ts ), the current
flows via Q1 , then via the output capacitor and load, and back to neutral through Q4 . The ground
of the output side is tied to neutral potential as Q4 is conducting all the time in a positive half-line
cycle. Another complete switching cycle repeats when Q2 switches on again by the gate-to-source
voltage of the driver circuit. Similarly, during the negative half-line cycle, Q3 is in ON–state and Q4 is
in OFF–state: the operation in the negative half-line cycle is analogous except the role of the upper and
lower switches are exchanged. Q1 turns out to be the master switch, and Q2 becomes the slave switch.
Figure 3c,d depict the operation principle when the input AC voltage is negative. Reliance on two
major operating modes, together with optimizing the performance, a new control signal sequence is
depicted and explained in Section 2.4.
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Figure 3. 3. Currentflowsflows during positive and negative AC half cycles: (a)(a)

positive ACAChalf-cycles from
Figure
Figure 3.Current
Current flows during
during positive and and negative
negative ACAC halfhalf cycles:
cycles: positive
(a) positive half-cycles
AC half-cycles from
0 to0 DT
from s; (b) positive AC half-cycles from DTDT s tos Ttos; T(c); (c)
negative ACAC half-cycles from 0 to
0 toDT s; (d)
0 to to
DTDT s ; (b)
s; (b)
positive
positive ACAC half-cycles
half-cycles fromfromDTs to T negative half-cycles from
s; (c) snegative AC half-cycles from 0 to DTs; (d) s
DT ;
(d)negative
negative ACAC half-cycles from
half-cycles from DT
DT
negative AC half-cycles from DTs to Ts. s to
s T
to .
sT s .

2.2.2. Signal Conditioning

2.2.2. and Sensing Circuit
2.2.2.Signal
Signal Conditioning
Conditioning and and Sensing
Sensing Circuit
Circuit
Referring
Referring toto
Referring to
Figure
Figure4, 4,the
Figure 4, the
the
signal
signalconditioning
signal conditioningand
conditioning andsensing
and sensing
sensing
circuit is isthe
circuit
circuit is the
interface
the interface
interface
ofofthe
of the
power
the power
power
stage
stageand
andcontrol
control
stage and control stage. For
stage. For the sake
the sakeof controller
of controllerdesign,
design,thethesystem
system uses
usesfourfoursensing
sensing
For the sake of controller design, the system uses four sensing circuitries and circuitries and
circuitries and
filters to
filters sense
filtersto
to sensethe
sense the vital signals,
the vital signals, namely
signals, namely input
namelyinput current
inputcurrentIL_sense
currentIL_sense,
IL_sensebus
, bus
, bus voltage
voltage
voltage V OUT_sense
VOUT_sense
VOUT_sense , input
, input, inputvoltage
voltage
voltage
Neutral VN_sense and input voltage line VL_sense .
NeutralVVN_sense
Neutral and input voltage
N_sense and voltageline
lineVVL_sense ..
L_sense

Figure 4. Sensing circuit of the proposed design.

Figure 4. Sensing circuit of the proposed design.
Figure 4. Sensing circuit of the proposed design.
Energies 2020, 13, 6297 6 of 18

Similar to most members belonging to the bridgeless PFC family, the current of totem-pole PFC
rectifier also withstands a fluctuating input line in regard to the output voltage ground and a continuous
shift of direction due to the inactivity of a boost converter branch in either cycle, an isolation methodology
is thus a must. In addition, the totem-pole PFC controller needs a rectified current reference signal
rather than the AC input current to realize PFC. To accomplish the requirement, two straightforward
shunt resistors RCS_N and RCS_L, are placed between the lower switch of slow speed phase leg Q4 and
the neutral terminal of the AC grid, upper switch Q3 and neutral terminal correspondingly.
An isolated sensing solution is applied with an isolation amplifier and an operational amplifier,
which are assembled in series after the current sensing resistors. The +5 V supply voltage for input
side VDD1 in respect of CS_N point is transported from the output of a low dropout voltage regulator
IC, which also drives the upper switch Q3 . The input side ground GND1 of the isolation amplifier is
referred to as the CS_N point, while the output side ground GND2 is linked to the ground of the power
stage. It can be observed from Figure 4 that the waveform of IL_sense with desired gain and rectified
positive shape is achieved as the output of the differential amplifier. The gain of the current sensing
circuitry is able to be derived as
KI = RCS GIso GOA (4)

RCS , GIso and GOA are the expressions of the resistance of the current sensing resistor, the gain of
the isolation amplifier and the gain of the op-amp, respectively. The inductor current obtains the highest
value when the difference in the positive input voltage and the negative input voltage (VIN+ − VIN− )
reaches the maximum value, which is effortlessly inferred from the component datasheet. The value
of current sensing resistors RCS_N and RCS_L should be selected depending mainly on the estimated
division between the maximum value in the differential input voltage of the isolation amplifier and the
peak value of the root-mean-square value of the input current.

(VIN+ − VIN− )MAX

RCS_N = RCS_L = √ (5)
2IRMS_MAX

Moreover, in this design, the designated shunt resistors are non-inductive resistors in an attempt
of minimizing the di/dt slew rate induced voltage spikes, which may have a detrimental impact on
the operation. In the aspect of sensing the input voltage, a low-frequency transformer is regularly
employed. Nevertheless, the transformer is costly, bulky and occupies a large area of the circuit, which
makes it incompatible with the high efficiency-oriented application. The higher linearity optical coupler
with a wide operating range is a common solution for voltage sensing as well. However, in comparison
with the voltage dividers, the optical coupler is much more complicated. In this paper, the line AC
voltage and neutral AC voltage are sensed separately by the voltage divider and then filtered to
eliminate high-frequency interference noises by a low-pass filter with waveforms as displayed in
Figure 4. Hence, the targeted sinusoidal VAC is obtained through the rectification function in the DSP
control block. The feedback circuit of DC output voltage is also implemented by a voltage divider in
combination with an RC network for simplicity.

2.3. DSP Control Block

The functional block diagram of the controller inside the DSP is introduced in Figure 5. In this
paper, the controller is implemented by using digital control with 60 MHz Texas Instrument
core-TMS320F28035. It is necessary to use four input signals IL_sense , VOUT_sense , VN_sense and VL_sense
for compensators as well as different functions. These sensed signals are converted to digital by using
12-bit ADC modules for sampling and conversion process from the DSP. Moreover, then, based on the
control method described in Section 3, the duties for the master switch and the slave switch can be
determined and implemented through enhanced pulse width modulation (EPWM) modules. In this
way, by using the auxiliary control circuit, the accurate gating signals are delivered for controlling all
switches at any operating condition by the logic control circuit. It is worth noting that the grid voltage
Energies 2020, 13, 6297 7 of 18

Energies
V is 2020, 13, x FOR
measured byPEER REVIEW
sensing the VN _sense and VL _sense independently; thus, the VAC_DSP which 7 of 18
is
AC
used for calculation in DSP should be derived as:
the grid voltage VAC is measured by sensing the VN_sense and VL_sense independently; thus, the
> VN_sense
(
VAC_DSP which is used for calculation VL_sense − VN_sense
in DSP should be derived as:
when VL_sense
VACDSP = (6)
VN_sense
V_ − V
− L_sense
V _ when V
when VN_sense > > VVL_sense
_ _
V = (6)
V _ −V _ when V _ >V_
When the converter operates in the positive AC semicycle, the VAC_DSP is equal to the difference
When −
of VL_sense theVN_sense
converter
whileoperates in the positive
the VAC_DSP is equalAC semicycle,
to the the of
difference VAC_DSP is equal
Vn_sense to theduring
− VL_sense difference
the
of VL_sense half-line
negative − VN_sense cycle.
while the VAC_DSP is equal to the difference of Vn_sense − VL_sense during the negative
half-line cycle.

Figure
Figure 5.
5. Functional
Functional block
block diagram
diagram of
of the
the controller
controller within
within the
the digital signal processor (DSP).

Figure 55also
alsoshows
showsthat thethe
that totem-pole
totem-polePFCPFC controller is composed
controller is composed of twoof control loops: the
two control voltage
loops: the
control loop is a low-frequency outer loop which regulates the output
voltage control loop is a low-frequency outer loop which regulates the output voltage of the boost voltage of the boost power
stage tostage
power be equal
to betoequal
the desired
to the reference value, while
desired reference value, thewhile
current thecontrol
currentloop is a high-frequency
control loop is a high-
inner loopinner
frequency whose target
loop is totarget
whose makeiscertain
to make the inputthe
certain current
inputshape
current to shape
be a replica
to be aofreplica
the AC of voltage
the AC
shape. In
voltage termsInofterms
shape. the voltage
of the control
voltageloop, VOUT_sense
control is subtracted
loop, VOUT_sense from the
is subtracted reference
from output voltage
the reference output
Vcmd . The
voltage resulting
Vcmd difference
. The resulting signal Vcmd
difference − VV
signal is then fed
cmd − VOUT_sense
OUT_sense into the
is then fed voltage
into theloop controller.
voltage loop
The bandwidth
controller. of the voltage
The bandwidth loop
of the must be
voltage loopfarmust
less than
be far 120lessHzthan
to sufficiently attenuate the
120 Hz to sufficiently second
attenuate
harmonic
the secondofharmonic
the outputof voltage. As forvoltage.
the output the currentAs loop, IL_sense
for the currentis subtracted
loop, IL_sensefromis the current command
subtracted from the
Icmd . The
current resultingIdifference
command cmd. The resulting cmd − IL_sense
signal (Idifference ) is then
signal (Icmd fed into)the
− IL_sense current
is then fedloop
into type II controller,
the current loop
whose output is sent to the EPWM module. However, only the current
type II controller, whose output is sent to the EPWM module. However, only the current loop loop controller cannot make
the powercannot
controller qualities makemeet
the the
powerrequirements.
qualities meet Antheadvanced
requirements. technique, i.e., duty-ratio
An advanced feedforward
technique, i.e., duty-
from [34],
ratio is combined
feedforward fromwith this
[34], is duty cycle towith
combined create theduty
this PWM_Master
cycle to createand PWM_Slave
the PWM_Masterin a suitable
and
way. A deadtime
PWM_Slave is accompanied
in a suitable between these
way. A deadtime two EPWMs
is accompanied in the middle
between these two of switching
EPWMs inevents to be
the middle
immune
of to shoot-through
switching events to be conditions
immune towhile the masterconditions
shoot-through and slave switch while thefleetingly
masterturnandoff.
slaveMoreover,
switch
it is important
fleetingly turn to note
off. that the other
Moreover, four functioning
it is important to notesignals,
that thepositive
other four polar detector, blanking
functioning signals, window,
positive
negative
polar delayblanking
detector, window window,
and positive delaydelay
negative window,windoware fashioned
and positive fordelay
different purposes,
window, which is
are fashioned
stated
for more visibly
different purposes, in the following
which auxiliary
is stated circuit.in the following auxiliary circuit.
more visibly

2.4. Auxiliary
2.4. Auxiliary Logic
Logic Circuit
Circuit
The establishment
The establishment of
of the
theauxiliary
auxiliarycontrol
controllogic
logiccircuit
circuitisisbased
basedononthe idea
the ofof
idea exporting thethe
exporting turn-on
turn-
and turn-off sequence of four switches Q , Q , Q and Q in a smooth and simple way. As
on and turn-off sequence of four switches1 Q12, Q2,3 Q3 and4,Q4, in a smooth and simple way. As shown shown in
in Figure 6, a straightforward signal sequence (on the left-hand side) and an auxiliary control logic
circuit (on the right-hand side) are further elaborated to generate the expected signals for all switches.
Energies 2020, 13, 6297 8 of 18

Figure 6, a straightforward signal sequence (on the left-hand side) and an auxiliary control logic circuit
Energies
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further elaborated to generate the expected signals for all switches. 8 of 18

Figure 6. Key signal sequence (left) and auxiliary logic circuit (right) of the proposed control structure.
Figure 6. Key signal sequence (left) and auxiliary logic circuit (right) of the proposed control
structure. sent from the DSP controller and four targeted
There are six input signals of the control subcircuit
output signals transmitted to the gating driver of switches. Among them, the duty cycle for the
mainThereswitchare six input signals
PWM_Master and the of the
dutycontrol
cycle of subcircuit sent from the DSP
the synchronous-rectifier controller
switch and four
PWM_Slave is
targeted output signals transmitted to the gating driver of switches. Among
directly routed from the output of the controller. One of the four remaining functioning-signals is them, the duty cycle for
athe main switch
positive PWM_Master
polar detector formed and thesensing
from duty cycle
the of the synchronous-rectifier
input grid voltage VAC to decide switchwhich
PWM_Slave
switches is
work according to the distinct operating mode of the totem-pole PFC rectifier. The output signal of thea
directly routed from the output of the controller. One of the four remaining functioning-signals is
positive polar
positive polar detector
detector isformed
HIGH from whensensing
the gridthe inputgoes
voltage gridpositive.
voltage V OnAC to decide which switches
the other hand, the output
work according to the distinct operating mode of the totem-pole
signal of the positive polar detector goes LOW as the grid voltage is negative. A NOT PFC rectifier. Thelogic
output
gatesignal
is usedof
the positive polar detector is HIGH when the grid voltage goes positive.
to invert the positive polar detector signal in the effort of avoiding the shoot-through of two fast-speedOn the other hand, the
output signal
switches at theof the time.
same positive polar
These detector
signals also goes
have LOW as the grid
the capability voltage is
of enabling and negative.
disabling A AND
NOT gates
logic
gate is used to invert the positive polar detector signal in the effort of
to switch the PWM sequences alternately for each half-line period. Meanwhile, a blanking window avoiding the shoot-through of
two
is fast-speed switches
supplemented for safety atpurposes
the sameunder time. abnormal
These signals also have
conditions the capability
in which all switches of are
enabling
turnedand off
disabling AND gates to switch the PWM sequences alternately for each half-line
during the commutation intervals at the boundaries of positive and negative half-line cycles. For the period. Meanwhile,
a blanking
reason windowunwanted
of evading is supplemented for safetyby
issues instigated purposes under current
the crossover abnormal conditions
spikes, in which
the negative delayall
switchesand
window are positive
turned off during
delay windowthe commutation
are proposed intervals
to insert the at the boundaries
delay time between of positive
turn onand negative
moments of
the fast speed leg and slow speed leg. More specifically, the negative delay window and positivespikes,
half-line cycles. For the reason of evading unwanted issues instigated by the crossover current delay
the negative delay window and positive
on Q3 /Qdelay window are proposed to insert the delay time between
window are realized by turning 4 after Q1 /Q2 experiences a turn-on in either semicycle such
turn the
that on slow-speed
moments ofleg the fast speed
switches leg and slow
can completely speedrecover
reverse leg. More
wherebyspecifically,
the drive the negative
gating delay
signals for
window and positive delay window are realized by turning on Q 3/Q4 after Q1/Q2 experiences a turn-
line-frequency-switched devices and high-frequency-switched devices are fulfilled in an optimal way.
on incourse
This either is
semicycle
important such that
since it the slow-speed
contributes leg switches
pointedly can completely
to downgrade reverse
the current spikesrecover whereby
and the ITHD.
the drive gating signals for line-frequency-switched devices and high-frequency-switched devices
areFirmware
3. fulfilled in an optimal
Design for the way. This course
Control Strategy is important since it contributes pointedly to downgrade
the current spikes and the ITHD.
3.1. Algorithm Flowchart
3. Firmware Design totem-pole
This prototype for the Control PFCStrategy
software is implemented by EPWM interrupt service routine
(ISR) of DSP controller, with running all PFC functions, and state machines in the periodical interrupt.
3.1. Algorithm Flowchart
This prototype totem-pole PFC software is implemented by EPWM interrupt service routine
(ISR) of DSP controller, with running all PFC functions, and state machines in the periodical interrupt.
In addition to the PFC functions and state machines, initializing the variables and clearing the
Energies 2020, 13, 6297 9 of 18

Energies
In 2020,to
addition 13,the
x FOR
PFCPEER REVIEWand state machines, initializing the variables and clearing the controller
functions 9 of 18

parameters, in the beginning, handled in the main background loop. The control method is designed
controller
to form oneparameters, in the beginning,
compact software and can behandled in the main
easily integrated intobackground loop. The
the DSP controller of control method
the application
for easing to use in the industrial environment. The entire PFC control software is implemented inoftwo
is designed to form one compact software and can be easily integrated into the DSP controller the
application for easing to use in the industrial environment. The entire PFC control
ISRs. The current loops are executed in the fast interrupt every 15.38 µs, the voltage loop and state software is
implemented
machine in two in
are executed ISRs.
the The current
slower loops
interrupt areaexecuted
with in the of
30.76 µs period fast interruptThe
execution. every 15.38 µs,
flowchart the
of the
voltage loop and state machine are
ISR loop is shown in the following Figure 7. executed in the slower interrupt with a 30.76 µs period of
execution. The flowchart of the ISR loop is shown in the following Figure 7.

Figure 7. The
Figure 7. The principal
principal software
software flowchart
flowchart of
of the
the proposed
proposed control
controlstructure.
structure.

The flowchart for PFC implementation is explained in more detail below. These critical tasks are
The flowchart for PFC implementation is explained in more detail below. These critical tasks are
assigned in the ISR loop.
assigned in the ISR loop.
•• Obtain
ObtainADC
ADCresults:
results: The
The task
task aims
aims at
at acquiring
acquiring 44 ADC ADC channel
channel values
values comprising
comprisingthe the line
line voltage
voltage
sensing signal,
sensing signal, the
the neutral
neutral voltage
voltage sensing
sensing signal,
signal, the
the inductor
inductor current
current sensing
sensing signal
signal and
and thethe
output voltage sensing
output voltage sensing signal. signal.
•• Generate
Generatefunctioning
functioningsignals:
signals: InIn the
the hardware
hardware design,
design, employing
employing the the proper
proper driving
driving signals
signals atat the
the
auxiliary logic circuit for controlling GaN switches and MOSFETs results
auxiliary logic circuit for controlling GaN switches and MOSFETs results in the need of generating in the need of
generating functioning signals such as positive polar detector, blanking window,
functioning signals such as positive polar detector, blanking window, negative delay window and negative delay
windowdelay
positive and window.
positive delay window.
Accordingly, thisAccordingly, this task
task creates these creates signals
functioning these functioning
based on thesignals
ADC
based on the ADC results of the line voltage sensing signal, the neutral voltage
results of the line voltage sensing signal, the neutral voltage sensing signal and the output voltage sensing signal
and thesignal
sensing output as voltage
aforesaidsensing signal
in Section 2.3. as aforesaid
Software in subsection
counters 2.3. Software
are appropriately added counters
to remove are
appropriately added to remove glitches or noises influencing these
glitches or noises influencing these functioning signals adversely. For instance, in case of the functioning signals
adversely.
positive polarFordetector
instance,signal
in case of the positive
changes the statepolar
fromdetector
HIGH tosignal
LOW,changes
but not the state
at the from HIGH
zero-crossing
to LOW,
zone, whichbut not atthe
enables thecounter
zero-crossing
increment zone,
in a which enables the
row, a threshold counter increment
is programmed with suchin aa higher
row, a
threshold is programmed with such a higher value than this counter that the
value than this counter that the function can clear the improper signal. Otherwise, the controller function can clear
the improper signal. Otherwise, the controller will behave as if the AC grid
will behave as if the AC grid swaps to a negative semicycle. Thus an enormous current spike will swaps to a negative
semicycle.
be producedThus an enormous
by being current spike
shorted between will be
the ground and produced by being
output bus, resultingshorted
in thebetween
damagethe of
ground and
the components. output bus, resulting in the damage of the components.
•• Rectify
RectifyVac_DSP:
Vac_DSP:The The task
task produces
produces the the rectified
rectified waveform
waveform (M-shape
(M-shape waveform)
waveform) of the ofACthe AC
mains
mains voltage sensing signal to prepare for calculating
voltage sensing signal to prepare for calculating the current command. the current command.
• Calculate current command (ABCKm): The task calculates the current command Icmd where factors
are established in corresponding as follows: The notation A is the output of the voltage loop
controller whose maximum value U _ and minimum value U _ contain:
Energies 2020, 13, 6297 10 of 18

• Calculate current command (ABCKm ): The task calculates the current command Icmd where factors
are established in corresponding as follows: The notation A is the output of the voltage loop
controller whose maximum value UV_MAX and minimum value UV_MIN contain:

UV_MAX ≥ A ≥ UV_MIN (7)

Afterward, the notation B, which is the inverse of squared Vrms, is derived to calculate within
DSP by:
1 1
B=  (8)
4095 2 VRMS 2

3.3KAC

where 4095
3.3 is the DSP coefficient of 12-bit ADC. It should be noticed that both A and B are calculated in
the previous interrupt service routine. Next, C denotes the AC mains voltage sensing signal:

4095
C= V (9)
3.3KAC AC

Moreover, then Km is the multiplier gain, which is specified as a constant designed in advance.
To choose the proper Km , some extra steps should be taken. The first action is expressing the current
command from Equations (7)–(9):

1 1 4095
Icmd = A(  )( VAC )Km (10)
4095KAC 2 VRMS 2 3.3KAC

3.3
√  
Simplifying and substituting VAC = 2VRMS sin(ωt), the Equation (10) becomes:

1 1  √  
Icmd = A( 4095K ) 2sin(ωt) Km (11)
AC VRMS
3.3

Meanwhile, the measured current value is given within DSP by:

4095
Imsd = IAC KI (12)
3.3
√  
Substituting IAC = 2IRMS sin(ωt), the Equation (12) becomes:

√   4095
Imsd = 2IRMS sin(ωt) KI (13)
3.3
Following the current control law, the measured current value must be equal to the commanded
current value Icmd = Imsd , combining the Equations (12) and (13) with PAC = VRMS IRMS PF = VRMS IRMS
due to the close-to-unity power factor, Km is deducted as:
2
4095KAC KAC KI

Km = PAC (14)
3.3 A

• Implement Duty-cycle feedforward and current loop: The current loop controller is designed and
implemented by DSP to catch improved duty cycles for PWM_Master and PWM_Slave.
• Assign the new duty cycle: After implementing the duty feedforward and current loop controller,
the new duty value is available. Afterward, an upper-end limitation is imposed on this updated
duty ratio to prevent excessive current and instability when working at a high duty ratio. Therefore,
the objective of this task is assigning the novel duty cycle value to assure the duty of EPWMs
signals placed on the correct gate driver’s signal pin.
Energies 2020, 13, 6297 11 of 18

3.2. State Machine

Referring to Figure 8, five specific states of the PFC state machine are described briefly with the
Energies
state 2020, 13, x FOR PEER REVIEW
diagram. 11 of 18

Figure
Figure 8. PFC state
8. PFC state diagram
diagram running
running in
in interrupt
interrupt service
service routine
routine (ISR).
(ISR).

•• Idle: Inrush current

Idle: Inrush current relay
relay is
is turned
turned offoff rather
rather than
than bypassing
bypassing thethe inrush
inrush current
current resistor
resistor in
in the
the
beginning.
beginning. Inrush current relay is turned on (bypass the inrush current resistor) and moving to
Inrush current relay is turned on (bypass the inrush current resistor) and moving to
the
the next
next state
stateififVVAC is continually higher than 85 V during 100 ms. At the beginning of a start-up,
AC is continually higher than 85 V during 100 ms. At the beginning of a start-
both outputs
up, both of the
outputs of voltage looploop
the voltage and and
control looploop
control are zero.
are zero.
•• Relay bounce: Checking
Relay bounce: Checking VAC V is still higher than 85 V after the relay bounces. If V AC is
AC is still higher than 85 V after the relay bounces. If VAC
is stable
stable in
in aa
duration
duration of of 1000
1000ms,ms, the
the controller
controller is is enabled.
enabled.
•• Ramp-up: The output voltage value
Ramp-up: The output voltage value is elevated is elevated linearly.
linearly. The
The controller
controller forces
forces the output voltage
the output voltage
to
to follow
follow the
the reference
reference value
value until
until the
the output
output voltage
voltage reaches
reaches the
the demanded
demanded value.
value. This
This leads
leads to
to
protecting the circuit from the excessive starting-up
protecting the circuit from the excessive starting-up current. current.
•• Steady state: The normal condition of PFC operation and checking of an overvoltage condition. condition.
•• Fault: The incidents of fault state concerning the output voltage are determined by being out of
range. Once
Once the voltage exceeds
exceeds more or less than 6% of its nominal value, the controller will
overvoltage protection.
activate the overvoltage protection.

4. Experimental Results
4. Experimental Results
To
To confirm
confirm thethe functionality
functionality and
and to
to measure
measure the the efficiency
efficiency of
of the circuit, aa pertinent
the circuit, pertinent experimental
experimental
arrangement is formed. Figure 9 depicts a global view of the realized converter,
arrangement is formed. Figure 9 depicts a global view of the realized converter, whereas Table whereas Table 11
tabulates
tabulates the
the specification
specification of of the
the prototype.
prototype. A A 2.6
2.6 kW
kW totem-pole
totem-pole PFCPFC prototype
prototype is is built
built with
with the
the
standard
standard grid
grid voltage range of
voltage range of 90
90 to
to 264
264 VAC.
VAC. The The control
control daughter
daughter card
card is
is attached
attached toto the
the mother
mother
power
power stage
stageboard
boardand andworks
works asas
thethe
brain for for
brain the the
whole converter.
whole The needed
converter. The needed valuevalue
for current sense
for current
resistors is 10 mOhm
sense resistors for eachfor
is 10 mOhm side of the
each sideslow-speed leg to compromise
of the slow-speed the measurement
leg to compromise accuracy
the measurement
and
accuracy and the power dissipation, as mentioned previously. To satisfy the required wattage,Ohm
the power dissipation, as mentioned previously. To satisfy the required wattage, four 0.04 four
resistors
0.04 Ohmare stackedare
resistors in stacked
parallel.inThe footprint
parallel. Thedimension of the designed
footprint dimension of thecircuit
designedis 11.9 cm ×is9.6
circuit cmcm
11.9 ×
5.4 cm.
× 9.6 cm × 5.4 cm.
 IXFH60N65X2 as slow speed leg
Power inductor LP 604 µH
Output capacitor CL 2*560 µF
Controller core DSP TMS320F28035
Power factor ≥ 0.99
Energies 2020, 13, 6297 Peak efficiency > 99.1% 12 of 18
Harmonic content < 2% at 230 V and full load

Control card
Energies 2020, 13, x FOR PEER REVIEW 12 of 18
Slow-speed Fast-speed leg
leg MOSFETs Table 1. The specification and the parameters of the design. GaN FETs

Item Value/Model Output

Input supply voltage VAC 90–264 Vac capacitors
Output voltage VOUT 385 Vdc bus nominal
Input frequency fline 43–63 Hz DSP
1 kW @ 90–132 V, with 115 V nominal
Output power POUT
2.6 kW @ 180–264 V, with 230 V nominal
Auxiliary
Switching frequency fs 65 kHz
GaN System’s GS66516B as fast control
speed circuit
leg
Semiconductor device Q1, Q2 Semiconductor device Q3, Q4
IXFH60N65X2 as slow speed leg
Power inductor LP 604 µH
Output capacitor CL 2*560 µF
Power inductor EMI filter and bypass relay
Controller core DSP TMS320F28035
(a)Power factor (b)
≥ 0.99
Peak efficiency > 99.1%
Figure 9.
Figure Perspectiveof
9. Perspective ofthe
thehardware
hardware prototype:
prototype: (a)
(a)bird’s
bird’seye
eyeview;
view;(b)
(b) top
top side view.
view.
Harmonic content < 2% at 230 V andside
full load
Table 1. The specification and the parameters of the design.
Control
Figure 10 displays thecard
experimental waveform of the input voltage and the inductor current
Slow-speed
under the full load condition 115 VAC.Fast-speed
of the 2.6 kW at 230 VAC and the 1 kW atValue/Model
Item It can be leg
shown
leg MOSFETs
that the inductor current (channel 2) is perfectly sinusoidal and in phase with GaN
the FETs voltage
input
Input supply voltage VAC 90–264 Vac
(channel 1) seamlessly.
Output voltage VOUT 385 Vdc bus nominal
Output
Input frequency fline 43–63 Hz capacitors
1 kW @ 90–132 V, with 115 V nominal
Output power POUT
2.6 kW @ 180–264 V, with 230 V nominal
Switching frequency fs 65 kHz DSP
GaN System’s GS66516B as fast speed leg
Semiconductor device Q1 , Q2 Semiconductor device Q3 , Q4 Auxiliary
IXFH60N65X2 as slow speed leg
Power inductor LP 604 µH control circuit
Output capacitor CL 2*560 µF
Controller core DSP TMS320F28035
Power factor ≥0.99
Power
Peak inductor
efficiency EMI filter and bypass relay
>99.1%
(a)
Harmonic content <2% at (b)
230 V and full load
(a) (b)
Figure 9. Perspective of the hardware prototype: (a) bird’s eye view; (b) top side view.
Figure10.
Figure 10Experimental
displays thewaveforms
experimental of the waveform
totem-pole PFCof the inputrunning
rectifier voltage (a)and the
at 230 VACinductor current
input and
under Figure
2.6the
kWfull 10
output displays
loadload; (b)the
condition experimental
ofVAC
at 115 the 2.6
inputkWwaveform
at 1230
and kWVAC of the
outputand input
the
load 1voltage
(for kW
bothat andandthe
115
left VAC. inductor
right current
Itfigures:
can be shown
VAC
under
that 100 the full load
theV/division,
inductor condition
current
channel IL 5ofA/division,
(channel
1– the2)2.6iskW at 230 2.VAC
perfectly
channel and the
sinusoidal
Timebase 5and1 kWin at 115 VAC.
phase
ms/division). with It can
the be shown
input voltage
that the1)inductor
(channel current (channel 2) is perfectly sinusoidal and in phase with the input voltage
seamlessly.
(channel 1) seamlessly.

(a) (b)

Figure
Figure 10.10.Experimental
Experimentalwaveforms
waveforms of of the totem-pole
totem-polePFCPFCrectifier
rectifierrunning
running(a)(a)
atat
230 VAC
230 VAC input and
input and
2.62.6
kW kW outputload;
output load;(b)
(b)atat115
115VAC
VACinput
inputand
and11 kW
kW output
output load
load (for
(for both
bothleft
leftand
andright
rightfigures:
figures:VAC
VAC
100100 V/division,
V/division, channel1–1–ILIL55A/division,
channel A/division, channel
channel 2.
2. Timebase
Timebase55ms/division).
ms/division).
transition conditions of load from 100% to 50%, from 50% to 100%, from 50% to 0%, and from 0% to
50%. The purple curve (channel 1), the hot pink curve (channel 2), the light blue curve (channel 3),
and the dark yellow curve (channel 4) demonstrate the AC input voltage, the inductor current, the
output current, and the DC link voltage on the output terminal, respectively. The input current hits
the new static operation point shortly after a few mains period with a trivial overshoot at first. The
Energies 2020, 13, 6297 13 of 18
bus voltage fully recovers within roughly 395 ms and discloses the maximum deviation of 34 V.
The prototype of the totem-pole PFC rectifier is also tested under the start-up scheme of the
converter at the
In order to mains
reveal voltage
dynamic of responses
90 VAC and of 230
the VAC with aaminimum
prototype, load step load
fromof 300tomA,
low highasand
revealed
from
in Figure
high 12a,b.
to low loadThe light
with theblue curve
output (channel
voltage 3) shows
tightly the DC
regulated link VDC.
at 385 voltage on the11a–d
Figure output, whereas
display the
the hot pink curve (channel 2) embodies the inductor current and the purple curve
transition conditions of load from 100% to 50%, from 50% to 100%, from 50% to 0%, and from 0% to 50%.(channel 1) depicts
the
The input
purplevoltage, respectively.
curve (channel 1), theReferring to these
hot pink curve figures,
(channel 2), the complete
the light start-up
blue curve procedure
(channel 3), andtakes
the
approximately
dark yellow curve 1950(channel
ms. The4)input AC voltage
demonstrate the achieves
AC inputthe start value
voltage, after several
the inductor current,firstthe
charging
output
pulses.
current,Subsequently,
and the DC link the input on
voltage current rises terminal,
the output in a linear way until The
respectively. the input
bus voltage
currentachieves
hits the new the
designed value.point
static operation As soon as Vafter
shortly OUT reaches this point,
a few mains thewith
period statea machine turns into
trivial overshoot at the
first.Steady
The bus state, and
voltage
the circuit jumps to the regulation operation. This feature can deal
fully recovers within roughly 395 ms and discloses the maximum deviation of 34 V. with excessive power dissipation
and reduce device stress.

(a) (b)

(c) (d)
Figure 11. Measurement
Measurementresultresultofofthe
thetransient
transientresponse
response (a)(a)
from 100
from to to
100 50 50
percent load;
percent (b)(b)
load; from 50
from
50 100
to to 100 percent
percent load;
load; (c) from
(c) from 50 to50 to 0 percent
0 percent load;
load; (d) (d)0from
from to 500percent
to 50 percent load.
load. (for (for all V
all figures: figures:
AC 100

VAC 100 V/division,

V/division, channel 1– channel 1– IL 10 A/division,
IL 10 A/division, channel 2–channel
VOUT 50 2– VOUT 50 channel
V/division, V/division, channel
3– IOUT 3– IOUT
2 A/division,
2 A/division, channel 4. Timebase
channel 4. Timebase 500 ms/division). 500 ms/division).

The prototype of the totem-pole PFC rectifier is also tested under the start-up scheme of the
converter at the mains voltage of 90 VAC and 230 VAC with a minimum load of 300 mA, as revealed in
Figure 12a,b. The light blue curve (channel 3) shows the DC link voltage on the output, whereas the hot
pink curve (channel 2) embodies the inductor current and the purple curve (channel 1) depicts the input
voltage, respectively. Referring to these figures, the complete start-up procedure takes approximately
1950 ms. The input AC voltage achieves the start value after several first charging pulses. Subsequently,
the input current rises in a linear way until the bus voltage achieves the designed value. As soon as
VOUT reaches this point, the state machine turns into the Steady state, and the circuit jumps to the
regulation operation. This feature can deal with excessive power dissipation and reduce device stress.
Energies 2020, 13, 6297 14 of 18
Energies 2020, 13, x FOR PEER REVIEW 14 of 18
Energies 2020, 13, x FOR PEER REVIEW 14 of 18

(a) (b)
(a) (b)
Figure 12. Start-up waveforms of the totem-pole PFC (a) at 90 90 VAC
VAC with
with300
300mAmAload
loadcurrent;
current;(V(VAC
AC

50Figure 12. Start-up

V/division
V/division ininAC
waveforms
ACcoupling
coupling of thechannel
mode,
mode,
totem-pole IPFC
channel 1– I1– L 5 (a) at 90 VAC
A/division,
L 5 A/division,
with 300
channel
channel 2– V 2–
OUT
mA
V
50
load
50 current; (VAC
V/division,
V/division,
OUT channel
50 V/division
channel in AC500
3. Timebase coupling mode, (b)
ms/division) channel
at 2301– IL 5 A/division,
VAC withmA mAchannel
300load load 2– VOUT
current 50 V/division, channel
3. Timebase 500 ms/division) (b) at 230 VAC with 300 current (VAC(V100 100 V/division
ACV/division in ACin
AC3. Timebase
coupling 500
mode, ms/division)
channel (b) at 230 VAC with 300 mA load current (V AC 100 V/division in AC
coupling mode, channel 1– I1– ILA/division,
L 10 10 A/division, channel
channel 2– V2– VOUT
OUT 50 V/division,
50 V/division, channel
channel 3. Timebase
3. Timebase 200
coupling
200 mode, channel 1– IL 10 A/division, channel 2– VOUT 50 V/division, channel 3. Timebase 200
ms/division).
ms/division).
ms/division).
The
The efficiency
efficiency curve
curve with
with relation
relation to
to the
the continuous output power
continuous output power atat 230
230 VAC
VAC line
line voltage
voltage is
is
shown The
in efficiency
Figure 13, curvethe
where with relation
efficiency to the continuous
achieves 99.14% at outputhigh
nominal power
lineat 230 VACand
conditions linemaintains
voltage is
shown in Figure 13, where the efficiency achieves 99.14% at nominal high line conditions and
shown
over 98.5%in for
Figurewhole
13, where range.
the efficiency achieves 99.14% at nominal high line conditions and
maintains overthe98.5% for load
the whole load range.
maintains over 98.5% for the whole load range.

Figure 13. The efficiency curve with the overall load range of 2.6 kW at high line condition 230 VAC.
Figure 13.The
Figure13. Theefficiency
efficiencycurve
curvewith
withthe
theoverall
overallload
loadrange
rangeofof2.6
2.6kW
kWatathigh
highline
linecondition
condition230
230VAC.
VAC.
The measured
The measuredPF PFand and ITHD
ITHD values,
values, which
which are major
are the the major reference
reference for evaluating
for evaluating the power the quality
power
The measured PF and ITHD values, which are the major reference for evaluating the power
quality performance,
performance, are essentially
are essentially decided decided
by by themethodology
the control control methodology and compensation
and compensation rather thanrather
the
quality performance, are essentially decided by the control methodology and compensation rather
than
power the power
stage. Tablestage.
2 Table
summarizes 2 summarizes
the measured thePFmeasured
and THD PF
of and
the THD
proposed of the proposed
control structure control
at the
than the power stage. Table 2 summarizes the measured PF and THD of the proposed control
structure
minimum at the minimum and maximum input AC voltage over ten different load levels. The PF and
structureand maximum
at the minimum input
and AC voltage input
maximum over ten
ACdifferent load ten
voltage over levels. The PF
different andlevels.
load THD The measured
PF and
THD
at measured atfull
maximum line fulland
load are 0.998 and 2.79%, respectively, whereas thoseline
at the
THD measured at maximum line full load are 0.998 and 2.79%, respectively, whereas those atare
maximum line load are 0.998% 2.79%, respectively, whereas those at the minimum the
minimum
0.999% andline are 0.999
1.76%, and 1.76%, respectively. Meanwhile,
14 showsFigure 14 shows theatpower factorvoltage
at low
minimum line arerespectively.
0.999 and 1.76%, Meanwhile, Figure
respectively. Meanwhile, the power
Figure factor
14 shows the low
power input
factor at low
input
115 VACvoltage 115 VAC
(dot-dashed (dot-dashed
line) and high input line) voltage
and high 230input
VAC voltageline).
230 VACpower(solidfactor
line). higher
The power
input voltage 115 VAC (dot-dashed line) and high input(solid
voltage 230The VAC (solid than
line). The power
factor
0.99 higher
from 30% than
load 0.99
to from
100% 30%
load. load to 100% load.
factor higher than 0.99 from 30% load to 100% load.
Energies 2020, 13, 6297 15 of 18
Energies 2020, 13, x FOR PEER REVIEW 15 of 18

Table2.2.The
Table Themeasured
measuredtotal
totalharmonic
harmonicdistortion
distortion(THD)
(THD) and
and power
power factor
factor (PF) at the line voltage
voltage of
of
90 V and 264 V. 90 V and 264 V.

Load (%) Load (%)

VV AC = 90
AC = 90 VV VAC = 264VACV= 264 V
PF THD (%) PF THD (%)
PF THD (%) PF THD (%)
10 0.981 6.13 0.911 8.72
20 10 0.9910.981 6.13
4.55 0.911 0.983 8.72 4.61
20 0.991 4.55 0.983 4.61
30 0.996 3.18 0.988 3.79
30 0.996 3.18 0.988 3.79
40 0.997 2.67 0.993 3.51
40 0.997 2.67 0.993 3.51
50 50 0.9980.998 2.39
2.39 0.995 0.995 3.31 3.31
60 60 0.9980.998 2.17
2.17 0.997 0.997 3.17 3.17
70 70 0.9980.998 2.08
2.08 0.998 0.998 3.08 3.08
80 80 0.9990.999 2.01
2.01 0.998 0.998 2.91 2.91
90 90 0.9990.999 1.81
1.81 0.998 0.998 2.83 2.83
100 100 0.9990.999 1.76
1.76 0.998 0.998 2.79 2.79

Figure 14. The

Figure 14. The measured
measured PF
PF curve
curve with
with respect
respect to
to the
the overall
overall load
load range
range at
at low
low line
line 115
115 VAC
VAC and
and high
high
line 230 VAC.
line 230 VAC.

As illustrated in Figure 15, the ITHD gains further improvement when applying the functioning
As illustrated in Figure 15, the ITHD gains further improvement when applying the functioning
signals around the zero crossing. The black curve shows the ITHD values with functioning signals
signals around the zero crossing. The black curve shows the ITHD values with functioning signals
applied, while the red curve presents those without functioning signals. Compared to the ITHD
applied, while the red curve presents those without functioning signals. Compared to the ITHD of
of 3.74% under the 230-VAC testing condition of the control strategy without functioning signals,
3.74% under the 230-VAC testing condition of the control strategy without functioning signals, the
the ITHD with offered functioning signals achieves 1.52% at the mid-range of output power and is
ITHD with offered functioning signals achieves 1.52% at the mid-range of output power and is
always smaller than 3% only except at 10% load condition. As the power level is very low, the input
always smaller than 3% only except at 10% load condition. As the power level is very low, the input
of the amplifier for the current measurement is very small, whereby the sensing current signal has a
of the amplifier for the current measurement is very small, whereby the sensing current signal has a
larger error unmatched with the current reference, leading to a higher ITHD value. Such a figure also
larger error unmatched with the current reference, leading to a higher ITHD value. Such a figure also
shows the current spikes at zero crossings notably disappear when applying the functioning signals.
shows the current spikes at zero crossings notably disappear when applying the functioning signals.
Energies 2020, 13, 6297 16 of 18
Energies 2020, 13, x FOR PEER REVIEW 16 of 18

Figure 15. The

Figure15. The measured
measuredharmonic
harmonicdistortion
distortionin
inthe
thecurrent
current(ITHD)
(ITHD)and
andwaveform
waveformcomparisons
comparisonswith
with
both the presence and absence of the functioning signals at the grid voltage zero-crossing zone over
both the presence and absence of the functioning signals at the grid voltage zero-crossing zone over the
full range of load.
the full range of load.

5. Conclusions
5. Conclusions
The proposed solution was implemented by combining hardware and firmware to optimize the
The proposed solution was implemented by combining hardware and firmware to optimize the
performance of the e-mode GaN-based totem-pole PFC rectifier for grid-connected ESS, no longer only
performance of the e-mode GaN-based totem-pole PFC rectifier for grid-connected ESS, no longer
at rated power but also throughout a wide load range. The adopted control structure has the merits of
only at rated power but also throughout a wide load range. The adopted control structure has the
easy implementation, a simple algorithm with a digital controller on the DSP TMS320F28035, which is
merits of easy implementation, a simple algorithm with a digital controller on the DSP
tough to be accomplished with a more intricate model owing to the obligatory calculation attempt.
TMS320F28035, which is tough to be accomplished with a more intricate model owing to the
The analytic and experimental results on a 2.6 kW prototype demonstrated excellent performance
obligatory calculation attempt. The analytic and experimental results on a 2.6 kW prototype
where the power factor can be improved to near unity, the efficiency surpasses 99% over the large load
demonstrated excellent performance where the power factor can be improved to near unity, the
range, and the input current total harmonic distortion reduces to 1.52. The control also diminishes
efficiency surpasses 99% over the large load range, and the input current total harmonic distortion
the component stress during the soft start-up procedure considerably. The steady-state and dynamic
reduces to 1.52. The control also diminishes the component stress during the soft start-up procedure
behaviors proceed at a PCB size of 119 mm × 96 mm and a height of 54 mm to justify the prototype’s
considerably. The steady-state and dynamic behaviors proceed at a PCB size of 119 mm × 96 mm and
feasibility as well.
a height of 54 mm to justify the prototype’s feasibility as well.
Author Contributions:The
AuthorContributions: Theauthor
authorN.-N.D.
N.-N.D.conceived
conceivedthe
thecontrol
controldesign
designmethod,
method,verified
verifiedwith
withsimulation
simulationand
and
experiments, debugged the system and wrote the paper. The author B.-S.H. was responsible for investigating the
experiments, debugged the system and wrote the paper. The author B.-S.H. was responsible for investigating
literature resources, layout and hardware consideration. The author T.-T.N. was responsible for building some
the literature
parts resources,
of hardware layout and
and software, hardware
as well consideration.
as carrying The authorThe
out the experiments. T.-T.N. wasN.-T.P.
authors responsible for building
and J.-H.W. were
some parts for
responsible of hardware
testing theand software,
circuit as well
and data as carrying
acquisition. Theout the experiments.
authors The authors
H.-J.C. and Y.-C.L. N.-T.P.the
supervised and J.-H.W.
research,
provided materialsfor
were responsible for testing
experiments, and reviewed
the circuit and data the paper. AllThe
acquisition. authors haveH.-J.C.
authors read and
andagreed
Y.-C.L.tosupervised
the published
the
version of the manuscript.
research, provided materials for experiments, and reviewed the paper. All authors have read and agreed to the
publishedThis
Funding: version of the
research manuscript.
received no external funding.
Conflicts
Funding:of Interest:
This Thereceived
research authorsno
declare no conflict
external funding.of interest.

Conflicts of Interest: The authors declare no conflict of interest.

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