Single-Stage AC/DC Boost-Forward Converter with

High Power Factor, Regulated Bus and Output

Voltages
Dylan Dah-Chuan Lu
School of Electrical
and Information Engineering,
The University of Sydney, Australia
Herbert Ho-Ching Iu Velibor Pjevalica
School of Electrical, Electronic JP “Srbijagas”, Narodnog Fronta,
and Computer Engineering, 21000 Novi Sad, Serbia
The University of Western Australia, Australia

Abstract— Unlike existing single-stage AC/DC converters with
uncontrolled intermediate bus voltage, a new single-stage AC/DC
converter achieving power factor correction (PFC), intermediate
bus voltage output regulation and output voltage regulation is
proposed. The single power stage circuit is formed by integrating
a boost PFC converter with a two-switch-clamped forward con-
verter. The current stress of the main power switches is reduced
due to separated conduction period of the two source currents
flowing through the power switch. A dual-loop peak current mode
controller is proposed to achieve PFC, and ensure independent
bus voltage and output voltage regulations. Experimental results
on a 24V/100W hardware prototype are given to confirm the
theoretical analysis and performance of the proposed converter.
The converter ranges 86%–92% of conversion efficiency at full
load condition.
I. I NTRODUCTION
Single-stage power-factor-corrected (S2 PFC) AC/DC con-
verters, which combine a power factor correction (PFC) circuit
and a DC/DC regulator circuit, and share a common set of
active power switch(es), have been introduced [1]-[5]. The
aims are to reduce the converter size, control circuitry and thus
cost. Three critical problems are found in S2 PFC converters:
1) Extra current stress on the switch as it has to handle currents
from the line input voltage and the bus voltage simultaneously,
hence lowering conversion efficiency; 2) High voltage stress on
power semiconductor devices due to uncontrolled intermediate
bus voltage; 3) Voltage spike on main switch caused by the
leakage energy for transformer-isolated rear DC/DC stage.
Therefore the S2 PFC approach is only attractive for low power
applications.
Various approaches have been introduced to solve partly
the aforementioned problems [6]-[20]. Variable switching fre-
quency [6]-[7] limits the input power pumping to the bus
capacitor by increasing the switching frequency at decreasing
load, and vice versa. Bulk capacitor voltage feedback [8]-
[10] can effectively reduce the voltage stress by reducing
the charging current in the boost inductor when the load
is decreasing. However, dead angle of input current occurs,
resulting in poor power factor and reduced available power
from the line. By adding a parallel PFC converter with the
diode-capacitor filter, the bus voltage is clamped at the peak
input voltage and input current can be designed to comply with
IEC 61000-3-2 requirement [11]. However, the bus voltage still
varies largely with the input voltage. Therefore the capacitance
has to be large enough for hold-up time requirement at low-
line condition. Load current feedback technique is introduced
[12] in which the load information is brought forward to the
input stage, controlling the input current directly. At any time
the switch handles current from either the line input voltage
or the storage capacitor. However, the high input current
harmonics problem and large variation of bus voltage against
line voltage still exist. Operating both stages in DCM may
reduce the voltage stress but it may not favour high output
current/power applications [9], [13]-[14]. Direct power transfer
is introduced [9]-[19] to place an auxiliary coupled winding
in series with the charging path of boost inductor, “stealing”
energy to output directly after the first power process. The
voltage stress is reduced ripidly while maintaining high power
factor. Conversion efficiency is also improved. But there is no
control of bus voltage against the line voltage. The authors in
[3] and [20] attempted to control the bus voltage and output
voltage in S2 PFC converters but due to the integrated structure,
the currents from both input sources (AC mains and storage
capacitor) cannot be separated. Hence the current stress issue
remains. Moreover, since the duty cycle varies largely for
universal input applications, an extra range switch is needed.
In this paper, a new S2 PFC converter derived from novel
integration of boost converter and two-transistor-clamped for-
ward converter is proposed. In summary, the proposed con-
verter has the following advantages:
• The proposed S2 PFC converter gives simultaneous PFC,
bus voltage regulation and fast output regulation which
are not possible in existing S2 PFC converters.
• No additional switches, such as range switch, are needed
to implement universal input range applications.
• The current stress of the two power switches is lower
than that of the single-switch (or multiple-switch) S2 PFC
converter circuits.
• High power factor as there is no deadband of input current
around the zero crossing of the line input voltage.
• Stand-by mode is possible that saves power.

978-1-4244-3828-0/09/$25.00 ©2009 IEEE 2645


D3
vDS2 6
iD2
D4
S2 D2 N :1
Lo
iL1
- -
ip Lp D5 Co
X A
L1
6 6
iD1
CB
iin  vDS1 T1
|vin | D1 VB
S1 A Q
R2 R1
B E/A 2
Fig. 1. Proposed boost-forward S2 PFC AC/DC converter.
II. P ROPOSED C IRCUIT AND I TS O PERATION
A. Circuit desciption
2 across primary winding of T1 is thus zero (assume D1 has zero
The proposed boost-forward S PFC converter is shown in
Fig. 1. It consists of an input inductor L1 , a two-transistor-
clamped (S1 and S2) forward converter with transformer T1
and a storage capacitor CB . The boost inductor L1 is used to
shape the input current for PFC and to feed CB . Transformer
T1 with turns ratio N : 1 is used to transfer energy from CB
to output load at transistor turn-on period. Bus capacitor CB
serves as a storage element to absorb power imbalance be-
tween input and output and maintain output voltage constant.
Diodes D1 and D2 are used to recycle the leakage energy in
T1 back to CB , provide a path for T1 reset and clamp the
drain-to-source voltages of S2 and S1 to bus voltage VB . D3
is a bypass diode for charging of CB to provide necessary
housekeeping power at start-up. Once VB rises above peak
input voltage, D3 is reverse biased.
B. Circuit operation
To simplify the analysis of operation, it is assumed that all
semiconductor devices are ideal. The capacitances of CB and
Co are so large that the ripple voltage on them are negligible;
VB and Vo are constant dc voltage sources. The rectified
input voltage |vin | is essentially constant within each switching
cycle as the switching frequency fs (= 1/Ts ) is much higher
than the line frequency. Finally, the boost inductor L1 works in
DCM whereas the primary inductance of forward transformer
Lp operates in CCM. The modes of operation is explained as
follows:
Mode 1 (T0 − T1 ): Both the switches S1 and S2 are closed.
As the intermediate bus voltage VB is higher than the rectified
input voltage |vin | at all times, the bridge diodes are reverse
biased in this Mode. Therefore inductor L1 is not charged and
iL1 = 0. Capacitor CB is discharged through S2 − Lp − S1.
Energy is being transferred to output through T1. A voltage
(VB /N − Vo ) is applied on Lo and it is charged up linearly.
This period is for regulation of Vo .
Mode 2 (T1 − T2 ): Mode 2 is initiated by turning off S2
while S1 remains in on-state. The parallel capacitance of S2
is charged up so that the drain-to-source voltage of S2, vDS2 ,
rises towards VB until it is clamped by VB . Because ip cannot
sustain a sudden change of current direction, D1 is turned
Vo
z2
Io
- z1
”1”-D Q S2
E/A 1 vc1
Vref 1 PWM 1 R FF1
Ro Vo
”0”- S
VB 6
CLK
z4
?
”1”-D
B
S1
z3 PWM 2 R FF2
”0”- S
vc2
Vref 2
Fig. 2. Dual-loop current mode controller for the proposed converter.
on to maintain the current flow in T1. The voltage applied
forward voltage drop). Namely, T1 is free-wheeling within this
interval and the rate of change of ip is zero. The secondary
of T1 is also at 0V. Therefore D4 is reverse biased, and D5
conducts to carry the discharge current of Lo . Meanwhile, a
voltage |vin | is applied on L1 and it is charged up linearly.
This period is for PFC and regulation of VB .
In contrast to existing S2 PFC converters, the proposed
converter has separate operation modes (Modes 1 and 2) to
separate currents from input line voltage and bus capacitor.
This reduces current stress on the power switches, as illustrated
in [16].
Mode 3 (T2 − T3 ): Mode 3 begins when S1 is also turned
off. The parallel capacitance of S1 is charged by ip . The
drain-to-source voltage of S1, vDS1 , rises towards VB . When
vDS1 rises slightly above VB , D2 is forward biased. vDS1
is clamped at VB and vDS2 is reduced to VB − |vin |. Diode
D2 provides the path to maintain the discharge current of L1
and energy in L1 is dumped to CB through Lp and D2 . T1 is
reset through the same path. Lo continues to discharge and Co
assists sustaining Vo . This period is for T1 reset and energy
transfer to storage elements.
After some time S1 and S2 turn on again to begin the next
switching cycle, the operation described above will repeat.
III. C ONTROL
Fig. 2 shows the simplified schematic of the proposed
dual-loop current mode control for the proposed converter.
Both loops are triggered by the same clock (CLK) to have
synchronized ON pulse. When a clock pulse is generated, both
S1 and S2 go to high state and CB delivers energy to output
load. The first loop (with E/A 1 and PWM1) is used for output
voltage regulation: the output voltage Vo is sensed by the
inverting input of the error amplifier E/A 1 with compensation
network, and an error control voltage vc1 is generated. vc1 is
compared to the switch current of S1 by comparator PWM 1
to produce desired off duty cycle for S2 through the D-type
flip-flop (FF1). The second loop (with E/A 2 and PWM2) is
used for PFC and bus voltage regulation: the bus voltage VB
is detected by the inverting input of the error amplifier E/A
2 with compensation network, and an error control voltage
2646
 Low input |vin,L | High input |vin,H |
z }| { z }| {
 T -..
.
S1
Gate ... .. -
..
S2 ... ..
.. ..
Gate .. ..
-
-.... D1a T ......
.. .. .. .. .. ..
..-.. ..
.. .. .. D2a T ..
.. .. .. ..
iL1 .. . . .. .. .. ..
..
-.... .... ... ...-...
.. .. ..
...
..
..
. . . -
D1b T D2b T t

Fig. 3. PFC capability under peak current mode control.

Fig. 4. Switching waveforms of iL1 (upper) and iD1 (lower). Scale: 4A/Div,
vc2 is generated. vc2 is summed with the inductor L1 current 4A/Div.
and compared to ground by comparator PWM 2 to produce
desired off duty cycle for S1 through the D-type flip-flop As |vin,H | > |vin,L |, comparing (6) and (7) we can conclude
(FF2). Duration of S1 is longer than that of S2 (Fig. 3). When that iin,H > iin,L . As the instantenous average input current
current flowing through R2 (in Fig. 1), which represents peak follows the input line voltage, the converter achieves PFC
inductor current iL1 , is reached, point B is pull to negative automatically under peak current mode control.
and S1 is turned off. The converter then enters Mode 3.
In the design of the controller, on one hand, the compen- V. E XPERIMENTAL V ERIFICATION
sation network by E/A2 is of slow response, which has the To verify the feasibility of the proposed boost-forward
cut-off frequency of around 10-20Hz, to avoid the 100Hz ac S2 PFC AC/DC converter, a laboratory prototype with the
ripple from bus capacitor being amplified and cause input following specifications has been implemented and tested:
current distortion eventually. On the other hand, E/A1 is of |vin | = 100 - 240Vac; Vo = 24Vdc; Po = 100W; fs =1/T
fast response to provide tight output regulation. = 50kHz. The key circuit parameters are listed as follows:
IV. P OWER FACTOR C ORRECTION C APABILITY L1 =400µH, Lp =750µH, N =4, Lo =800µH, CB =470µF/450V,
Co =4700µF/35V, S1-IRF830, S2-IRF840, D1 =D2 -UF5407,
Let the input line voltage near zero-crossing and near peak
D3 =D4 -BYW29, R1 =R22/2W and R2 =R47/2W.
value be |vin,L | and |vin,H | respectively. The instantaneous
Fig. 4 shows the switching waveforms of inductor current
average input currents, as shown in Fig. 3, at low and high
iL1 (upper) and diode D1 current iD1 (lower). The input
line voltages are given respectively by
voltage and filtered input current of the converter at 240V
|vin,L | and 100V line voltages and at full load condition are shown in
iin,L = D1a T (D1a + D1b ), (1) Figs. 5 and 6 respectively. The measured power factor is above
2L1
0.96 and efficiency of the converter is above 86% at full load
|vin,H | condition, with maximum efficiency of 92%, as shown in Fig.
iin,H = D2a T (D2a + D2b ). (2)
2L1 7. The converter regulates at VB =400V (through Mode 2) and
Because of peak current mode control, the peak input currents Vo =24V (through Mode 1) for entire line and load conditions.
at different input voltages are the same, therefore Finally, Fig. 8 shows that the stand-by mode feature is made
|vin,L | |vin,H | possible in the proposed converter by keeping S2 closed and
D1a = D2a . (3) allowing current from CB to regulate Vo through switching of
2L1 2L1
S1. Once VB is below 350V, S2 is open to allow input current
Applying voltage-second on L1 in both conditions, we get to supply energy to CB .
|vin,L | L1 + Lp
D1b = D1a × , (4) VI. C ONCLUSION
VB − |vin,L | L1
This paper presents with verifications of experimental re-
|vin,H | L1 + Lp sults the single stage PFC (S2 PFC) converter concept - PFC,
D2b = D2a × . (5)
VB − |vin,H | L1 regulation of bus and output voltages at the same time. The
Substituting (4) and (3) into (1), we have key idea is to construct the power circuit so that current
Lp from two input sources (AC main and bus capacitor) can
|vin,H | VB + |vin,L | L1 be separately controlled. Therefore, although the two power
iin,L = D2a T [ ]. (6)
2L1 VB − |vin,L | processing stages share the same power switches, only one of
Similarly, we have the input current for higher line voltage the two currents passes the switches at a time within each
Lp
switching period. Current stress on power switches is also
|vin,H | VB + |vin,H | L1 reduced as a result. Moreover, by deliberatly restricting the
iin,H = D2a T [ ]. (7)
2L1 VB − |vin,H | current from AC main, the converter can work at stand-by

2647

Fig. 5. Input voltage vin and filtered input current iin at 240V(rms) and
full load. Scale: 190V/Div; 0.25A/Div.
Fig. 6. Input voltage vin and filtered input current iin at 100V(rms) and
full load. Scale: 70V/Div; 0.33A/Div.
mode with energy saving, which can hardly be implemented
in existing S2 PFC converters.
R EFERENCES
[1] M. Madigan, R. Erickson, and E. Ismail, “Integrated high quality rectifier
regulators,” in IEEE Power Electronics Specialists Conf., 1992, pp. 1043-
1051.
[2] R. Redl, L. Balogh, and N. O. Sokal, “ A new family of single
stage isolated power factor correctors with fast regulation of the output
voltage,” in IEEE Power Electronics Specialists Conf., 1994, pp. 1137-
1144.
[3] D. M. Divan, G. Venkataramanan, and C. Chen, “ A unity power factor
forward converter,” in IEEE Ind. Appl. Society Annual Meet., 1992,
pp. 666-672.
[4] C. Qiao and K.M. Smedley, “A topology survey of single-stage power
factor corrector with a boost type input-current-shaper,” IEEE Trans.
Power Electron., vol. 16, no. 3, pp. 360-368, May 2001.
[5] T. S. Kim, G. B. Koo, G. W. Moon, and M. J. Youn, “A single-
stage power factor correction AC/DC converter based on zero voltage
switching full bridge topology with two series-connected transformers,”
IEEE Trans. Power Electron., vol. 21, no. 1, pp. 89-97, Jan. 2006.
[6] M. H. L. Chow, Y. S. Lee, and C. K. Tse, “Single-stage single-switch
isolated PFC regulator with unity power factor, fast transient response,
and low-voltage stress,” IEEE Trans. Power Electron., vol. 15, no. 1,
pp. 156-163, Jan. 2000.
[7] M. M. Jovanovic, D. M. C. Tsang, and F. C. Lee, “Reduction of voltage
stress in integrated high-quality rectifier-regulators by variable-frequency
control,” in Proc. IEEE Applied Power Electronics Conf., 1994, pp. 569-
575.
[8] J. Qian, Q. Zhao, and F. C. Lee, “Single-stage single-switch power factor
correction AC/DC converters with dc-bus voltage feedback for universal
line application, ” IEEE Trans. Power Electron., vol. 13, no. 6, pp. 1079-
1088, Nov. 1998.
2648
Fig. 7. Measured power factor and conversion efficiency of the proposed
converter at full load.
Fig. 8. Stand-by mode feature of the proposed converter.
[9] J. Y. Lee, “Single-stage AC/DC converter with input-current dead-zone
control for wide input voltage ranges,” IEEE Trans. Ind. Electron.,
vol. 54, pp. 724-732, Apr. 2007.
[10] L. K. Chang, and H. F. Liu, “A novel forward AC/DC converter
with input current shaping and fast output voltage regulation via reset
winding,” IEEE Trans. Ind. Electron., vol. 52, pp. 125-133, Feb. 2005.
[11] O. Garcia, J. A. Cobos, P. Alou, R. Prieto, and J. Uceda, ”A simple
single-switch single-stage AC/DC converter with fast output voltage
regulation,” in IEEE Power Electronics Specialists Conf., 1999, pp. 111-
116.
[12] Q. Zhao, and F. C. Lee, “Single-switch parallel power factor correction
AC/DC converters with inherent load current feedback,” in IEEE Applied
Power Electronics Conf., 2002, pp. 270-276.
[13] J. L. Lin, W. K. Yao, and S. P. Yang, “Analysis and design for a novel
single-stage high power factor correction diagonal half-bridge forward
AC-DC converter,” IEEE Trans. Power Electron., vol. 53, no. 10, pp.
2274-2286, Oct. 2006.
[14] H. Wei, I. Batarseh, G. Zhu and P. Kornetzky, “A single-switch ac-dc
converter with power factor correction,” IEEE Trans. Power Electron.,
vol. 15, no. 3, pp. 421-430, May 2000.
[15] D.D.C. Lu, D.K.W. Cheng and Y.S. Lee, “Single-stage AC-DC power-
factor-corrected voltage regulator with reduced intermediate bus voltage
stress,” IEE Proc. -Electr. Power Appl., Vol 150, No. 5, pp. 506-514,
September 2003.
[16] D.D.C. Lu, D.K.W. Cheng and Y.S. Lee, “Reduction of current and
voltage stresses in single-stage ac/dc power factor correction converters
with reduced repeated power processing and inherent input current
control,” Journal of Circuits, Systems and Computers, pp. 535-555, Jun.
2004.
[17] S. Luo, W. Qiu, W. Wu, and I. Batarseh, “Flyboost power factor
correction cell and a new family of single-stage AC/DC converters,”
IEEE Trans. Power Electron., vol. 20, no. 1, pp. 25-34, Jan. 2005.
[18] Y. Q. Zheng, and G. Moschopoulos, “Design considerations for a new
ac-dc single stage flyback converter,” in Proc. IEEE Applied Power
Electronics Conf., 2006, pp. 400-406.
[19] A. Lazaro, A. Barrado, M. Sanz, V. Salas, and E. Olias, “New power
factor correction AC-DC converter with reduced storage capacitor volt-
age,” IEEE Trans. Ind. Electron., vol. 54, pp. 384-397, Feb. 2007.
[20] P. L. Wong, and F. C. Lee, “A novel concept in integrating PFC and
DC/DC converters,” in CPES Annual Seminar, 2000, pp. 274-281.