New High Voltage Gain DC-DC Converter Based on
Modified Quasi Z-Source Network
Farhad Abbasi Aghdam Meinagh
Faculty of Electrical and Computer Engineering
University of Tabriz
Tabriz, Iran
f.abbasi93@ms.tabrizu.ac.ir
Abstract—In this paper, a new non-isolated high voltage gain
DC-DC converter using a combination of the modified quasi Z-
Source and switched-capacitor networks is proposed. The
proposed DC-DC converter has an acceptable number of
elements, but achieves the low voltage stresses for its
semiconductors and capacitors. Moreover, the voltage gain of the
proposed converter is significantly high at lower duty cycles
compared to the prior-art converters. In addition, the steady-
state analysis is given along with the passive elements design.
Then, the proposed converter is compared with other converters
to highlight its advantages and drawbacks. Finally, simulation
results in PSCAD/EMTDC are given to validate the theoretical
analysis.
Keywords—Quasi Z-Source; non-isolated DC-DC converter;
high voltage gain; switched-capacitor
I. INTRODUCTION
Renewable energy sources like fuel cells, wind and
photovoltaic (PV) are becoming more popular considering the
disadvantages of fossil fuels. However, typical PV panels can
only provide an output voltage of 12 to 80 V, which is not
desirable in industrial applications with the desired voltage of
200, 400 or 600 V [1, 2]. As a result, high voltage gain DC-DC
converters are essential in the mentioned applications. Isolated
and non-isolated converters are two major categories of the
DC-DC converters. A high-frequency transformer is used in
the isolated DC-DC converters, which provides the galvanic
isolation between the input source and the load. Moreover, a
large turns ratio of the transformer enhances the boosting
capability of the isolated converters [3].
However, the high number of components leads to a high
cost, large volume and low efficiency for the isolated DC-DC
converters. In addition, the saturation possibility for the
transformer is another disadvantage of the isolated converters.
Conventional non-isolated DC-DC converters represent lower
voltage gains compared to the isolated ones. However, non-
isolated converters, usually, have a lower component and a
simpler structure compared to the isolated ones. The major
problem of the non-isolated DC-DC converters is the low
voltage gain, which restricts their applications in industry [4].
Various techniques and topologies have been presented to
increase the voltage gain of the non-isolated DC-DC
converters. Cascaded [5] and voltage-lift techniques [6], using
Jing Yuan, Yongheng Yang
Department of Energy Technology
Aalborg University
Aalborg, Denmark
yua@et.aau.dk, yoy@et.aau.dk
switched-capacitors (SC) [7], switched-inductors (SL) [8] and
multiplier cells [9] are the major methods to increase the
voltage gain. Z-source converters [10] can provide higher
voltage gain compared to the conventional voltage/current-fed
converters. In addition, Z-source-based converters like the
quasi Z-source (qZS) [11], switched-boost (SB) [12] and quasi
switched-boost (qSB) [13] converters have been introduced to
achieve higher voltage gains and power density compared to
the conventional converters. A combination of the mentioned
techniques can further enhance the boosting capability of the
non-isolated DC-DC converters.
For example, the qZS converter and a voltage-lift cell have
been combined in a high voltage gain DC-DC converter in
[14]. However, this converter suffers from high voltage stresses
on the switches and diodes and, also, a high number of the
inductors. The proposed converter in [15] is based on the
combination of the qZS converter and the cascading technique.
The presented converter in [16] uses a qZS network and
voltage multiplier cell to improve the voltage gain. In [17], the
SL network has been combined with the qZS network to
improve the boosting capability. The voltage gain of this
converter has been improved at the cost of high voltage stress
on the semiconductors. Likewise, the SC network has been
combined with the qZS network in [18] to improve the voltage
gain, and however, this improvement is not significant. In [19],
both of the SC and SL networks are employed to improve the
voltage gain of the SB network. The improvement of the
voltage gain in this converter is not remarkable, while it uses a
high number of inductors and diodes. The voltage gain of the
presented DC-DC converter in [20] is the double of the
conventional qZS DC-DC converter. On the other hand, this
topology demands a high number of diodes and capacitors. The
high voltage gain qZS converter in [21] represents low voltage
stresses on its capacitors and a high voltage gain. However, this
topology uses many capacitors and inductors, which will
increase its size, cost, weight and losses. A hybrid Z-source
boost DC-DC converter is presented in [22] with high step-up
capability using qZS networks in its topology. However, this
converter has a large component-count of passive elements.
In this paper, a new non-isolated high voltage gain DC-DC
converter using the combination of the modified quasi Z-
Source network and switched-capacitor cells is thus proposed.
The proposed converter can achieve high voltage gains in
lower duty cycles compared to the prior-art converters. In
   D5   D5
Io Io
I L1   I L1  
C1 L2 C1 L2
I in I in
L1 D1 IL2 L1 D1 IL2
     
 V C2 D2 Co Vo  V C2 D2 Co Vo
 in   in 
S1      
C4 S1 C4
S2  S2 
 
C C
D3  3 D4  3 D4
D3

Fig. 1. Proposed high step-up DC-DC converter. (a)

addition, the voltage stresses on the semiconductors and

  D5
Io
capacitors are low. In this paper, the proposed converter is I L1  
C1 L2
introduced and its steady-state analysis is done in Section II. I in
The passive components design based on the steady-state L1 D1 IL2
  
analysis is done in Section III. The proposed converter is  V C2 D2 Co Vo
 in    
compared with similar converters in Section IV. Finally, the S1 C4
S2 
simulation results are represented in Section V before the
conclusion. 
C
D3  3 D4
II. PROPOSED TOPOLOGY AND ITS OPERATION PRINCIPLE
The proposed topology is shown in Fig. 1. The proposed (b)
converter consists of two main parts: the modified qZS
network and the switched capacitor network. The modified Fig. 2. Equivalent circuits of the proposed high voltage gain DC-DC
converter: (a) Mode 1 and (b) Mode 2.
qZS network is comprised of inductors L1 and L2, capacitors
C1, C2 and C3, diodes D1, D2 and D3, and a switch S1. In
addition, a switch S2, a diode D4 and a capacitor C4 form the average current flowing through L1 and L2, respectively. iC1,
switched-capacitor network. The diode D5 connects the iC2, iC3 and iC4 are the currents flowing through the capacitors
positive terminal of the input voltage to the positive terminal C1, C2, C3 and C4, respectively. Iin is the input current. VS1 and
of the output voltage and Co is the output capacitor. VS2 indicate the voltages across S1 and S2. Also, vD5 is the
voltage across D5.
The proposed converter has two operating modes, and the
equivalent circuit of each operating mode is depicted in Fig. 2. Mode 2 [ t1  t  t2 ]
The operation principle of the proposed converter is detailed
In the second operating mode, S1, S2 and D5 are
in the following.
conducting, while other semiconductors are off. This condition
Mode 1 [ t0  t  t1 ] leads to the charging of L1, L2 and C2, in addition to the
discharging of C1, C3 and C4. The following equations are
The first mode starts by turning off the switches S1, S2, and valid for the second operating mode.
reverses bias of the diode D5. This condition results in forward
bias of diodes D1, D2, D3 and D4. In this mode, L1, L2 and C2 vL1  Vin  VC 3  VC 1 , vL 2  VC 3  VC 2 ,
are discharging, while C1, C3 and C4 are charging. Thus, the    
following equations are obtained. Vo  Vin  VC 3  VC 4

vL1  Vin  VC 2  VC 3 , vL 2  VC 2 iC1   I L1 , iC 2  I L 2 , iC 3   I in  I L 2 ,

   
 iC 4  I L1  I in , I L1  I in  I o
 VC1  VC 2  
V  V The voltages across the non-conducting elements
 C3 C4
expressed as:
 I in  I L1 , iC1  iC 2  I L 2  I L1 ,
    vD1  VC 2  VC1  VC 3
iC 3  iC 4  I L1 
 vD 2  vD 3  VC 3  
vS 1  VC 3 , vS 2  VC 4 v  V
     D4 C4
VD 5  Vin  Vo
where, vD1, vD2, vD3 and vD4 represent the voltages across D1,
where, VC1, VC2, VC3 and VC4 are the average voltages across D2, D3 and D4, respectively. The switching period ends with
C1, C2, C3 and C4, respectively, Vin is the input voltage and Vo turning off the switches. Fig. 3 shows the steady-state
is the output voltage. In addition, VL1 and VL2 are the voltages operating waveforms of the components of the proposed DC-
across L1 and L2, respectively. Moreover, IL1 and IL2 are the DC converter. The switching algorithm of the switches is
  G S 1,S 2 where fs is the switching frequency. Likewise, the current
1
t ripple of the inductor L2 is given as:
VL1
D 1  D 
Vin  VC 1  VC 3
 I L 2  Vin  
Vin  VC 2  VC 3
t L2 f s  1  3 D 
VL 2 Considering KCL in Fig. 1 and the current balance law during
VC 3  VC 2 one switching period for C1 and C2, the average value of
t currents can be expressed as:
VC 2

I L1 G 2Vin GVin 6 1  D 
I L 1,ma x  I L1,ave  I in  I o    Vin  
R R R( 1  3 D )2
I L 1,min
I L2
t  I L 2, ave  I L1, ave  
I L 2 ,max
I L 2 ,min Inductors can then be designed by considering (8), (9), (10),
t
VD1 (11) and the inductor current ripple factor (xL%=∆IL/IL,ave) as:
VC 3  VC 1  VC 2

t RD  1  3 D 
VD 2  L1  2 L2   
VC 3 3 xL1 % f S
VD 3 t

VC 3 B. Capacitor Design
VD 4 t When substituting (5) in IC = CdVC/dt, and considering
VC 4 (10) and (11), the voltage ripple of the capacitors can be
VD 5 t obtained as:
V o  V in
t0 t1 t2
t  3D 1  D   3D 2  4 D  3
1  D  T
VC1  VC 2  Vin
C1or 2 f s R 1  3D 
DT 2

Fig. 3. Steady-state waveforms of the proposed converter. 
 3D 1  D   3D 2  7 D  6 
 
 C3V  Vin  
C3 f s R 1  3D 
2
based on a pulse width modulation (PWM) algorithm. Both of 
switches S1 and S2 have the same gating pulses. Considering 
V  3D 1  D  V
2
the voltage balance law of the inductors during one switching
 C4 f s R 1  3D 
C4 in
cycle and Fig. 3, the average voltages across the capacitors
and the voltage gain of the proposed converter can be asserted 
as follows: The capacitors values can be derived by considering (7), (13)
and the capacitor voltage ripple factor (xC%=∆VC/VC) as:
 D
VC1  VC 2 
1  3D
Vin  3 1  D   3D 2  4 D  3
 C1,2 
 1  xC1,2 % f s R 1  3D 
 VC 3  VC 4  Vin   
 1  3D
 3D 1  D   3D 2  7 D  6 
 Vo 3 1  D   C3   
G    xC 3 % f s R 1  3D 
 Vin 1  3D  3D 2 1  D 
C4 
in which D is the duty cycle and G is the voltage gain. Based  xC 4 % f s R
on the proposed converter voltage gain equation, it is known 
that the proposed converter can achieve high voltage gains in IV. COMPARISON WITH OTHER CONVERTERS
low duty cycles and with low voltage stress on the capacitors.
For better clarification of features and drawbacks of the
III. PASSIVE COMPONENTS DESIGN proposed high step-up DC-DC converter, a comprehensive
comparison is done among the similar structures with almost
A. Inductor Design the same variation range of the duty cycle in Table I. Based on
The current ripple of the inductor L1 can be obtained by Table I, the presented converter in [14] has the lowest number
substituting (1) and (7) in VL = Ldi/dt as: of active elements, while the presented converter in [19] has
the highest number of them. In addition, the presented
2 D 1  D  converters in [19] have the lowest number of passive
 I L 1  Vin   elements. The proposed converter has the third lowest total
L1 f s  1  3 D 
 Vo (V) Vin (V) VS1 (V) 10*IS1 (A)
40  225 100
Normalized Voltage Stress on

[22], three qZS cells

35 [14] 150 75
75 50
Proposed
30 25
[19] 0
Capacitors

[22],two qZS cells 0

25 VC1 (V) VC3 (V)
100 VS2 (V) 10*IS2 (A)
20 75 100
50 75
15 25 50
0
25
10 VC2 (V) VC4 (V) 0
100
5 75 VD1 (V) 10*ID1 (A)
5 10 15 20 100
50
Voltage Gain (G) 25 75
(a) 0 50
100 VL1 (V) 25
Normalized Voltage Stress on

Proposed 150 0
[22], three qZS cells 75 VD2 (V) 10*ID2 (A)
80 [19] 100
Semiconductors

0
[14] 75
[22], two qZS cells VL2 (V) 50
60 100 25
50 0
40 0 VD3 (V) 10*ID3 (A)
-50 100
IL1 (A) 75
20 4.00 50
5 10 15 20 3.50 25
Voltage Gain (G) 3.00 0
2.50
VD4 (V) 10*ID4 (A)
(b) 2.00
100
IL2 (A)
20 75
Proposed 3.20 50
[22], three qZS cells 25
2.80
[19],[14] 0
15 2.40
VD5 (V) 10*ID5 (A)
Voltage Gain (G)

[22], two qZS cells

Iin (A) 200
8.0
150
10 6.0
100
4.0 50
2.0 0
5 0.19060 0.19062 0.19064 0.19060 0.19062 0.19064
Time Time
0 (a) (b)
0 0.05 0.1 0.15 0.2 0.23
Fig. 5. Simulation results of the proposed converter: (a) input and output
Duty Cycle (D)
voltages, voltages across and currents flowing through the inductors, voltages
(c) across the capacitors and (b) input current and voltage stress of the
Fig. 4. Comparison of the parameters for presented converters in Table I: semiconductors.
(a) the normalized total voltage stress on capacitors versus the voltage gain,
(b) the converter voltage gain versus the duty cycle, and (c) the converter proposed converter has the highest voltage gain compared to
voltage gain comparison.
the similar converters except for the duty cycles between 0.22
and 0.25. For the very limited range of duty cycles between
number of elements in Table I. In addition, the presented 0.22 and 0.25, the presented converter in [22] with three qZS
converter in [22] with three qZS cells has the limited variation cells has the highest voltage gain.
range for its duty cycle. Furthermore, the voltage stress of the
capacitors, switches and diodes are compared in Table I. V. SIMULATION RESULTS
In order to verify the proper operation of the proposed high
For better demonstration, the comparison of the voltage voltage gain DC-DC converter, simulations have been carried
gain, the normalized total voltage stress on the capacitors and out in PSCAD/EMTDC. The topology shown in Fig. 1 was
the normalized total voltage stress on the switches and diodes implemented in the simulations with system parameters shown
are shown in Fig. 4. Based on Fig. 4(a) and Table I, the in Table II. Simulation results are shown Fig. 5.
presented converter in [19] has the lowest total voltage stress
on its capacitors in the same voltage gain. The proposed DC- As it is observed in Fig. 5(a), the proposed high voltage
DC converter has the second lowest total voltage stress on the gain converter gives Vo = 239 V, VC1,2 = 20 V, VC3,4 = 99 V,
capacitors. Based on Fig. 4(b) and Table I, the presented which are compatible with the theoretical values obtained from
converter in [14] and the proposed converter have the lowest (7) with values of Vo = 240 V, VC1,2 = 20 V, VC3,4 = 100 V,
and second lowest total voltage stress on their semiconductors, where the input DC voltage is only 40 V. This means that a
respectively. Finally, according to Fig. 4(c) and Table I, the conversion ratio of around 6 is achieved by the proposed DC-
 TABLE I. COMPARISON OF THE SIMILAR HIGH STEP-UP DC-DC CONVERTERS.
[22]
Parameters Proposed converters SL/SC-SBC[19] [14]
Two qZS cells Three qZS cells
2S , 5D ,
1S , 3D , 1S , 4D , 2S , 7D , 1S , 3D ,
Component number 2L , 5C
3L , 5C 4 L , 7C 2 L , 3C 4 L , 4C

GVin DGVin GVin

Switches GVin GVin , GVin
3 1  D  1 D 2

Voltage stress DGVin GVin

GVin ,
, 1 D 2 GVin GVin
Power diodes 3 1  D  GVin GVin ,
DGVin 1 D 2
 G  1Vin 2 1  D 
DGVin
,
3 1  D  DGVin , 2 DGVin 1  2 D  GVin , DGVin DGVin GVin GVin  1  D  GVin
Capacitor voltage , ,
GVin 1  2 D  GVin 1  3D  GVin , 2 DGVin 1 D 2 2 2 1  D 
3 1  D 
Duty cycle variation range 0  D  0.33 0  D  0.33 0  D  0.25 0  D  0.33 0  D  0.33
3 1  D  1 1 2 1  D  2 1  D 
Voltage gain (G)
1  3D 1  3D 1  4D 1  3D 1  3D

DC converter. In addition, it can be further observed in Fig. VI. CONCLUSION

5(a) that the maximum and minimum values of the voltages
across the inductors are equal to VL1,max = 158 V, VL1,min = –39
V, VL2,max = 79 V, VL2,min = –19 V. These values are close to the
theoretical values obtained from the steady state analysis given
in (1) and (4). Moreover, as evidenced in Fig. 5(a), the average
currents through the inductors are IL1,ave = IL2,ave = 2.9 A with
the current ripples being ∆IL1 = 2∆IL2 = 1.2 A. These simulation
results for the currents flowing through the inductors in the
proposed converter are compatible with the theoretical values
IL1,ave = IL2,ave = 3 A and ∆IL1 = 2∆IL2 = 1.28 A, which are
calculated according to Eqs. (8)-(11).
As discussed previously, another merit of the proposed DC-
DC converter is the ability to achieve low voltage stresses on
the power devices. Then, the voltage stresses on the power
semiconductors are presented in Fig. 5(b). According to Fig.
5(b), it can be read that the maximum voltage across the power
semiconductors S1, S2, D1, D2, D3 and D4 is 99 V, while the
voltage stress of the diode D5 is equal to 200 V. Compared to
the calculated theoretical values, i.e., vS1= vS2= vD1= vD2 = vD3=
vD4 = 0.5vD5=100 V, according to (3) and (6), the error is
negligible. Thus, it has been validated that the proposed
converters achieve low voltage stresses on the devices. In all,
the above simulation results have demonstrated the
effectiveness of the proposed converter in terms of high voltage
conversion gain and low voltage stress on power
semiconductors. It could be a promising solution for renewable
energy applications like PV systems.
TABLE II. PARAMETERS OF THE SIMULATION MODEL.
Parameter Value Parameter Value
Vin 40 V L1 & L2 500  H
C1 , , C5 470  F D 0.2
fS 50 kHz R 400 
G 6 Po 144 W
In this paper, a new high step-up DC-DC converter using a
modified quasi Z-Source network and an SC network was
proposed. The proposed converters could achieve high voltage
gains using lower duty cycles compared to the similar
converters. In addition, the proposed converter had an
acceptable number of elements and lower voltage stresses on
its elements. In this paper, the steady-state analysis with the
design procedure was prepared. Then, a comparison with the
similar literature was presented, and the simulation results
verified the advantages and the proper operation of the
proposed converter.
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