DC-DC Converter Based on the Bipolar Boost

Converter and Dickson Voltage Multiplier

Y. Berkovich, B. Axelrod, D. Shoshani Y. Beck

The Faculty of Engineering The Faculty of Engineering
Holon Institute of Technology, Tel Aviv University
Holon, Israel Tel Aviv, Israel
Boris.Axelrod@gmail.com

Abstract— A novel modification of DC-DC converter with a capacitors has been analyzed in [8]. The converter with two
high voltage ratio is proposed. The converter consists of an input levels of the switching frequency has been applied in [14-16],
boost converter, bridge commutator and Dickson voltage however, the practical use of such a scheme is difficult due to
multiplier. The circuit is characterized by a high voltage gain. its complexity.
An important advantage of the circuit is its practically rigid
external characteristic in the continuous current mode (CCM). In the present paper, the scheme of boost converter with a
This is achieved by the absence of active power losses in the change of polarity of the inductor current supplied to the
process of capacitors’ recharging. An additional advantage of the Dickson voltage multiplier is presented. In this case, recharge
proposed scheme is the low required capacitance of the voltage of the capacitors is made not to short circuit but under the
multiplier capacitors A detailed analysis of the proposed action of a current source, which takes the recharge energy and
converters has been produced. The results of theoretical analysis then returns it to the load.
are confirmed by the simulation in MATLAB/SIMULINK.
Circuit verification has been made in a laboratory prototype with II. DC-ANALYSIS
the output power 200W.
Keywords— DC-DC converter; power supply, voltage The proposed circuit (Fig. 2), like the converter described
multiplier. in [8], includes the boost converter and the voltage multiplier.
However, unlike the above converter (Fig. 1), instead of a
single transistor, the proposed circuit includes a controlled
I. INTRODUCTION inverter which reverses the multiplier input current during each
AC-DC and DC-DC voltage converters using multipliers operating period. This avoids the additional power losses by
scheme Dickson or Cockcroft - Walton are widely used in the periodical shorting of the capacitors C1 and C2 of the
various fields of technology, such as power supplies for voltage multiplier. As it was shown in [8], these losses result
medical-use X-ray high power generators, in suppliers of in a significant reduction of the output voltage with increasing
electrostatic filters, in transformerless converters for solar the load current. The proposed scheme allows keeping the
batteries and fuel elements [1-3]. The diode-capacitor voltage rigidity of the external characteristic and the minimum value of
multipliers are simple, reliable and considerably increase the converter inner resistance in the CCM.
output voltage. They can be powered directly from the AC
grid, performing both functions and rectifier and multiplier [1]. C2
+ L
However, it is difficult in this case the use of three-phase D1 D2 D3
Vin S
networks. Moreover, such systems need the large capacitors. C1 C3 Ro
Therefore, in the modern systems the intermediate high
frequency cell is used or in form of inverter [4.5] or in form of
DC-DC converter [6-10]. This allows reducing the capacitance Fig. 1. Converter presented in [8].
of the capacitors and increasing voltage ratio.
In recent years, there have been proposals to use diode- C2
capacitor voltage multipliers in conjunction with the switched- L D1 D2 D3
coupled inductor boost converters [11-13]. In all these cases, S1 S2
the characteristic property of the multipliers is the "softness" of
the output characteristic "current-voltage" caused by the + Vin
D0
C1 C3 Ro Vo
-
increase in inner resistance of the system “power source-
S4 S3
multiplier”. Moreover, this inner resistance leads to additional
losses and reduced efficiency. The mechanism of appearance
the inner resistance and estimation of power loss and additional Fig. 2. Proposed converter.
voltage drop due to the charge and short circuit discharge of the

978-1-5386-3669-5/18/$31.00 ©2018 IEEE

 iC 2 The cyclically switching topologies of the proposed circuit
C2 -
+ V C2 are given in Fig. 3, and the switching diagram is shown in Fig.
L D1 D2 D3
4.
i in S1 S2
C1 C3 Ro
[t0, t1]. (Fig. 3a). A new cycle begins at t0 by turning on the
+ Vin D0 +V +V
Vo
switches S2 and S4. At this time interval current of the inductor
- C1 - C3
- iC 3 L flows through the circuit C1 − D2 − C2 , rest of the diodes are
S4 S3 iC1
“off”. As a result the voltage across the capacitor C1 decreases
a) while the voltage across capacitor C2 - increases. At the same
- time capacitor C3 is discharged through the load. This time
VC2
D1
C2
D2
+
interval ends when the voltages VC1 and VC2 become equal and
L D3
diode D2 is closed.
i in S1 S2
C1 C3 Ro [t1, t2]. (Fig. 3b). At this time interval current of the
D0
+ Vin + V
- C1
+V
- C3 Vo inductor L flows through the diode D0, rest of the diodes are
- “off”, the capacitor C3 is discharged through the load.
S4 S3 iC 3
[t2, t3]. (Fig. 3c). Instead of transistors S2 and S4 start to
b)
conduct transistors S1 and S3. The current of the inductor L
flows via two parallel branches: D1-C1 and C2-D3-C3. As a
C iC 2 result, the voltage across the capacitors C1, C3 increases while
2 -
VC2
+
the voltage across capacitor C2 - decreases.
L D1 D2 D3

i in S1 S2
A. Output–input voltage gain in the continuous current mode
C1 C3 Ro
Vin D0 (CCM)
+ +V
- C1
+
- V C3 Vo
- iC1 iC 3
The main assumptions are as follows:
S4 S3
The ON-state resistance RDS.on of the main switches as well
c) as the forward voltage drops of the diodes are neglected.
Initially we examine the circuit containing 3 diode-
capacitor cells (see Fig. 2).
Fig. 3 Switching topologies of the proposed circuit;
(a)[t0 , t1 ], (b)[t1, t2 ], (c )[t2 , t3 ] . Firstly we obtain the average capacitor voltage VC1.
- for the time intervals t0 – t1 and t1 – t2 - (DTS) :

S2 , S 4 t diL
vL.1 = Vin = L (1)
dt
S1 , S3 t
- for the time interval t2 – t3 ((1-D)TS) :
diL
iin t
vL.2 = Vin − VC1 = L (2)
dt
The volt-second balance for the inductor L :
vC 3
DTS TS

vC1,
vC1
V
0
in dt +  (V
DTS
in − VC1 )dt = 0 (3)
vC 2 , vC 2
vC 3 t gives the expression for the average value of the capacitor
voltage VC1:
t Vin
iC1 VC1 = . (4)
1− D
t Taking into account that
iC 3
t0 t1 t2 t3 VC1 = VC 3 − VC 2 ; VC1 = VC 2
DT (1 − D)T
T we obtain the expression for the output voltage Vo:
2Vin
Fig. 4 Timing diagram of the steady state regime in CCM. Vo = VC 3 = . (5)
1− D
 Finally for n diode-capacitor cells: In this case the volt-second balance for the input inductor:

 n + 1  Vin DTS ( D + D1 )TS

Vo =   (6)
 2  1− D

0
Vin dt + 
DTS
(Vin − VC1 )dt = 0 (7)
This expression does not differ from the corresponding
formula obtained in [8].
gives
However unlike the converter described in [8], the
proposed scheme does not have a short-circuit mode of the  D
input capacitors C1 and C2 . VC1 = Vin  1 + . (8)
 D1 
In Fig. 5, the theoretical DC gain is represented versus duty
cycle D and number of diode capacitor cells n. As it was in the previous case (CCM):

B. Output–input voltage gain in the discontinuous current  D

VC 3 = Vo = 2VC1 = 2Vin  1 +  (9)
mode (DCM)
 D1 
Fig.6 shows the timing diagram in the discontinuous
current mode. Parameter D1 can be obtained based on the following
considerations.
M ( D)
On the one hand, the average value of the load current
Vo
I o.av = (10)
Ro
n=7
On the other hand, the average value of the load current can
n=5 be defined as the average current of the diode D3. Here it
n=3
should be taken into account that iD3 = iL / 2 and
D
I L.max = Vin
D fL
.
So we receive
Fig. 5. DC-gain of the proposed converter versus duty-cycle in CCM.
DD1
I o.av = Vin
4 fL
(11)
Δiin t Comparing (10) and (11) we obtain
iin
t 4Vo fL
vL D1 =
Vin Ro D
(12)
vC 3 Substituting (12) in (9), we receive the required expression
of the voltage ratio as a solution of the quadratic equation
vC1
vC1, Vo R D2
M ( D) = = 1+ 1+ o
vC 2 , vC 2 Vin 2 fL
(13)
vC 3
t
It can be shown that in the general case for n diode-
capacitor cells
iD 3
Vo R D2
D1T M ( D) = = a + a2 + b o
Vin fL
iDo t , (14)
t0 t1 t2 TS
DT (1 − D)T where
T n −1 n −1
1 1
a= ⋅2 2
; b= ⋅2 2
2 n +1
Fig. 6. The timing diagram of the steady state regime in DCM.
 2
n +1 1 V  n +1 
I in = I o = in ⋅   (18)
2 1 − D Ro  1 − D 
C. The boundary between continuous and discontinuous
The same current flows via the diodes of the circuit at the
current modes appropriate time intervals.
The condition of the boundary regime is as follows The maximum voltage on the switches S2 and S4:
1 1 Vin
I in.av = I L.max = ΔiL (15) VS 2, S 4,max = VC1 = (19)
2 2 1− D
Substituting The voltage stresses on the diodes during the appropriate
time intervals are also equal to the voltage VC1=Vin/(1-D).
D
I L.max = Vin During the first time interval takes place the negative
fL
reverse voltage on the switches S1 and S3. Its maximal value is
and equal to the double change of the voltage at each of capacitors
C1 and C2:
V 2 / Ro ( 2Vin /(1 − D) )
2
P 4Vin 1− D
I in.av = o = o = = VS1, S 3.max = 2 ⋅ ΔVC1 = I in.av (20)
Vin Vin Vin Ro (1 − D) 2 Ro fC1
we obtain the following expression defining the transition Since the switches S1, S3 are affected by the negative
boundary from CCM to DCM: reverse voltage, the implementation of the proposed scheme
needs to change. Fig. 7 illustrates two methods for performing
8 fL = (1 − D )2 DRo . (16)
circuit:
In the general case for n diode-capacitor cells a. using transistors MOSFET (Fig. 8a). In this case the
2 first and third arms should include the blocking diodes DS1 and
(n + 1)
fL = (1 − D) 2 DRo (17) DS3.
2
b. using reverse blocking IGBT (Fig. 8b). These transistors
Fig. 7 presents the voltage ratio M = Vo / Vin against take on a reverse voltage.
normalized parameter Ro/fL for different values of duty cycle
in continuous and discontinuous current modes for n = 3 . The
C2
graphics are built according to (5), (13) and (16).
-
+
D1 D2 D3
Next, we determine the maximal currents and voltage L
S1 S2
stresses on the most important elements of the system. C1 C3 Ro
D0
+ V DS1 +
-
+
- Vo
The current I in through the inductance L and through the - in

transistors: S4 S3

DS 3

15
M
a.
D = 0.8 C2 -
+
10 D1 D2 D3
CCM DCM D = 0.6 L
S1 S2
C1 C3 Ro
D0
+ Vin + +
D = 0.4 - - - Vo
5 S4 S3

Ro
ro = b.
fL
0
0 100 200 300 400 500 Fig. 8. Two ways of implementation of the proposed converter.

Fig. 7. Voltage ratio M = Vo / Vin against the normalized parameter Ro/fL1

for D = 0.4; 0.6; 0.8 with the boundary between CCM and DCM for n=3.
 III. SIMULATION REZULTS
iin vGS 3
To verify the results of the analysis of the proposed Vin
converter we have modeled its scheme in
MATLAB/SIMULINK. The circuit parameters were as follow: vGS 4
Vin = 10V ; L = 1mH ; C1 = C2 = C3 = 10 μ F ;
Ro = 50Ω ; f s = 50 kHz
5μs
The appropriate simulation results are shown in Fig. 9.
With the help of this model, the influence of the load
resistance and the capacitance of the multiplier capacitors was a.
checked. As a result, it was found that changing the load and
reducing the capacitance down to C = 0.1μF practically did
not affect the output voltage
5μs
It should be noted that the above theoretical analysis of the
scheme is qualitatively and quantitatively in good agreement
with the results of computer simulation.

IV. EXPERIMENT REZULTS

The proposed converter with n=3 was implemented in the
laboratory. The practical experimental results are given in Fig.
10. The circuit parameters were as follow: b.
Vin = 24V ; Po = 200W ; L = 47 μ H ;
C1 = C2 = 10 μ F ; C3 = 47 μ F ; D = 0.6; f s = 50kHz.
5μs
The switches were of type MOSFET IRF1405 and the
diodes were of type MBR4025.
Fig 10a shows the gate pulses applied to transistors S3 and
S4 , input voltage and input current. Figs 10b and 10c show
maximal voltage stresses across the transistors S4 and S3. Fig.
10c shows the voltage on the capacitor C1.
The output voltage was very close to the theoretical
value Vo = 120V . The efficiency of the converter varied from c.
88% (for Po = 50W ) to 95% (for Po = 200W ).

iin
5μs

iD 0
iD1

vC1

vC 2
d.
Fig. 10. Experimental waveforms of the laboratory model for
vo
Po = 200W ; D = 0.6 : a - input voltage Vin (24V), transistor voltages
vGS 3 , vGS 4 (2V/div) and input current iin (2A/div); b - transistor voltage
vDS 4 (20V/div); c- transistor voltage vDS 3 (2V/div); d -capacitor voltage
vC1 (20V/div).
Fig. 9. The simulation results, input current, diode currents and capacitor
voltages in the steady state CCM regime
Vin = 10V ; D = 0.75; Lin = 1mH ; C1 = C2 = 10μF ; Ro = 50Ω
 V. CONCLUSIONS
The structure of the proposed circuit is quite simple. The
circuit provides a very high voltage ratio and high efficiency.
Minimizing power losses of the converter is realized due to
recharge of the multiplier capacitors by the current of the
source, which returns the recharge energy to the load. It allows
obtaining a rigid external characteristic of the inverter under
load changes. In addition, it is shown that the capacitance of
the multiplier capacitors can be substantially reduced.

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