IET Power Electronics

Research Article

Non-isolated high gain DC–DC converter with ISSN 1755-4535

Received on 11th June 2018
Revised 19th September 2018
low device stress and input current ripple Accepted on 17th October 2018
E-First on 21st November 2018
doi: 10.1049/iet-pel.2018.5556
www.ietdl.org

B. Sri Revathi1, Prabhakar Mahalingam1

1School of Electrical Engineering, Vellore Institute of Technology, Chennai, India
E-mail: prabhakar.m@vit.ac.in

Abstract: In this article, a novel DC–DC converter with high voltage gain capability is presented. The proposed converter is
synthesised from (i) a basic two-phase interleaved boost converter (IBC) which uses coupled inductors (CIs) instead of discrete
inductors and (ii) diode-capacitor multiplier (DCM) cells to achieve higher voltage conversion ratio. The outputs obtained from
the interleaved and the DCM stages are judiciously cascaded with the outputs obtained from the secondary winding of the CIs
to enhance the voltage gain. The input current is almost ripple free due to the adopted interleaving mechanism. As voltage gain
is extended using CIs and DCMs, the voltage stress on the semiconductor devices is minimal and only a fraction (10.5%) of the
output voltage. Experimental results obtained from the 18 V/380 V, 150 W prototype converter, operating at a maximum
efficiency of 94% under full-load condition, validate the proposed concept. Further, practical results obtained under closed-loop
condition confirm that the converter yields a constant output of 380 V DC which is suitable for microgrid application.

1 Introduction
Due to stringent pollution norms, electrical energy conversion from
abundant, non-polluting, and renewable energy sources like
photovoltaic (PV) systems is gaining prominence. An intermediate
high gain DC–DC converter is required to supply the regular loads
from the PV source as the output voltage from the PV panels is
generally less and in the order of 12–60 V [1].
Conventional boost converter (CBC) along with its basic
derivatives like quadratic and cascaded boost converters are not
suitable for high voltage gain applications; the converters suffer
from drawbacks like very high voltage stress on the switch,
extreme duty ratio operation, and its associated diode reverse
recovery problems [2–4].
Generally, non-isolated high gain converters with low input
current ripple are preferred over isolated converters for PV
applications. In [5, 6], numerous solutions to achieve high voltage
gain are reported.
Although interleaved boost converter (IBC) helps in handling
higher power [7] and achieving ripple-free input current [8], its
voltage gain capability is same as CBC. In the modified single-
ended primary-inductor (SEPIC) converter presented in [9],
extreme duty ratio (D) of 0.81 is required to achieve a voltage
conversion ratio of 10. In [10], a non-isolated converter is derived
from conventional flyback converter along with voltage doubler
and clamping diode to reduce switch stress. Converters with dual
switch structure are proposed in [11, 12] to reduce the voltage and
current stress on the power switches.
In switched inductor-based converters proposed in [13, 14], the
switches are operated such that the inductors get connected in
parallel and series during charging and discharging operations,
respectively. However, the voltage stress on the power switches is
relatively higher.
Voltage gain extension using inductor-free options like switched
capacitor (SC), voltage multiplier cell (VMC), and voltage doubler
[15] is available; their voltage gain is moderate. Although IBCs
integrated with VMCs [16, 17] and modified VMCs [18] provide
higher voltage gain, the total component count and consequent
power loss increase when higher voltage conversion ratios (>10)
are required.
Generally, one or more voltage gain techniques are combined
together to achieve high voltage gain [19, 20]. In coupled inductor
(CI)-based converters, the provision to adjust the turns ratio offers
flexibility to extend the voltage gain [21]. Converters with suitable
combinations of CI and SC are proposed in [22, 23] to achieve the
required voltage gain. The additional voltage stress on the switches
caused by the leakage inductance of the CIs is suppressed by
incorporating passive or active lossless clamp circuits to recycle
the energy stored in the leakage inductance [24–27].
A modified version of conventional boost–flyback converter
which uses a CI along with passive snubber is proposed in [28] to
reduce the input current pulsations and voltage stress across output
diode. Voltage multiplier modules comprising of CIs and SCs
along with passive lossless clamping are proposed in [29] to
improve the power conversion efficiency.
Converters using variety of magnetic structures like dual CI
[30] and multi-winding inductors [31] are presented in the
literature. However, owing to manufacturing complexities, these
techniques are rarely used for extending the voltage gain.
This paper introduces a high gain IBC incorporating CIs
combined with diode-capacitor multiplier (DCM) cells. The paper
is organised as follows: Section 1 introduces the proposed
converter while the power circuit description is presented in
Section 2. In Section 3, the operating principle and characteristic
waveforms of proposed converter are detailed. Section 4 presents
the steady-state analysis and design details of the proposed
converter. In Section 5, the experimental results obtained from a
prototype converter which operates under open- and closed-loop
conditions are elaborated. Section 6 discusses the performance
comparison of the proposed converter with few state-of-the-art
converters and conclusions are presented in Section 7.
2 Power circuit description
Fig. 1 shows the power circuit diagram of the proposed converter.
The proposed converter is constructed using a two-phase IBC
which uses CIs instead of simple inductors. As CIs are used, the
required higher voltage gain is obtained by adjusting their turns
ratio (n). DCM cells are connected across each secondary winding.
The two-phase IBC structure reduces the (i) effective input current
ripple and (ii) current stress on the power switch. The voltage gain
obtained from the IBC is further extended by using DCMs. In the
proposed converter, five DCM cells (D1–C1 to D5–C5) are used.
The cumulative output obtained from the DCM cells is stored
across the output capacitor C01. One DCM module (D1S–C1S, D2S–
C2S) is connected across each secondary winding (L1S, L2S) and the

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Fig. 1 Power circuit diagram of the proposed converter
output is connected to individual output capacitors C02 and C03. All
the three output capacitors C01, C02, and C03 are connected in
series to achieve higher output voltage.
3 Operating principle of the proposed converter
The operating principle of the proposed converter during one
complete switching cycle is explained using four modes. The
proposed converter is built from the basic two-phase IBC.
Therefore, switches S1 and S2 are operated with a phase shift of
180° between them. Further, in the proposed converter, as the duty
ratio (D) is >0.5 (D = 0.55), both the switches remain in the ON
state for some time interval. The power circuit operation is easily
and clearly explained with the following valid assumptions:
i. All the passive elements and semiconductor devices are ideal.
ii. The converter operates in continuous conduction mode (CCM)
and the input current is continuous.
iii. The primary winding L1P and L2P of the CIs are precharged
before turning ON the circuit.
Mode 1: (t0 − t1)
During Mode 1, at t0, both the switches S1 and S2 are turned
ON. The input current flows into the switches through the primary
winding (L1P and L2P) of the CIs. Current through L1P and L2P
increases linearly and aids in storing energy across them.
Resultantly, the voltage across the primary windings L1P and L2P
starts building up towards Vin. The diodes located in the DCM cells
remain in OFF state. Diodes D1S and D2S which are connected
across the secondary winding of CIs are turned ON and OFF,
respectively. The load demand is taken care by the output
capacitors C01, C02, and C03.
The equations governing Mode 1 are given by
1 In the secondary side of the CIs, energy stored in L1S and C1S is
iL1P(t) = v t (1)
L1P L1P
1 discharges completely to bring its current magnitude to IL1P, min.
iL2P(t) = v t (2)
L2P L2P
At instant t = t1, L2P is completely charged; current through L2P
reaches its maximum value IL2P, max and marks the end of Mode 1.
Mode 2: (t1 − t2)
Mode 2 commences at time t = t1 when the switch S2 is turned
OFF so as to transfer the energy stored in L2P and DCM capacitors
C2, C4 to the load. The energy stored in L2P forward biases diodes
D1, D3, and D5 of the DCM cell and charges the capacitors C1,
C3, and C5. Since switch S1 is still conducting, the primary
2554
winding L1P continues to charge towards the input voltage. The
rate of current rise through L1P is same as the rate of fall in current
through L2P. Current through the primary winding of the CIs is
expressed as follows:
iL1P(t) = iS1(t) − iC1(t) (3)
vin + vC2 + vC4 − vC01
iL2P(t) = t (4)
L2P
Diode D01 conducts and charges the output capacitor C01. In the
secondary winding L1S, diode D1S is forward-biased and charges
C1S. The energy stored across L2S and capacitor C2S is transferred
through diode D03 to charge the output capacitor C03 while diode
D2S remains in OFF state.
In the DCM cells, current through diode D1 is given by
iD1(t) = iL2P(t) − iC2(t) (5)
At time t = t2, Mode 2 comes to an end when inductor L2P is
completely discharged so that current through it reaches its
minimum value IL2P, min and switch S2 is turned ON again.
Mode 3: (t2 − t3)
During Mode 3, switch S2 is turned ON at time t = t2 and both
S1 and S2 conduct. The stored energy across the primary windings
L1P and L2P of the CIs rises linearly. As both L1P and L2P continue
to store energy, the diodes in the DCM cells remain reverse-biased.
At time instant t = t3, the secondary winding L1S is completely
charged and reaches its maximum value which is given by iL1P, max.
Capacitor C1S is also completely charged and is ready to discharge
to the output capacitor C02 through the diode D02. The load
demand is met by the voltage across the output capacitors C01−C03.
Mode 3 ends at time t = t3. The equations that govern Mode 3 are
expressed as follows:
1
iL1S(t) = iD1S(t) = i (t) (6)
n L1P
vL2S(t) + vC2S(t) = vC03(t) (7)
Mode 4: (t3 − t4)
In Mode 4, at time t = t3, S 1 is turned OFF and S2 remains in its
ON state. Therefore, primary winding L1P starts discharging its
stored energy to the output capacitor C01 through the DCM
capacitors C1, C3, and C5. Hence, the odd numbered diodes in the
DCM cells (D1, D3, and D5) are reverse-biased. As S2 is ON, L2P
continues to store energy while the DCM capacitors C2 and C4
acquire charge through the even numbered diodes D2 and D4.
Current flowing through L1P is given by
vin + vC1 + vC3 + vC5 − vC01
iL1P(t) = t (8)
L1P
transferred to the output capacitor C02 while current flows through
L2S and diode D1S to charge C2S. At time t = t4, inductor L1P
During Mode 4, the governing equations are expressed as follows:
iL2P(t) = iS2(t) − iC2(t) (9)
1
iL2S(t) = iD2S(t) = i (t) (10)
n L2P
vL1S(t) + vC1S(t) = vC02(t) (11)
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 Fig. 3 Characteristic waveforms of proposed high gain DC–DC converter

Figs. 2a–c show the equivalent circuit of the proposed converter

during various operating modes while the characteristic waveforms
of the key circuit parameters are depicted in Fig. 3.

4 Steady-state analysis and design details

4.1 Voltage gain
The voltage gain of the proposed converter is obtained from the
output voltage which is given by

V 0 = V C01 + V C02 + V C03 (12)

By applying Kirchhoff's voltage law around the loops involving the

DCM capacitors and by back substitution, the voltage that is
developed across C01 is derived. Intuitively, the voltage appearing
Fig. 2 Equivalent circuit during across C01 is the sum of voltage outputs obtained from interleaved
(a) Mode 1 and Mode 3, (b) Mode 2 and (c) Mode 4 stage and the gain extension provided by the DCM cells. Hence,
voltage across C01 is given by
Time instant t4 marks the end of Mode 4 and one operating cycle.
Next switching cycle commences when S1 is turned ON again to 1+N
V C01 = V (13)
charge the primary winding L1P. 1 − D in

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where N is the number of DCM cells and D is the duty ratio of the In the DCM cells, the current stress on the diodes reduces
switches. progressively when traversed from input to output port. In general,
Capacitors C02 and C03 acquire their charge from the secondary the current rating of the diode present in xth DCM cell is expressed
winding of the CIs. Therefore, voltage developed across C02 and as
C03 is expressed as
1−D
IDx = I (23)
nk 1 + x + 2nk in
V C02 = V C03 = V (14)
1 − D in
Current through the output diode D01 is given by
where k is the coupling coefficient of the CIs.
Substituting (13) and (14) in (12), the voltage gain (M) of the 1−D
ID01 = I (24)
proposed converter is derived as 1 + N in

1 + N + 2nk Since the output diodes D02 and D03 are connected across the
M= (15)
1−D secondary winding of the CIs, their current rating is expressed as

4.2 Voltage stress on the switches 1−D

ID02 = ID03 = I (25)
nk in
In the proposed converter, the switches which are located in the
interleaved stage experience a voltage stress which is similar to 4.5 Design of inductor and capacitor
that of a CBC. Therefore, the voltage stress on S1 and S2 is given
by The inductor and capacitor values are determined from the current
and voltage ripple magnitudes, respectively.
1 In the proposed converter, the primary winding of the CIs is
V S1 = V S2 = V (16) used to obtain a two-phase IBC. The primary inductance values are
1 − D in
designed using (26).
Alternatively, considering the output voltage obtained from the
interleaved stage, the voltage stress is expressed as V inD
Lpy = L1P = L2P = (26)
2 f Δiin
V C01 1
V S1 = V S2 = = V (17) The turns ratio of the CIs is obtained from (27) using which the
N (1 + N + 2nk) 0
inductance value of the secondary winding is computed.
4.3 Voltage stress on diodes
M(1 − D) − 1 − N
n= (27)
The voltage rating of the diodes is obtained by determining the 2k
reverse voltage impressed across them. The magnitude of reverse
voltage is given by the potential difference between two DCM Lsy = n2Lpy (28)
capacitors which are connected across the anode and cathode
terminals of each diode. Therefore, diodes D1–D5 are subjected to In the proposed converter, depending on the ideal voltage gain, the
equal voltage stress magnitudes given by actual turns ratio value is determined to be n = 2.2 as shown in
Fig. 4a. Due to leakage inductance, the coupling coefficient k is
2 2 always <1. As the value of k impacts the voltage gain and voltage
V DDCM = V D1 − D5 = V = V (18)
1 − D in 1 + N + 2nk 0 stress on the diodes, a plot of M versus D is obtained and shown in
Fig. 4b. The practical value of k is experimentally found out to be
Voltage stress on output diode D01 is given by 0.875. The impact of k = 0.875 on the reduction in voltage gain is
negligible when compared to k = 1. Thus, the switches used in the
N 1 proposed converter are practically operated at D = 0.55 and the CIs
V D01 = V C01 − V = V (19)
1 − D in 1 + N + 2nk 0 are wound for a turns ratio of n = 2.2 with a coupling efficient of k
= 0.875.
Output diodes D02 and D03 are located at the secondary side of the The value of output capacitances is obtained from the load
CIs. Their voltage rating is given by current and voltage ripple appearing across the individual yth
capacitor and expressed in (29).
nk nk
V D02 = V D03 = V = V (20) I0D
1 − D in 1 + N + 2nk 0 C01 = C02 = C03 = (29)
f ΔvC0y
Multiplier diodes D1S and D2S are connected between the
secondary winding and multiplier capacitors C1S and C2S. The value of DCM capacitances is also obtained by considering the
Therefore, their voltage stress value is obtained as current through each DCM cell and voltage ripple impressed across
the individual DCM capacitor.
nk nk
V D1S = V D2S = V = V (21)
1 − D in 1 + N + 2nk 0 5 Hardware results and discussion
A prototype version of the proposed high gain DC–DC converter is
4.4 Current stress on switches and diodes fabricated and experimented to validate the proposed hypothesis.
The switches share the total input current due to the adopted Table 1 provides the specifications of the prototype converter while
interleaved structure. Since a two-phase IBC is used in the the component details are provided in Table 2. Gate pulses to
proposed converter, the current rating of the switches is expressed switches S1 and S2 are obtained by suitably programming an
as Arduino Due micro-controller. IRF25600 dual MOSFET driver is
used to amplify the gate pulses obtained from the microcontroller
Iin and applied to the power switches S1 and S2. Tektronix
IS1 = IS2 = (22) (TPS2024B) four-channel digital storage oscilloscope (DSO) along
2
with high voltage (P5210) and current probes (A622) is employed

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Fig. 4 Voltage gain plot of the proposed converter
(a) For various values of turns ratio n, (b) When coupling coefficient k varies with n =
2.2
Fig. 5 Experimental results obtained from the prototype version of the
to capture the required voltage and current waveforms at proposed converter
appropriate junctures. (a) Waveforms demonstrating the voltage conversion ratio; CH1: input voltage, CH2,
Fig. 5a shows the waveforms of input voltage (CH1), gate CH3: gate pulse of S1, S2, respectively, and CH4: output voltage, (b) Voltage
pulses to S1, S2 (CH2, CH3), and the output voltage (CH4) waveforms across the input port (CH1) and output capacitors C01–C03 (CH2–CH4,
obtained during experimentation. When the switches of the respectively)
proposed converter are switched at 50 kHz with a duty ratio of D =
0.55, the converter yields the desired 380 V output from the DCMs is incorporated, the proposed converter yields the required
specified 18 V input. Thus, the voltage conversion ratio of 21.11 is voltage gain (21.11) at a safe duty ratio of D = 0.55.
verified. Since an appropriate gain extension concept using CIs and Fig. 5b shows the voltage waveforms obtained at the input port
(CH1) and at various output stages which are same as the voltage
developed across the output capacitors C01 to C03 (CH2–CH4).
Table 1 Specifications of the proposed converter The voltage waveforms obtained from the oscilloscope match very
Parameter Value closely with the design values obtained using the analytical
input voltage (Vin) 14–25 V expressions (13) and (14).
output voltage (V0) 380 V As polypropylene (film) capacitors with low equivalent series
resistance (ESR) are used in DCM cells, the total voltage drop
output power (P0) 150 W across the DCM stage alone is reduced. Further, ripple-free DC
switching frequency (f) 50 kHz voltages obtained across the output capacitors confirm the design
primary winding inductance (L1P, L2P) 80 μH methodology adopted to obtain the value of various capacitances.
coupling coefficient (k) 0.875 Fig. 6a shows the expected complimentary operation of the
switches and the voltage stress experienced by them as compared
turns ratio (n) 2.2
with the output voltage. The magnitude of the voltage stress is in
duty ratio (D) 0.55 perfect agreement with the theoretical value obtained using (16).

Table 2 Details of components used in the prototype

Circuit element
switches S1, S2
diodes D1–D5, D1S–D2S, D01–D03
DCM capacitors C1–C5, C1S–C2S
output capacitors C01–C03
Device type
MOSFET (2 nos.)
fast recovery diodes (10 nos.)
polypropylene capacitors (7 nos.)
electrolytic capacitors (3 nos.)
Part no. (ratings)
PSMN9R5-100PS (100 V, 89 A, 8.16 mΩ)
HTG5U100 (100 V, 5 A, 0.65 V)
ECW-FD2W475J (4.7 μF/450 V)
EEU-EB2E470 (47 μF/250 V)

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Fig. 6 Experimental waveforms to validate (a)–(c) voltage stress on the switches and diodes and (d) current through the input port and primary windings
(a) Waveforms validating the voltage stress on the switches; CH1: voltage across S1, CH2: voltage across S2, and CH3: output voltage, (b) Voltage stress waveforms on D1 and D2;
CH1: gate pulse to S1, CH2, CH3: voltage across D1 and D2, respectively, and CH4: output voltage, (c) Input voltage waveform (CH1), voltage across D1S (CH2), D2S (CH3), and
the output (CH4), (d) Waveforms corresponding to current through the primary winding of CIs (CH1, CH2) and input (CH3)

The voltage spikes observed in the waveforms are due to the
leakage inductance of the CIs. However, the magnitude of the
spikes are within safe limits and do not damage the switches. The
voltage stress on the DCM diodes D1, D2 and the secondary side
of the CIs (D1S and D2S) are depicted in Figs. 6b and c,
respectively.
To easily understand the operation of DCM cell and clearly
correlate the voltage impressed across the diodes, pulse applied to
S1 (CH1) and output voltage (CH4) are also captured and depicted
in Figs. 6b and c. As observed in Fig. 6b, diode D1 turns ON when
S1 is turned ON while D2 is in the reverse-biased condition. In
percentage terms, the voltage stress on the diodes works out to
21% of the output voltage.
From Fig. 6c, the complimentary behaviour of diodes D1S and
D2S is observed. Further, the voltage stress on both the diodes is
equal to twice the output voltage obtainable from a CBC. As the
diodes D1S and D2S are located in the secondary side of the CIs,
their voltage stress magnitude is determined by the turns ratio and
coupling coefficient of the CIs. In the proposed converter, CIs are
designed with turns ratio n = 2.2 and coupling coefficient k = 0.875.
The experimental value of voltage stress impressed on D1S and D2S
clearly validates the proposed concept. Since the duty ratio of the
switches and turns ratio value of the CIs is normal (not too high),
the voltage stress value of D1S and D2S is also less and only about
20% of the output voltage.
Fig. 6d shows the experimental waveforms of current through
the primary winding of the CIs (L1P and L2P) along with the input
current. The phase displacement and magnitude of the current
through the primary windings validate the current sharing
mechanism achieved using the interleaved stage. Further, the
current through the individual primary winding is just about
discontinuous while the total input current (which is the sum of the
two individual inductor currents) is clearly continuous with
reduced ripple content (25% of input current). Thus, when
interleaving technique is employed, smaller inductance values with
lower current ratings are sufficient to meet the required (higher)
input current rating with less ripple.
Figs. 7a–c show the practical voltage and current waveforms
which are obtained at the input and output ports under various load
conditions. From Fig. 7a, the efficiency under full load condition is
computed as 94%. Use of MOSFETs with lower voltage ratings,
diodes with reduced ON state voltage drop, and polypropylene
capacitors with low ESR results in the converter operating at good
efficiency. When the converter operates at slightly over load
condition (116.66% of full load, 175 W), the voltage drop
occurring across the diodes and stray resistance of the CIs cause
reduction in the output voltage; V0 reduces to 368 V as shown in
Fig. 7b. The efficiency of the proposed converter under slightly
overloaded condition works out to 90.7%.
When the load on the proposed converter is reduced to 135 W
(90% of full load), the output voltage rises to 400 V and efficiency
value is about 92% (Fig. 7c). As the input current magnitude is
lower at lightly loaded condition, the voltage drop on the diodes
and the stray resistance of the CIs are also reduced. Hence, the

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Fig. 7 Practical voltage and current waveforms obtained at the input and output ports under various load conditions and efficiency values
(a) Full load condition; input voltage (CH1), input current (CH2), output voltage (CH3), and output current (CH4), (b) Overload condition (116.66% of full load), (c) Light load
condition (90% of full load)

output voltage shoots up to 400 V and results in better power
conversion efficiency value as compared to over load condition.
The loss occurring across various elements employed in the
proposed converter is computed using (30)–(32).
2
Pswitch_loss = Iswitch_RMS × Rswitch_ON + Pswitch_ON
+ Pswitch_OFF
2
Pdiode_loss = V diode_ON × Idiode_Avg + Idiode_RMS × Rdiode
2
PCI_loss = Ipy 2
× Rpy + Isy × Rsy + Piron
Parameters like Vdiode_ON, Rdiode, and Piron are obtained from the
manufacturers' datasheets and the loss across individual
components is computed. Fig. 8a shows the loss distribution profile
of the proposed high gain DC–DC converter under full-load
condition.
Due to the gain extension technique employed, the conduction
loss on the switches is less and about 17% of total loss. The
cumulative loss occurring across all the diodes is about 23.56% of
the total loss. The power loss occurring across the CIs is mainly
due to the stray resistance of the windings and the power loss in the
magnetic core. As the CIs are designed to extend the voltage gain,
they carry more current; the stray resistive loss is higher and is
reflected as the major loss contributor (28.56% of total loss). The
loss due to ESR of capacitors, the stray resistance of the tracks
used in the printed circuit board (PCB), and conducting wires are
minimum and account for 3.33% of the total loss. The total loss
(Ptotal_loss) occurring in the proposed converter is obtained by
summing up all the individual power losses expressed in (30)–(32).
From the values of output voltage V0, output current I0, and total
power loss, theoretical efficiency (η) is obtained using (33).
V 0 × I0
η= × 100% (33)
(V 0 × I0) + Ptotal_loss
(30)
Fig. 8b shows the efficiency curve of the proposed converter
(31) obtained during simulation and experimentation. The analytical
values match very closely with the values obtained through
(32) experiments.
When the load on the proposed converter is varied from 90 to
116% of full load, the variation in output voltage is about 3.5 to
5.2% of the rated value. To regulate the output voltage and
maintain it constant at 380 V, closed loop is implemented. The
actual value of output voltage is suitably sensed using a simple
potential divider network and applied as feedback to the
microcontroller. Based on the load current and line (input) voltage
variations, the duty ratio of S1 and S2 is suitably adjusted to
maintain the output voltage at 380 V. Figs. 9a and b show the
regulated output voltage when the load current and line voltage
magnitudes, respectively, undergo a step change. Due to the
implementation of closed-loop control, the output voltage is
quickly regulated and the output voltage is restored to the nominal
value within a very short time. Figs. 9c and d, respectively, depict
the photographs of the prototype converter and the complete
experimental set-up.

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Fig. 8 Loss distribution profile under full-load condition and efficiency curve of the proposed converter
(a) Power loss occurring across the elements used in the proposed converter, (b) Efficiency curve under simulation and experimentation

Fig. 9 Experimental waveforms demonstrating the closed-loop response of the proposed converter and photographs
(a) Output voltage (CH1) remains constant when load current (CH2) varies, (b) Soft start-up and dynamic response when input voltage (CH1) is varied from 11.8 to 21.2 V; output
voltage (CH3) settles down quickly to the desired value (380 V) with very low undershoot and overshoot, (c) Photograph of the proposed converter, and (d) Photograph of the
experimental set-up

6 Performance analysis and comparison with 6.1 Voltage gain

some existing state-of-the-art converters
To appreciate the beneficial features of the proposed converter,
some of its key performance attributes are benchmarked with
similar state of the art converters which are presented in [25–28].
Table 3 provides the details of the attributes which are compared.
The proposed converter offers the highest voltage gain when
compared to some similar state of the art converters.
Moreover, the voltage gain of the proposed converter is at least
twice the maximum voltage conversion ratio offered by the
converter presented in [25]. Although all the converters considered
for comparison use CIs, the structure of the proposed converter and
adopted the gain extension technique results in the highest voltage

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© The Institution of Engineering and Technology 2018
Table 3 Comparison of proposed converter with existing converters
Attributes Converters presented in references
[25] [26] [27] [28] Proposed
input voltage (Vin), volts 20 25 20 30 18
output voltage (V0), volts 200 200 190 200 380
voltage gain (M) 10 8 9.5 6.66 21.11
duty ratio (D) 0.51 0.65 0.64 0.47 0.55
no. of magnetic elements 1 CI 2 (1 simple inductor 1CI 2 (3 winding CI and 2 CI
and 1 CI) simple inductor)
turns ratio of CIs (n) 2 3 1.8 1.5, 4 2.2
no. of diodes employed 4 3 3 3 10
no. of capacitors used 4 4 3 4 10
total component count (TCC) 10 10 8 10 24
M/TCC 1 0.8 1.1875 0.66 0.879
voltage stress on switches as percentage of V0 20 25 26.3 28 10.5
(Vsw)
voltage stress on diodes as percentage of V0 33.3 75 73.68 42.45 20.3
(Vdiode)
M/Vsw 0.5 0.32 0.361 0.237 2.10
M/Vdiode 0.3 0.106 0.129 0.156 10.39
gain extension technique CI and voltage voltage doubler and CI CI and SC CI and integrated flyback CI and DCM
multiplier

Fig. 10 Performance plots of the proposed converter

(a) Voltage gain comparison, (b) Radial chart demonstrating the superior features of proposed converter as compared to some existing converters

gain of 21.11. Fig. 10a shows the voltage gain characteristics of all
the converters considered for comparison.
6.2 Voltage stress on the switches
In the proposed converter, two switches are used to form the basic
two-phase IBC. As the switches are located nearer to the input side,
their voltage stress magnitude is greatly reduced. In fact, the
voltage stress experienced by the switches is equal to that of the
switch used in CBC. Resultantly, though the output port is at a
higher voltage level (380 V), the voltage stress impressed on the
switches is just about 10.5% of the output voltage. Incidentally, the
switches used in all the other converters considered for comparison
are also subjected to a reduced voltage stress magnitude only.
To appreciate the steep reduction in the switch voltage stress
magnitude, ratio of voltage gain to the magnitude of switch voltage
stress (expressed as percentage of V0) is obtained and is denoted as
M/Vsw. The proposed converter offers the highest M/Vsw value.
Since the proposed converter yields the highest voltage gain with
least voltage stress impressed on the switches, the highest M/Vsw
value is obtained. In fact, the M/Vsw value is about ten times higher
than the converter presented in [28]. The M/Vsw value for the
converter presented in [25] is 0.5; the M/Vsw value of the proposed
converter is four times higher. Thus, the ability of the developed
converter to yield a very high voltage gain with low voltage stress
on the switches is clearly demonstrated.
6.3 Voltage stress on the diodes
The diodes employed in the proposed converter are subjected to the
least voltage stress due to the gain extension (DCM) technique.
The diodes used in [26, 27] experience the highest voltage stress
which is about three-fourths of the output voltage magnitude.
In the proposed converter, diodes D1S and D2S which are
located at the secondary side of the CIs and closer to the output
port experience a relatively higher voltage stress. However, as the
turns ratio of the CIs is only 2.2, the voltage stress on D1S and D2S
is reduced. Further, majority of the diodes are located in the DCM
cells and are subjected to a reduced voltage stress which is about
20.3% of V0 only. The ratio of voltage gain to percentage voltage
stress on the diodes (M/Vdiode) clearly indicates the reduced voltage
stress impressed on the diodes at high voltage gain value. Thus, the
adoption of the DCM cells as a gain extension mechanism to
achieve higher voltage gain with reduced voltage stress on the
semiconductor devices is validated. Fig. 10b demonstrates the

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© The Institution of Engineering and Technology 2018
superior features of the proposed converter when compared to
some existing state-of-the-art converters.
6.4 Total component count (TCC) and M/TCC ratio
The converter presented in [27] uses the least number of
components while the proposed converter uses maximum number
of components. The use of more components in the proposed
converter is acceptable when the M/TCC value is observed. The
M/TCC value of the proposed converter is pretty close to the
highest value of 1.1875 obtained in [27] and justifies the
employment of maximum components.
7 Conclusion
In this paper, a non-isolated high gain DC–DC converter which is
synthesised from an IBC and employs CIs and DCM cells to
extend the voltage gain is implemented. The converter yields a
practical voltage conversion ratio of 21.11. The proposed converter
operates at a maximum efficiency of 94% when delivering 150 W
power to the output (full-load condition). The basic IBC structure
used in the proposed converter aids in sharing the current through
the switches and reducing the input current ripple to 25% of the
total input current. The output voltage obtained from the converter
is regulated by implementing a closed loop.
Hence, a constant voltage of 380 V is obtained at the output
terminals even when the input voltage and load current change.
The significant advantages of the proposed converter are its ability
to (i) provide high voltage gain (21.11) at safe duty ratio (D =
0.55), (ii) yield the high voltage gain value with low voltage stress
on the switches and diodes (10.5 and 20.3% of output voltage,
respectively), (iii) operate with low input current ripple (25% of
Iin), and (iv) provide regulated (constant) output voltage when
input voltage and output current change. The beneficial features of
the proposed converter and its ability to provide a regulated output
voltage make it a good choice for DC microgrid application.
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© The Institution of Engineering and Technology 2018