2014 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES)

Design and Analysis of a High Gain Boost

Converter
Mummadi Veerachary
Dept. of Electrical Engineering, IIT Delhi, New Delhi, India
E-mail: mvchary@ee.iitd.ac.in

Abstract— A high gain boost converter is proposed in this paper.
This converter belongs to two switch topology and is capable of
giving a higher voltage gain at moderate duty ratios. Although it
is two switch topology, but they are controlled synchronously
and hence single pulse width modulated signal is sufficient
enough to control the power processing. Through steady-state
analysis various parameter design expressions are formulated.
State-space and discrete-time models are formulated for
dynamical characterization of the proposed converter. A digital
controller is designed to ensure 100 V for point of load
applications. A 24 to 100 V, 100 Watt prototype is considered,
both in analysis and simulation, for verification of the proposed
topology. Analysis and simulation results are in close agreement
with each other.
keywords: Boost Converter, Digital Controller, Fifth-order boost
converter, Voltage Regulation, Voltage-mode Controller.
I. INTRODUCTION
Boosting of voltage, from a low battery, is required to drive
several point of load applications and also to obtain enough
power at a pre-specified voltage magnitudes. Simple single-
switch boost converter is capable of delivering higher load
voltage from a low voltage battery, but it is at the cost of
lower efficiency. Even if efficiency is not the desirable
feature, excessive boosting is difficult to realize at higher
loads. Reasons for inferior performance of the conventional
boost converter are: (i) voltage gain penalization on account
of non-idealities, particularly at higher loads, (ii) extreme
duty ratio operation, for realizing larger voltage gain,
deteriorates efficiency, (iii) higher switching losses may
reduce its efficiency, (iv) larger duty ratios of active switch is
responsible for shorter conduction time of the output rectifier
diode and thus results in reverse recovery issues, (v) higher
power rating device is needed in larger boosting applications
and the corresponding FET-family device exhibits larger ON-
state resistance, and (vi) more ripple current on load side of
the converter, etc.
modulated (PWM) converters belonging to boost family are
reported in literature[1].
Several transformerless DC-DC converters were reported
and few of them are: (i) cascaded form of boost structures [3],
(ii) the quadratic topologies [4], (iii) the switched-inductor/
switched-capacitor type [5]-[6], (iv) the voltage-lift type, (v)
topologies with embedded voltage doublers [7]-[8], and (vi)
multiplier based topologies [12], etc. These topologies able to
provide higher gain than the conventional boost converter,
but at moderate duty ratio the achievable gain is combatively
on lower side. Extensive work on coupled inductor based
topologies [9] has been reported, but here higher switch stress
is the limiting factor. A step-up converter [10] based on the
combination of KY converter synchronously rectified buck-
boost converter is reported. Although, this topology yields
lower ripple current on load side together with voltage
boosting at low duty ratio, but the amount of boosting is
comparatively on lower side. Several higher order boost dc-
dc converters, 4th ~ 8th-order family, have been reported in the
open literature [3]-[4]. Key features of these topologies are:
(a) lower ripples (current/ voltage) on either side of the
converter, (b) reduced size of energy storage elements, and
(c) enhanced dynamic performance, etc. Hybrid versions of
switched-capacitor and couple inductor based topologies have
been reported in the literature, but the input current of these
topologies is no longer continuous. Such solutions needing a
larger input filters. In addition, they exhibit poor voltage
regulation against line and load fluctuations. In ref[4] a high

In the process of overcoming limitations of conventional

boost converter, several modified topologies have been
reported and more topologies are expected in near future.
However, to resolve some of these contradictory issues,
particularly to reduce ripples in voltage/ currents additional
filtering components must be inserted on the load side of the
converter. These additions lead to higher order converter
configurations, capable of meeting ripple standards, but
induce stability issues. Several higher-order pulse width (a) Proposed high gain boost converter

978-1-4799-6373-7/14/$31.00 ©2014 IEEE

 X
r1 D2 D3
rc1
L1 rc2 vˆg iˆz
v0
C1 C2 v̂ ref ê v̂0
rc3 d̂
r2 L2 R
Vg

D1 C3

X X
S1 S2
Fig. 3. Block diagram of closed-loop controlled HGBC.
(b) Equivalent circuit during mode-I operation
X
r1 D2 D3 II. STEADY-STATE ANALYSIS OF PROPOSED SOFT-
SWITCHING TWO-INPUT DC-DC CONVERTER
rc1
L1 rc2
A. Steady-state Analysis
v0
C1 C2
The proposed HGBC is shown in Fig. 1 and it is fifth-order
rc3 in nature on account of five energy storage elements (L1, L2,
Vg r2 L2 R C1, C2, and C3). These switching devices S1, S2, are turned-
X ON and OFF simultaneously in synchronous fashion and
D1 C3
hence one common pulse width modulated (PWM) input with
two drivers are sufficient enough to meet the driving
requirements of the proposed converter. As the proposed
S1 S2 converter belongs to boost topology, wherein the current
drawn from source is large and hence the currents in each
(c) Equivalent circuit during mode-II operation
inductor is continuous. Therefore, only continuous inductor
Fig. 1. Circuit diagram and equivalent circuits of the high gain boost current mode (CCM) of operation is analyzed here.
converter. Depending on the switch (S1, S2) and diodes conduction two
voltage gain boost converter is reported. But its main different modes of operations are possible and the respective
limitation is one of the switch operates at extreme duty ratio, modes equivalent circuits are shown in Fig. 1b and 1c,
which is responsible for poor utilization as well as over stress respectively. The voltage gain of the proposed HGBC can
of switching devices. To overcome some of these easily be established through application of volt-sec balance
to the inductors L1 and L2, and the important steps are given
disadvantages, a high gain fifth-order boost converter
below.
(HGBC) with better switch utilization is proposed in this
paper. Here, better switch utilization is ensured by
Vg d1Ts + VC1(1- d1)Ts = 0
synchronous switching scheme of devices. A detailed steady- (1)
state analysis of the HGBC is established and then a 100 Watt
prototype is designed for demonstrating the boosting features. (1- d1)Vg - VC1 + VC 2 - (1- d1)V0 = 0
(2)
VC1 = Vg d1 (1- d1)
(3)

Fig. 2. Voltage gain comparison of HGBC with other boost topologies.
⎡ 1 ⎤
V0 = ⎢1+ 2
⎥Vg
⎣⎢ (1- d1 ) ⎦⎥
(4)
A careful observation of the above expressions reveals that
the intermediate capacitor C1 charges to voltage that can
easily be obtained with conventional SEPIC converter.
Furthermore, the voltage gain expression denominator
includes second order term, (1-d1)2', and it gives quadratic
converter voltage gain variation with higher multiplying
feature. In view of this term the effective gain in the lower
duty ratio ranges is high as compared to conventional boost
and other comparable converters. Furthermore, resultant term
of the product is always less than the individual terms. Hence,
at lower duty ratio the converter is capable of giving higher
voltage gains. In most of the boost topologies, reported in
literature, the voltage gain increases with increase in duty
ratio and similar trend is also seen even in this topology. This
is the distinctive feature of the proposed converter wherein
moderate duty ratio (D<0.5) is sufficient enough to have
larger boosting capability. The voltage gain generated from
the above derived expression is plotted in Fig. 2 and also
compared with conventional boost and quadratic boost
converter. This voltage gain variation clearly indicates the
proposed converter suitability for lower duty ratio of
operation.
B. Small-signal Analysis
For dynamical characterization and digital controller
design the state-space and discrete-time models are needed.
In continuous current mode of operation the circuit has two
operating modes, which are: Mode-1: S1, S2, D1, D2 and D3 -
ON (0 < t < DTs); Mode-2: D4 - ON (DTs < t <Ts). In each
mode of operation, the circuit is linear, and its behaviour can
easily be described by the state-space model [13] given by:
[ x] = ⎡⎣ Aj ⎤⎦ [ x] + ⎡⎣Bj ⎤⎦ [u]
[ y] = ⎡⎣E j ⎤⎦ [ x] + ⎡⎣Fj ⎤⎦ [u]
where [Aj] is the state matrix, [Bj] the input matrix, [Ej] the
output matrix, [x] the state vector, [y] the output vector, and
[u] is the excitation vector. Discrete-time models can easily
be derived from state-space average models with appropriate
transformations as reported in ref[8]. The discrete-time
modelling reported in ref[8] is used here to establish various
small-signal z-transfer functions and the corresponding model
is listed below. Of all possible small-signal transfer functions
the following control-to-output, input-to-output and output
impedance z-transfer functions listed below are useful for
controller design as shown in Fig. 3. Several digital controller
design methods are reported in literature, which are done
either in s-domain or in the z-domain. Although it is possible
to obtain the digital controller through s-domain and later on
converting into z-domain is possible. But, here a z-domain
based design is employed as the discrete-time domain models
are having more accuracy. A block-diagram of the closed-
loop controlled HGBC is shown in Fig. 3. Here, loopgain is
used in SISOTOOL as the platform for controller design. The
final resulting controller (eqn. 13), detailed step-by-step
design methodology is discussed [4], ensures the desired
range of stability margins to the closed-loop converter
(5) system: GM> 6 dB, PM is [45° ~ 75°] and sufficient
bandwidth.

⎡ r1
0 0 0 0
⎤ xˆ ⎡⎣NTs ⎤⎦ = φxˆ ⎡⎣(N -1)Ts ⎤⎦ + γ dˆ ⎡⎣(N -1)Ts ⎤⎦ (8)
⎢− L ⎥
⎢ 1 ⎥
⎢ ⎡ RrC3 ⎤ ⎥
⎢ ⎢ r2 + rC1 + rC2 + + R +r ⎥ ⎥ (6) where φ = e A1 (DTs −td )φ1φ2;γ = e A1 (DTs −td )αφ2, φ1 = eAt1 d , φ2 = e A2D2Ts ,
−1 −1 −r2
⎢ 0 −⎣ C3 ⎦ ⎥
α = [( A1 - A2 ) X + ( B1 - B2 )Vg ].
⎢ L2 L2 L2 L 2 (r2 +rC3 ) ⎥
⎢ ⎥
[ 1] ⎢
A = 1 ⎥; vˆ 0 ( z ) dˆ ( z ) = E ′ ( z Ι- φ ) -1 γ (9)
⎢ 0 C1
0 0 0 ⎥ vˆ 0 ( z ) vˆ g ( z ) = E ′ ( z Ι - φ ) γ + F ′ -1 (10)
⎢ ⎥
⎢ -1 ⎥ (11)
iˆ0 ( z ) = [ E ′ ( z I - φ ) - 1 γ + J ′ ]
⎢ 0 C2
0 0 0 ⎥ vˆ 0 ( z )
⎢ ⎥ Bode Diagram
⎢ -R -1 ⎥
⎢ 0 0 0 60
⎣ C3 (R+rC3 ) C3 (R+rC3 ) ⎥⎦ Gvd
40 Loopgain
Gc
Magnitude (dB)

T
⎡1 1 ⎤ ⎡ RrC3 R ⎤
0 0 0⎥ ; [ E1] = ⎢0
20
[ B1 ] = ⎢ 0 0 ⎥;
⎣ L1 L2 ⎦ ⎣ (R+rC3) (R+rC3)⎦
0
⎡ (r1 + rC1 ) rC1 1 ⎤
⎢ -L 0 0 ⎥
L1 -L1 -20
⎢ 1
⎥
⎢ rC1 ( rC1 +rC2 ) −1 −1 ⎥
⎢ L 0 ⎥ (7) -40

⎢ 2 L2 L2 L2 ⎥
90

⎢ −1 −1 ⎥ 0
[A 2 ] = ⎢ C C1
0 0 0 ⎥;
⎢ ⎥ -90
Phase (deg)

1
⎢ −1 ⎥
⎢ 0 0 0 0 ⎥
-180

⎢ C 2 rC2 ⎥ -270
⎢ rC3 −1 ⎥
⎢ 0 0 0 ⎥ -360
⎣ C 3 (R+rC3 ) C 3 (R+rC3 ) ⎦
-450
0 1 2 3 4 5
10 10 10 10 10 10
T
⎡ R ⎤
Frequency (Hz)
⎡ 1 1 ⎤
[ B2 ] = ⎢0 0 0⎥ ; [ E2 ] = ⎢0 0 0 0 ⎥. Fig. 4. Frequency response characteristics of transfer functions (Gvd(z), Gc(z)
L2 C2rC2 ⎦ ⎣ (R+ rC3)⎦ and Loopgain).
⎣
 TABLE-I: DESIGN EXPRESSIONS OF THE CONVERTER A digital voltage-mode controller is designed using a pole-
placement technique. Matlab SISOTOOL [4] is used for this
Parameter Expressions
purpose. After fine tuning of the resultant controller, in pole-
L1 (Vg1D1) (ΔiL1 fS ) zero format, is
L2 ( D1V g ) ( Δ i L 2 f S (1 − D1 ))
C1 V g D 1 ( D 12 − 2 D 1 + 2 )
0.43( z − 0.965 )( z − 0.989 )
Gc ( z ) = (13)
R f s Δ v C 1 (1 - d 1 ) 3 ( z − 1 )( z − 0.93 )
C2 V g ( D 12 − 2 D 1 + 2 )
R f s Δ v C 2 (1 - D 1 )
Using the designed controller, eqn. 13, the closed-loop
system stability is verified in matlab [5] and the
corresponding loopgain bode plot is given in Fig. 4. To test
the feasibility of the designed controller, the converter
TABLE II: COMPARISON OF HGBC COMPONENT STRESS OVER THE OTHER
BOOST CONVERTERS
performance is verified both in PSIM [6] simulations and
Quantity HGBC SUC FOBC then on experimental prototype. The devices used in the
Voltage (2 − D) (1 + D)
experimentation are: Switch-IRFP250N, Diode-MUR1520,
⎡ 1 ⎤
Gain ⎢⎣1+ (1− D)2 ⎥⎦ (1 − D) (1 − D)
MOSFET Driver-IR2110 and Optoisolator-6N137. Digital
controller is realized in dsPIC microcontroller [7]. PSIM
S1-VS V0 V0 Vg software is used for time-domain simulations.
S1-CS Low High Medium
D1-VS Vg Vg (V0- Vg)
D1-CS Ig Ig Ig
D2-VS V 0 V0 (V0- Vg)
D2-CS 2I0 2I0 I0
D3-VS V0 V0 -
D3-CS Ig 2Ig -
Voltage Δv0 Δv0 Δv0
ripple
VS: Voltage stress; CS: Current stress

III. SIMULATION RESULTS AND DISCUSSIONS

To validate the proposed converter and its performance a
100 watts, 24 to 100 V HGBC prototype is made, simulation
and experimental studies are made. The parameters used are:
L1=250 µH, L2=400 µH, C1=10 µF, C1=10 µF, C1=5 µF. The
converter energy storage elements are designed to ensure
ripple contents in the inductors and capacitors (a) Simulation
(ΔiL1 = ΔiL 2 = 20%, Δvc1 = Δvc 2 = Δvc 3 = 5%). From the steady-
state voltage gain expression, eqn. 4, it is clear that this
converter is an extension of quadratic converter but an
additional boosting term equivalent to source voltage is added
on the output side. This additional boosting term equivalent
to source voltage is obtained just by using an additional diode
and capacitor over the quadratic boost or cascade boost
converter. Although, the component stress in this converter is
slightly higher than the quadratic converter but it is resulting
in higher load voltages. For identical load voltage cases the
component stress of the proposed converter is almost
identical to the quadratic or cascade boost converter. With
these parameters and using the models (eqns. 5 to 11) small-
signal transfer functions are obtained as

−0.1275z 4 + 0.4554z3 − 0.6063z2 + 0.3572z − 0.0788

Gvd ( z ) = (12) (b) Measurement
⎡⎣ z5 − 4.605z 4 + 8.604z3 − 8.161z 2 + 3.929z − 0.7677⎤⎦ Fig. 5. Steady-state waveforms at nominal operation.
 (b) Experimental measurement
Fig. 7. Dynamic response of load voltage against source voltage change (Vg:
20 to 28 V).

(a) Simulation
The steady-state waveforms for nominal operating
conditions are shown in Fig. 5. To test the controller
feasibility dynamic response are measured for (a) step change
in load (R: 150 to 75 Ω), (b) source voltage change (Vg: 20 to
28 V). The dynamic response time of 15 ms is seen in the load
voltage regulation against load perturbation. Controller
feasibility as well as the regulation feature is also measured
against gradual change in source voltage (20 to 28 V) as
shown in Fig. 7. In this case also the load voltage maintained
at around reference value. These simulation and experimental
results, given in Figs. 5 to 7, are close in agreement and slight
differences are on account of mismatch in the non-idealities
of prototype converter and simulation circuit.

IV. CONCLUSION
(b) Experimental measurement A boost topology capable of realizing high gain at low duty
Fig. 6. Dynamic response of load voltage against load change (R: 150 to 75
ratio was proposed in this paper. Voltage gain boosting
Ω).
feature was demonstrated through detailed steady-state
analysis. Small-signal models required for digital controller
design has been established and then digital controller was
designed. The high gain converter performance was tested,
both in simulation and experiment, and demonstrated its
regulation features.
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[4] Mukesh Singh Tomar, "Steady-state Analysis and Controller design for
a High-gain Fifth-order Boost Converter," Proc. of Annual IEEE India
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(a) Simulation
[5] MATLAB, user manual, 2005.
[6] PSIM, user manual, 2005.
[7] dSPIC30F2020, Microchip, user manual, 2009.