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Published in IET Power Electronics
Received on 29th April 2010
Revised on 27th August 2010
doi: 10.1049/iet-pel.2010.0139

ISSN 1755-4535

Unity power factor rectifier – inverter structure

operating under unbalanced supply and variable
DC bus voltage
A.I. Maswood F. Liu
Center for Advanced Power Electronics (CAPE), School of Electrical and Electronic Engineering,
Nanyang Technological University, Singapore 639798, Singapore
E-mail: Eamaswood@ntu.edu.sg

Abstract: A recently introduced method of improving converter input current waveforms as well as power factor are re-evaluated
under non-ideal operating conditions, that is, variable DC bus and unbalanced supply. The proposed method makes use of a novel
controlled front-end diode rectifier of a rectifier – inverter structure. The technique involves the use of bi-directional bi-pass
switches across the front-end rectifier, with a dSPACE-based intelligent control algorithm. The operation of the converter is
fully analysed as possible DC/AC drives and a complete design example is provided. The main feature of the topology is low
cost, small size, high power factor and simplicity. It is found to be a universal retrofit for DC drives, and in the front-end
rectifier of existing three-phase AC drives, UPS etc. for power factor correction without any passive or active filtering.

1 Introduction However, none of the above-mentioned works focused on

To maintain supply quality at acceptable levels, various
standards and guidelines, that is, IEEE 519 and IEC 61000-
3 specify limits of current harmonic content for certain
types of applications. Many promising power factor
correction techniques [1 –7] have been proposed related to
front-end rectifier, both in terms of topologies and control
methods. In their landmark work, Mehl and Barbi [1]
confirmed the success of such an approach. However, the
chief disadvantage was the requirement of large input
inductors. Among other past works to address such
challenge, the three-phase three-level (TPTL) rectifier drew
much attention. Salmon et al. [5] studied the operation of a
family of harmonic correction networks for three-phase
diode rectifiers utilising a combination of thyristor and
insulated gate bipolar transistor (IGBT) switches. Kim et al.
[8] proposed a harmonic elimination method utilising a
three-phase transformer. Based on the combination of a
three-phase diode rectifier and dc/dc boost converter, Kolar
et al. developed a new TPTL rectifier [6]. Zhao et al. [7]
proposed a force commutated three-level boost-type rectifier
with space vector control which solved the existing dc link
middle point voltage drifting problem. Ide et al. [9]
proposed a control scheme for a selected three-level
switched mode rectifier. Such TPTL rectifier utilises single
bidirectional switch per phase, resulting in a lower control
and driving effort. The significant advantage of the three-
level operation is the reduction of voltage stress on the
power switches, since only half of dc link voltage is applied
across the power switches allowing the use of low losses
and low-cost power devices.
the possibility of non-ideal operating conditions of such
converters. Moreover, they also lack the possibility of
simple and low-cost retrofitting of the existing commercial
three-phase drives. In this work, a recent method to
improve the input power factor (PF) of three-phase rectifier
initially proposed by Mehl and Barbi [1] and further
enhanced by Maswood et al. [2, 3] is re-examined under
load and supply voltage variation. The topology is depicted
in Fig. 1. It operates with low input current harmonic
distortion, and does not need any clamping circuit to
prevent excessive over voltage across the active switches
during the turn-off commutation. Apart from any previous
methods in the proposed technique, the bi-directional
switches are switched at high frequency (5 – 7 kHz),
resulting in the requirement of a very low value of input
inductors (‘L’ in Fig. 1). Since bi-directional switches carry
the load current of only a fraction of the diode conduction
period, their ratings will still be low and no EMI problem
would occur. In most cases, the line inductance is sufficient
and additional inductor is not required.
With reference to Fig. 1, Va , Vb and Vc represent the voltage
source of the three-phase ac system. L represents input inductor
for each phase, and D1 through D6 are line frequency power
diodes. Two identical capacitors Ca and Cb do help to
provide a balanced central node between the positive and
negative output terminals. Although the power circuit is
similar to the high-frequency pulse width modulation (PWM)
rectifier, the bidirectional switches operate at low frequency
and the gating circuit is relatively simple.
The line current shows a delay of approximately 308 (no
conduction) relative to the line-to-neutral supply voltage in

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doi: 10.1049/iet-pel.2010.0139 & The Institution of Engineering and Technology 2011
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Fig. 1 Front-end rectifier with three bi-directional switches and the switch layout

a conventional three-phase diode rectifier, resulting in With the above method, the input current THD can be as
periodical intervals where such current is null. The effect is low as 6.6% and input PF as high as 0.996. However, this
a low input PF and high harmonic distortion of the input simple diode rectifier was proposed to operate with a fixed
current. Each of the bidirectional switches Sa , Sb and Sc is load and fixed ‘optimal’ input inductance [2]. Since the
turned on during a specific interval, providing an alternative bidirectional switches are operated independent of load on
path for the input current. Thus the input current waveform the rectifier bridge, this method cannot provide optimum
is well shaped to nearly sinusoidal and a gate pulse with a input PF as well as input current THD under varying load
fixed duration of 1/12 of line voltage period (308) results in conditions. For example, the rectifier input PF can drop
a remarkable improvement of the input PF and input current below 0.9 and input current THD increased to 20% due to
total harmonic distortion (THD). the input current discontinuity at low-power conditions.
The rated output voltage of the converter can be calculated Fig. 2 depicts the rectifier performance at fixed bi-directional
by assuming the phase current to be zero when vt ¼ 1808 [2]. switch conduction under various load conditions. When
delivering a higher power than rated value, the rectifier
√ operates in a non-efficient mode as the PF suddenly drops
36 2Vi
VO = √ = 1.366Vi (1) (Fig. 2b). The phase shift between input current and voltage
7p 3 of the rectifier is found to exceed 308, resulting in a lower
input PF. At the same time, the voltage drop across the input
where VO is the rated output voltage and Vi is the input line to inductance is large due to the high input current [10–13].
line voltage.
Assuming that the input current supplies the load during 2 Proposed method at variable DC
the 908– 1208 interval, the critical input inductance can be bus power
determined by using (2) [2].
In this work, a unity PF front-end rectifier is proposed which
36 √ V2 V2 can operate either as a dc (Fig. 1) or an ac drive with a rear-
L = (2 2 − 3) · 3i = 3.8489 × 10−2 · i (2) end inverter as shown in Fig. 3. The rectifier– inverter
7 2p fPO fPO
structure can function at varying load conditions and supply
where f is the ac system frequency, Po and is the rectifier rated voltage and overcomes all the drawbacks mentioned above.
output power. It is achieved through the intelligent controller that varies

Fig. 2 Rectifier performance under various load conditions

a Input PF and input current THD
b Output voltage

900 IET Power Electron., 2011, Vol. 4, Iss. 8, pp. 899 –907
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0139
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Fig. 3 Complete circuit diagram of the proposed unity PF ac drive

the conduction period of bidirectional switches. These and 8. In stages 3, 6 and 9, only two phases are conducting
switches operate at only two times the line frequency and and the third phase current is discontinuous. For stage 1 in
its gating circuit is relatively simple. Owing to the low- 0 2 a interval, the following equations can be obtained
frequency nature of the switching patterns, power losses are with reference to Fig. 4a
reduced and low-cost devices can be used. This results in a
significant reduction in cost. ⎧
⎪ di
⎪
⎪ va = L a + vMN
⎪
⎪ dt
2.1 Converter operation below its rated power ⎨
di 1
vb = −L b − Vdc + vMN (3)
⎪
⎪ dt 2
When the output power is lower than the rated output power, ⎪
⎪
bidirectional switch conduction angle a is adjusted to make ⎪
⎩ v = L dic + 1 V + v
c
the output voltage constant and at the rated value. Due to dt 2 dc MN

phase current discontinuity, there will be nine conduction

stages corresponding to the 08– 1808 half period out of where vMN is the voltage between node M and node N.
which only stages 1 – 4 are illustrated in Fig. 4. Parameter b For three-phase supply without neutral, the three-phase
denotes the phase current discontinuity interval in radian current in Fig. 3 is guaranteed by
per half line voltage cycle.
It is found that there are only two conducting diodes in
stages 1, 4 and 7 and three conducting diodes in stages 2, 5 ia − ib + ic = 0 (4)

Fig. 4 Topological stages for ‘08 –1808’ interval of the input voltage Va
a Stage 1: 0 2 a interval
b Stage 2: a 2 ( p/3 2 b) interval
c Stage 3: ( p/3 2 b) 2 p/3 interval
d Stage 4: p/3 2 ( p/3 + a) interval

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From (3) and (4), we can obtain (5) for a 2 0 interval interval a 2 ( p/3 2 b), (10) can be solved as
√
vMN = 0 (5) 2Vi V t V a
ia (t) = √ (1 − cos vt) − dc + dc (11)
vL 3 3L 3vL
Thus
The phase current of other stages are similarly analysed and
dia formulated in Table 1 for all possible stages. The phase
va = L (6) current decreases to zero at the end of stage 8. In addition,
dt
the output voltage is kept constant at the rated output
voltage VO . So one can obtain ia ( p 2 b) ¼ 0 for the input
Since the input phase current ia starts from zero (ia(0) ¼ 0), it
current expression of stage 8 in Table 1.
can be solved as
Thus the relationship between a and b is solved as
√
2V 9 12
ia (t) = √i (1 − cos vt) (7) cos b = − (a + b) (12)
vL 3 7 7p

For a 2 ( p/3 2 b) interval, (8) can be obtained according to For a small value of b, one can obtain the approximate
Fig. 4b equation as

⎧ p
di b≃ −a (13)
⎪
⎪ va = L a + vMN 6
⎪
⎪
⎪
⎪ dt
⎪
⎨ di 1 In order to find the relationship between the conduction angle
vb = −L b − Vdc + vMN a and normalised dc link current, numerous attempts have
dt 2 (8)
⎪
⎪
⎪
⎪ dic 1 been made utilising Table 1. The following relationship was
⎪
⎪ v =L + V + vMN
⎪ c
⎩ dt 2 dc found to best match its behavioural pattern
ia − ib + ic = 0
a = 14.9 + 15.1k (14)
The voltage vMN and the phase current ia can be calculated as
(9) and (10), respectively. a is in degree and k denotes the normalised dc link current
with respect to the rated dc link current.
Vdc
vMN = − (9) 2.2 Converter operation above its rated power
6
When the output power demand is higher than the rated
di V output power, the conduction angle is adjusted to maintain
va = L a + dc (10)
dt 3 the output voltage constant around the value VO . In this
case, as expected, the conduction angle a will be larger
Employing the value of ia at vt ¼ a as the initial value of than 308. The phase current is continuous and b equals to

Table 1 Input current expressions at individual stage for Pout , PO(rated)

Stage Equation
√
1. 0 2 a 2V
ia (t) = √i (1 − cos vt)
vL 3
p  √
2V V tV a
2. a − −b ia (t) = √i (1 − cos vt) − dc dc
3 vL 3 3L 3vL
p  p √  √
2Vi p
2V p 
V t V a p 
3. −b − ia (t) = sin b − cos vt + + √i 1 − cos − b − dc dc − b + 2a
3 3 2 vL 6 vL 3 3 2L 6vL 3
√ √  
p p  2Vi 2V 3 p  V t V p 
4. − +a ia (t) = sin b + √i − cos vt − cos − b − dc dc − b + 2a
3 3 2 vL vL 3 2 3 2L 6vL 3
p  2p  √ √  p  
2Vi 2V 3 2V t V 2p
5. +a − −b ia (t) = sin b + √i − cos vt − cos − b − dc dc − b + 3a
3 3 2 vL vL 3 2 3 3L 6vL 3
  √  √  
2p 2p 2Vi p
2V 3 √ V tV a
6. −b − ia (t) = 2 sin b − cos vt − + √i − 3 sin b − dc dc
3 3 2 vL 3 vL 3 2 2L 2vL
 √ √
2p 2p 2Vi 2V √ V tV a
7. − +a ia (t) = sin b + √i (1 − cos vt − 3 sin b) − dc dc
3 3 vL vL 3 2L 2vL
 √ √
2p 2Vi 2V √ V t V a Vdc a
8. + a − (p − b) ia (t) = sin b + √i (1 − cos vt − 3 sin b) − dc dc
3 2 vL vL 3 3L 9vL 3vL
9. (p 2 b 2 p) ia(t) ¼ 0

902 IET Power Electron., 2011, Vol. 4, Iss. 8, pp. 899 –907
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0139
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Table 2 Input current expressions at individual stage for conduction angle a (thus pulse width). The proposed
Pout . PO(rated) control circuit block diagram is shown as Fig. 5. The dc
link voltage is also detected and compared with reference
Stage Equation
voltage to provide the required compensation for a. Due to
√ the uncontrolled characteristic of diode rectifier, a tiny
1. 0 2 a 2V 2pVdc Vdc a
ia (t) = − √i cos vt + − compensation can lead to optimum performance.
vL 3 9 vL 6 vL
√
p 2V Vdc t Vdc a 2pVdc
2. a − ia (t) = − √i cos vt + − +
3 vL 3 3L 6 vL 9 vL 3 Design example and implementation
p  √
p 2V Vdc t Vdc a 5pVdc A sinusoidal PWM (SPWM) voltage source inverter, a
3. − +a ia (t) = − √i cos vt + − +
3 3 vL 3 2L 6 vL 18vL popular topology in industry for ease of implementation,
p  2p √ is used as the rear-end converter for the intended
2V 2Vdc t Vdc a pVdc
4. +a − ia (t) = − √i cos vt + − + rectifier – inverter ac motor drive topology as depicted in
3 3 vL 3 3L 3vL 3vL
√
Fig. 3.

2p 2p 2V Vdc t Vdc a 2pVdc
5. − +a ia (t) = − √i cos vt − + +
3 3 vL 3 2L 3 vL 9 vL
√
3.1 Bi-directional switch ratings

2p 2V V t V a pVdc
6. +a −p ia (t) = − √i cos vt − dc + dc + Taking phase ‘a ’ as reference, the peak current through the
3 vL 3 3L 6 vL 9 vL
bidirectional switch can be calculated by substituting
vt ¼ 408 (the upper limiter of a) into the equation of stage
1 in Table 2. Hence, (16) can be used to calculate the
zero. Therefore there are six well-known conduction stages
bidirectional switch peak current.
and two-phase conduction stages 3, 6 and 9 of low-power
operation do not exist here. The phase current in each
stage is investigated and expressions are developed and PO
Isw(peak) = 0.6291 (16)
presented in Table 2. Similarly utilising the equations in Vi
Table 2, the relationship between a and k can be
expressed as follows Since the switch is off during the 408 – 1808 and 2208 – 3608
intervals the rms value of the switch’s current is given by
a = 30k (15) (17) and the average current is calculated using (18).

PO
2.3 Design of front-end rectifier controller under Isw(rms) = 0.1225 (17)
unbalanced supply Vi

Once the input phase voltage crosses zero-volt point, the PO

corresponding switch will be triggered. Under unbalanced
supply condition, the voltage zero crossings are not
equidistant, but depends on the degrees of unbalances [14].
It was found previously [9] that the phase (say phase ‘a’)
with the higher voltage-swell will have larger diode
conduction and vice versa. This also translates into longer
switching for switch ‘Sa’ (see Figs. 3 – 5). Accordingly, the
previously proposed controller in [9] is modified to take
this into account.
Each of the bidirectional switches (Sa , Sb and Sc) conducts
twice in every line voltage cycle. The drive pulse width for
the bidirectional switches is determined by the dc link
current being supplied. According to (14) and (15), one
needs to measure the dc link current Idc to control the
Isw(avg) = 0.0238 (18)
Vi
The bidirectional switches operate at only two times line
frequency, at reduced power loss, utilising low-cost devices.
Meanwhile, the voltage across the switch’s terminals is
lower than half of the dc link voltage when the switch is
off, eliminating any undue voltage stress.
3.2 Rated drive parameters
For the purpose of illustrating the design procedure, a
converter with the following specifications is chosen:
† input ac line-to-line voltage 220 V;
† ac frequency 50 Hz;
† rated output power 1.5 kW.

The critical input inductance of La , Lb and Lc , and at the

rectifier input side is calculated using (2), giving

2202
Lcritical = 3.8489 × 10−2 = 24.84 mH
50 × 1500

For the rated output power of 1.5 kW, the dc link voltage
of the front-end rectifier is calculated with (1) and results in

Fig. 5 Bi-directional switch control block diagram Vo = 1.3366 × 220 = 294.05V

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Fig. 6 Input phase current and its spectral composition at various load conditions
a 40% rated load
b 120% rated load

4 Operation under variable DC bus and Table 4 Performance parameters with controller under varying
input line inductances input inductances

4.1 Simulation result Input inductance a, 8 w1 , 8 THD PF Vdc , V

90% Lcritical 29.7 23.0 6.9% 0.996 296.4

The input current and its spectral compositions of the
100% Lcritical 30.4 24.6 6.5% 0.995 294.7
proposed converter, under 40% rated load and 120% rated
110% Lcritical 32.2 28.7 6.0% 0.987 290.0
load are presented in Fig. 6. The input PFs at 40% rated
load and 120% rated load are 0.987 and 0.976, respectively.
Table 3 gives the performance parameters at various load 4.2 Experimental results
conditions. In general, the PF drops as the load power
rating shifts from its rated value. It was however found that The controller is implemented using a single-board ds1102
within a practical limit, the PF remains very good microprocessor and developed under the integrated
exceeding any recommended IEEE or IEC standards. development environment of MATLAB-SIMULINK RTW
The input inductance plays a vital role on rectifier optimum provided by the Math Works, Inc. A prototype of the
performance. In a given AC network, the line inductance may rectifier – inverter structure depicted as in Fig. 3 is
vary due to various reasons. However, the proposed control constructed, and its performance is observed. The hardware
technique can overcome such difficulties. When the input prototype is shown in Fig. 7.
inductance varies within a certain range, the bidirectional The input PF, as well as the input current THD of the
switches conduction angle is calculated with the help developed prototype are shown in Fig. 8. Fluke-43 power
of voltage compensation part [3] to achieve optimum quality analyser with online numerical value illustration is
performance. Table 4 gives the performance parameters for used to monitor the waveforms. The input PF is shown
the converter operating at rated output power and under online at the upper right-hand corner of input current
various input inductance conditions. One can see that this waveform of Fig. 8.
topology can achieve a good performance even with the Prior to improvement, the input current THD and PF
input inductance variation of +10% range. was 91.5 and 0.72%, respectively, obtained from a similar

Table 3 Performance parameters at various dc bus conditions

Load (PO) f1 (8)D THD PFa Vdc , Vb

40% 3.8 14.9% 0.987 295.9

100% 24.6 6.5% 0.995 294.7
120% 212.1 6.4% 0.976 293.1

D w1 denotes the angle between the input line to neutral voltage

and fundamental current
a
where THD and PF is defined as

2
IS
THD = −1
I1

PF = cos w1 / 1 + THD2

b
The rated dc link voltage is 294.05 V Fig. 7 Top view of the hardware prototype without the motor load

904 IET Power Electron., 2011, Vol. 4, Iss. 8, pp. 899 –907
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0139
 www.ietdl.org

Fig. 8 Input current and voltage and current FFT of the proposed prototype at rated load

systems should be designed and operated to limit the

maximum voltage unbalance to 3% when measured at the
electric-utility revenue meter under no-load conditions.
And the International Electro technical Commission (IEC)
recommends that the maximum voltage unbalance of
electrical supply systems be limited to 2%. The developed
rectifier – inverter AC drive structure is subjected to a
maximum 10% unbalance to test its performance under
worst-case scenario. If the supply phase voltages are
assumed as Van , Vbn and Vcn , their corresponding zero,
positive and negative sequence can be expressed as [14]

Van + Vbn + Vcn

VO = (19)
3
Van + aVbn + a2 Vcn
Vp = (20)
3

Fig. 9 Bi-directional switch conduction angles (a) at different DC Van + a2 Vbn + aVcn
Vn = (21)
bus load conditions 3
YASKAWA VS-6006V7 1.5 kW commercial three-phase where a ¼ 1/1208 and a 2 ¼ 1/2408. The unbalance factor
Inverter. The proposed scheme is able to improve the input u can be defined as [14]
current THD to 5.0% and the input PF to 0.99. This is a
remarkable improvement in PF and THD. The experimental |Vn |
results agree with the MATLAB predicted waveforms and u= (22)
Vp
also as presented in Table 3.
The controller maintains the dc link voltage variation
within 3% of its rated value throughout its operation. And
the conduction angle a at different load conditions is shown The specification of 10% unbalance supply is chosen as
in Fig. 9. follows:

† phase a 127 V (1 p.u.),

5 Effect of unbalanced supply
Most electrical systems are designed based on the assumption
that the three-phase supply is symmetrical and at the
fundamental frequency of 50/60 Hz. With proper design,
the performance of forced commutated converter under
unbalanced supply could be improved [15, 16]. However,
three-phase diode rectifiers with capacitive filters are highly
sensitive to supply voltage unbalance, drawing significant
unbalanced line current even under slightly unbalanced
voltage condition [17].
The American National Standards Institute (ANSI)
standard C84.1-1995 recommends that electrical supply
† phase b 108 V (0.85 p.u.),
† phase c 152 V (1.20 p.u.).
5.1 Simulation results
Through MATLAB SIMULINK modelling, the phase ‘a ’
input current waveform (solid line) and its FFT are shown
in Fig. 10, phase ‘a’ where the dashed line is the
corresponding current waveform under balanced supply
conditions. The same waveforms for phase ‘b’ and ‘c’ are
also shown in this figure.
From the waveforms and their corresponding harmonic
spectra (FFT), one can notice that unbalance supply causes

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Fig. 10 Input current waveform and their FFTs under 10% unbalanced supply
Fig. 11 Phase ‘a’ current and current FFT under 10% unbalanced supply
mostly the third harmonics in all the three phases to shoot up.
Such non-characteristic harmonics are always absent in a
balanced three-phase system. The principal cause of PF
degradation under unbalance supply is due to the generation
of third and other triplen (3∗ N, N ¼ 1, 3, 5. . .) harmonics in
the input current [14]. These can be attributed to the
unequal conduction of the power diodes of the front-end
bridge rectifier. It was previously shown [14] that the phase
with the highest input voltage has the highest conduction
period and the lowest supply causes shortest period,
exceeding or falling short respectively of their typical 1208
conduction period. This causes the three-phase currents to
be different from one another resulting in non-cancellation
of the zero sequence (triplen) components.
It was also found that unbalance in supply voltage phase
angles will cause similar effect, and for the same reason.
Unbalance in both the magnitude and phase of supply
voltages will also affect the converter performance in a
similar fashion, only to add to the triplen harmonics.
However, such severe cases (10% or above) are rarely
906
& The Institution of Engineering and Technology 2011
encountered and the bidirectional switch controller with
its built-in capability can handle common unbalance well.
The PF remains high as confirmed by the results of Fig. 11.
5.2 Hardware experimental results
The current waveforms for phase ‘a ’, both in the time and
frequency domain, are shown in Fig. 11.
The supply voltage unbalance causes deterioration in the input
PF and input current THD of the rectifier–inverter structure.
However, with the proposed controller, the input current THD
for all three phases is below 10% approx., and the input PF is
above 0.95. Under such severe 10% unbalance, phase ‘b’ (not
shown) suffers the maximum degradation resulting in
somewhat lower PF. However, with the intelligent controller
that automatically varies the switch conduction angles to
minimise the effect of unbalance, this deterioration is under
commonly accepted (as well as IEE) standard of 10%. Under a
typical 5–7% supply unbalance the controller is most
effective, and the converter input PF is above 0.98.
IET Power Electron., 2011, Vol. 4, Iss. 8, pp. 899 –907
doi: 10.1049/iet-pel.2010.0139

6 Conclusions
In traditional converter for AC and DC motor drive
applications, the input PF can be poor especially at low
motor speeds. Passive filters or 12-pulse topology for the
front-end rectifier only adds to its heavy weight and
complexity and can sometimes cause severe resonance
problem. Most recently proposed power factor correction
schemes based on current injection and active filtering
requires significant additional hardware. This results in cost,
weight and complexity.
The proposed converter motor drive is verified to be
efficient and functional under unbalanced supply and over a
wide output power variations. This opens up the possibility
of the front-end-rectifier to be used as a DC motor drive. A
prototype of the converter has been designed, built and
tested to function both as DC and front-end converter for
existing AC drive. It shows the characteristics of simplicity
and high efficiency. Through the use of this new method,
a highly efficient and low-cost motor drive can be
economically built to operate within a wide load range with
PF above 0.99. At high 10% unbalance supply, the PF
remains high at or over 0.95. It also exhibits good
performances, even with a large DC bus voltage variation,
and is thus capable of withstanding power line
uncertainties. The requirement for large input inductance
has been eliminated through higher switching frequency of
the bi-direction switches. The proposed bidirectional switch
together with its controller is also a good PF correction
retrofit to the front-end rectifiers of the existing DC and AC
drives and UPS.
7 References
1 Mehl, E.L.M., Barbi, I.: ‘An improved high power factor and low cost
three-phase rectifier’, IEEE Trans. Ind. Appl., 1997, 33, pp. 485– 492
2 Maswood, A.I., Yusop, A.K., Rahman, M.A.: ‘A novel suppressed-link
rectifier-inverter topology with near unity power factor’, IEEE Trans.
Power Electron., 2002, 17, (5), pp. 381–386
IET Power Electron., 2011, Vol. 4, Iss. 8, pp. 899–907
doi: 10.1049/iet-pel.2010.0139
www.ietdl.org
3 Maswood, A.I., Fangrui, L.: ‘A novel variable hysteresis band current
control of three-phase three-level unity PF rectifier with constant
switching frequency’, IEEE Trans. Power Electron., 2006, 21, (6),
pp. 23–27
4 Pejovic, P.: ‘Two three-phase high power factor rectifiers that apply the
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