3884 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO.
12, DECEMBER 2011
A Bridgeless Single-Stage Half-Bridge
AC/DC Converter
Woo-Young Choi and Joo-Seung Yoo
Abstract—This paper proposes a new bridgeless single-stage
half-bridge ac–dc converter for power factor correction. The pro-
posed converter integrates the bridgeless boost rectifier with the
asymmetrical pulse-width modulation half-bridge dc–dc converter.
The proposed converter provides an isolated dc output voltage
without using any full-bridge diode rectifier. Conduction losses are
lowered by eliminating the full-bridge diode rectifier. Zero-voltage
switching of the power switches reduces the switching power losses.
The proposed converter gives a high efficiency, high power factor,
and low cost. The effectiveness of the proposed converter is veri-
fied on a 250 W (48 V/5.2 A) experimental prototype. The proposed
converter achieves a high efficiency of 93.0% and an almost unity
power factor for 250 W output power at 90 Vrm s line voltage.
Index Terms—AC–DC converter, asymmetrical pulse-width
modulation (APWM), bridgeless, half-bridge, single-stage, zero-
voltage switching (ZVS).
I. INTRODUCTION
HE advances in power factor correction (PFC) technol-
T ogy have enabled the development of single-phase ac–dc
converters [1]–[13] in the recent pieces of literature [30]–[54].
Among them, the single-stage ac–dc converter has been an ac-
tive research topic in the power electronics. A number of single-
stage PFC ac–dc converters have been introduced in the lit-
erature [1]–[13]. The discontinuous-conduction-mode (DCM)
single-stage PFC ac–dc converters are widely used for their
simple and efficient structures [4]–[13]. Generally, two power
stages of the PFC circuit [30]–[37] and dc–dc converter are
simplified by sharing a common switch [4]–[7] or a pair of
switches [8]–[13]. Most single-stage PFC ac–dc converters use
single-switch dc–dc converter topologies like flyback [4], [5]
or forward converters [6], [7]. However, the single-stage single-
switch ac–dc converters have low power efficiency because of
the hard-switching operation. The practical use of the single-
stage single-switch ac–dc converters has been limited for low
output power applications under 80 W.
Single-stage soft-switching ac–dc converters [8]–[13] have
been studied to improve the power efficiency. Single-stage soft-
Manuscript received July 15, 2010; revised September 18, 2010, November
9, 2010, and December 13, 2010; accepted March 31, 2011. Date of current
version December 6, 2011. This work was supported by the National Research
Foundation of Korea grant funded by the Korean Government (MEST) (2010-
0029431). Recommended for publication by Associate Editor K.-B. Lee.
The authors are with the Division of Electronic Engineering, Chonbuk Na-
tional University, Deokjin-Dong, Jeonju 561-756, Korea (e-mail: wychoi@
jbnu.ac.kr; juseung218@gmail.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2011.2141152
0885-8993/$26.00 © 2011 IEEE
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switching ac–dc converters based on the half-bridge converter
provide low voltage stresses and zero-voltage switching (ZVS)
operation of the power switches [8]–[10]. The active-clamping
techniques [11]–[13] have been applied to the single-stage PFC
ac–dc converters. However, the majority of these development
efforts have been focused on only reducing switching power
losses. The previous single-stage PFC ac–dc converters [8]–[13]
need the full-bridge diode rectifier. The full-bridge diode rec-
tifier increases the conduction losses and decreases the power
efficiency. Especially, at low line voltage, the full-bridge diode
rectifier causes high conduction losses, resulting in additional
thermal management. These problems can be overcome by elim-
inating the full-bridge diode rectifier. Up to now, however, any
bridgeless single-stage PFC ac–dc converter has not been re-
ported for single-stage PFC ac–dc converters.
This paper proposes a new bridgeless single-stage half-bridge
ac–dc converter. The proposed converter integrates the bridge-
less boost rectifier [14]–[19] with the asymmetrical pulse-width
modulation (APWM) half-bridge dc-dc converter [20]–[22].
The proposed converter provides an isolated dc output volt-
age without using any full-bridge diode rectifier. Conduction
losses are lowered by eliminating the full-bridge diode rectifier.
Switching power losses are reduced by the ZVS operation of the
power switches. The proposed converter gives a high efficiency,
high power factor, and low cost. The operation and analysis of
the proposed converter are presented. The performance of the
proposed converter is verified on a 250 W (48 V/5.2 A) ex-
perimental prototype. The proposed converter achieves a high
efficiency of 93.0% and an almost unity power factor for 250 W
output power at 90 Vrm s line voltage.
II. CIRCUIT DESCRIPTION
Fig. 1 shows the circuit diagram of the proposed converter.
The bridgeless boost rectifier consists of the boost inductor Lb ,
dc-link capacitor Cd , and switching devices D1 , D2 , S1 , and
S2 . D1 and D2 are slow-recovery diodes. S1 and S2 are metal–
oxide–semiconductor field-effect transistors (MOSFETs). DS 1
and DS 2 are body diodes of S1 and S2 , respectively. CS 1 and
CS 2 (CS = CS 1 = CS 2 ) are the output capacitors of S1 and S2 ,
respectively. The APWM half-bridge dc–dc converter consists
of Cd , S1 , S2 , blocking capacitor Cb , transformer T , output
diodes Do 1 and Do 2 , output filter inductor Lo , and output filter
capacitor Co . Ro is the output resistor. By sharing Cd , S1 ,
and S2 , the proposed converter integrates the bridgeless boost
rectifier with the APWM half-bridge dc–dc converter. The line
voltage vi is given by
√
vi = 2Vin sin ωt (1)
 CHOI AND YOO: BRIDGELESS SINGLE-STAGE HALF-BRIDGE AC/DC CONVERTER
Fig. 1. Circuit diagram of the proposed converter.
Fig. 2. Simplified circuit diagram of the proposed converter.
where Vin is the root-mean-square (RMS) value and ω is the
angular frequency of vi . ω is defined as ω = 2πfline where
fline is the line frequency. The line voltage vi is applied to the
boost inductor Lb through a line filter Lf and Cf . The line
filter is large enough so that the ripple current component of the
boost inductor Lb is negligible. S1 is controlled when vi is in a
positive line period. S2 is controlled when vi is in a negative line
period. By making the boost inductor Lb to operate in DCM,
PFC is naturally performed by the APWM control of the power
switches.
Fig. 2 shows the simplified circuit diagram of the proposed
converter. It shows the voltage and current directions of the
proposed converter. The line filter is not included for a simple
analysis of the proposed converter. For a positive half line period,
the ac source is connected to the terminal of the dc-link voltage
Vd through D1 . For a negative half line period, the ac source
is connected to the ground through D2 . The transformer T has
the magnetizing inductor Lm and leakage inductor Llk with the
turns ratio of 1:N:N where N = NS /NP and NS = NS 1 =
NS 2 . The leakage inductor Llk is assumed to be much smaller
than the magnetizing inductor Lm so Llk is negligible in the
analysis. The output filter inductor Lo is large enough so that
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3885
the output filter inductor Lo operates in continuous-conduction
mode (CCM). The capacitors Cd , Cb , and Co are large enough
so that the voltages Vd , Vb , and Vo are constant.
III. CIRCUIT OPERATION
Fig. 3 shows the operation modes of the proposed converter
during one switching period Ts . Fig. 3(a) shows the operation
modes during Ts for a positive half line period. S1 is controlled
with the duty ratio D. The conduction times of S1 and S2 are
DTs and (1 − D)Ts , respectively. When S1 is turned ON, the
input current ii flows through Lb , D1 , and S1 . When S1 is
turned OFF, the input current ii flows through Lb , D1 , Cd , S2 ,
and DS 2 . Fig. 3(b) shows the operation modes during Ts for a
negative half line period. S2 is controlled with the duty ratio D.
When S2 is turned ON, the input current ii flows through S2 ,
D2 , and Lb . When S2 is turned OFF, the input current ii flows
through S1 , DS 1 , Cd , D2 , and Lb .
Fig. 4 shows the operation waveforms of the proposed con-
verter during Ts for the positive half line period. Due to the
symmetric operation for each half line period, only the opera-
tion modes for the positive half line period are described. Vi is
 3886 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011

Fig. 3. Operation modes of the proposed converter during T s . (a) Operation modes for a positive half line period. (b) Operation modes for a negative half line
period.

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 CHOI AND YOO: BRIDGELESS SINGLE-STAGE HALF-BRIDGE AC/DC CONVERTER 3887

At the secondary side, the output filter inductor current iL o

increases as
N (Vd − Vb ) − Vo
iL o (t) = iL o (to ) + (t − t0 ) . (4)
Lo
Because iL o = iD o 1 , the primary current ip is expressed as
ip (t) = iL m (t) + N iD o1 (t) . (5)
Mode 2 [t1 , t2 ]: At t = t1 , S1 is turned OFF. The primary
current ip charges CS 1 and discharges CS 2 . The voltage VS 2
across S2 decreases from Vd to zero, while the voltage VS 1
across S1 increases from zero to Vd . The magnetizing current
iL m and boost inductor current iL b are considered constant be-
cause the time interval during this mode is negligible compared
to Ts . As long as the switch S2 is turned ON before the mag-
netizing current iL m changes its direction, ZVS of S2 can be
assured. At the secondary side, the output filter inductor current
iL o freewheels through both output diodes Do 1 and Do 2 . The
output diode current iD o 1 decreases while the output diode cur-
rent iD o 2 increases. Then, the ZVS condition of the switch S2
is
1 1
Lm [iL b (t2 ) + iL m (t2 ) + iD o1 (t2 )]2 > (CS 1 + CS 2 ) Vd2 .
2 2
(6)
When VS 2 is zero at t = t2 , the primary current ip flows
through the body diode DS 2 of S2 .
Mode 3 [t2 , t3 ]: At t = t2 , S2 is turned ON. ZVS of S2
is achieved when S2 is turned ON. The input current ii flows
through Lb , D1 , Cd , S2 , and DS 2 . The energy stored in the
boost inductor Lb is released to the dc-link capacitor Cd . The
boost inductor current iL b decreases as
vi
iL b (t) = iL b (t2 ) − (t − t2 ) . (7)
Lb
The magnetizing inductor current iL m decreases as
Vb
iL m (t) = iL m (t2 ) − (t − t2 ) . (8)
Lm
Fig. 4. Operation waveforms of the proposed converter during T s . At the secondary side, the output filter inductor current iL o
decreases as
Vo − N V b
considered constant during Ts because the switching frequency iL o (t) = iL o (t2 ) − (t − t2 ) . (9)
Lo
fs (=1/Ts ) is much faster than the line frequency fline . Before
Because iL o = iD o 2 , the primary current ip is expressed as
t = t0 , the switch S2 has been turned OFF. The voltage VS 1
across S1 is zero when the primary current ip flows through the ip (t) = iL m (t) − N iD o2 (t) . (10)
body diode DS 1 of S1 .
Mode 4 [t3 , t4 ]: At t = t3 , the boost inductor current iL b
Mode 1 [t0 , t1 ]: At t = t0 , S1 is turned ON. ZVS of S1
is zero. The magnetizing inductor current iL m decreases as (8).
is achieved when S1 is turned ON. The input current ii flows
The volt-second balance relation on the boost inductor Lb during
through Lb , D1 , and S1 . The boost inductor Lb stores energy
Ts gives the following relation:
from the line voltage vi . The boost inductor current iL b increases
as vi DTs = (Vd − vi ) ΔTs . (11)
vi By simplifying (11), the time interval ΔTs is expressed as
iL b (t) = (t − t0 ) . (2)
Lb vi DTs
ΔTs = . (12)
The magnetizing inductor current iL m increases as (Vd − vi )
Mode 5 [t4 , t5 ]: At t = t4 , S2 is turned OFF. As the primary
Vd − Vb current ip charges CS 2 and discharges CS 1 . The voltage VS 1
iL m (t) = iL m (to ) + (t − t0 ) . (3)
Lm across S1 decreases from Vd to zero, while the voltage VS 2

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 3888 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011

across S2 increases from zero to Vd . As long as the switch S1 The output filter inductor Lo should be large enough so that
is turned ON before the magnetizing current iL m changes its the output filter inductor current iL o is continuous. For the max-
direction, ZVS of S1 can be assured. At the secondary side, the imum average output current io, m ax and output filter inductor
output filter inductor current iL o freewheels through both output current ripple ΔiL o, during Ts , the following condition should
diodes Do 1 and Do 2 . The output diode current iD o 1 increases be satisfied:
while the output diode current iD o 2 decreases. Then, the ZVS ΔiL o (Vo − N Vb ) (1 − D) Ts
condition of the switch S1 is io,m ax > = . (22)
2 2Lo
1 1
Lm [iL b (t5 ) + iL m (t5 ) + iD o2 (t5 )]2 > (CS 1 + CS 2 ) Vd2 . By simplifying (22), the output filter inductor Lo should be
2 2 determined as
(13)
When VS 1 is zero at t = t5 , the primary current ip flows Vo (1 − 2D) Ts
Lo > . (23)
through the body diode DS 1 of S1 . The boost inductor current 4io,m ax
iL b is considered for the ZVS condition of S1 for each half line
period. The next switching period begins when S1 is turned ON B. Power Factor
again.
The boost inductor Lb operates at DCM. Then, the peak boost
inductor current iL b, p eak follows the line voltage vi with a fixed
IV. CIRCUIT ANALYSIS
duty ratio to supply the output power for a constant output
A. DC Characteristics voltage. Suppose that the converter is lossless and the duty ratio
is fixed, the boost inductor Lb should be determined as
From the volt-second balance relation on the magnetizing
inductor Lm during Ts , the voltage Vb across the capacitor Cb Vin2 DTs
Lb < (24)
is expressed as 2Po,m ax
Vb = DVd . (14) where Po, m ax is the maximum output power. For the positive
line period, the peak boost inductor current iL b, p eak during Ts
From the volt-second balance relation on the output filter
is expressed as
inductor Lo during Ts , the following relation between the output
voltage Vo and the dc-link capacitor voltage Vd is expressed: Vin DTs
iL b,p eak = . (25)
Vo Lb
= 2N D (1 − D) . (15) From (12) and (25), the average boost inductor current iL b, avg
Vd
during Ts is obtained as
From Mode 1, the following relation is obtained:
iL b,p eak
Vd − Vb iL b,avg = (D + Δ) Ts
iL m (t1 ) = iL m (t0 ) + DTs . (16) 2
Lm   
Vin D2 |sin ωt|
Because the primary current ip flows through the capacitor = √ √ . (26)
Cb , the average primary current ip, avg should be zero during Ts . 2Lb fs 1 − 2VV d |sin ωt|
in

The following relation can be obtained:

The average input power Pin for a half line period is expressed
ip,avg = (iL m ,avg + N Io ) DTs as
 π
+ (iL m ,avg − N Io ) (1 − D) Ts = 0 (17) 1
Pin = vi iL b,avg dωt. (27)
π 0
where iL m , avg is the average magnetizing inductor current. Io
is the average output current. From (17), The power factor can be expressed as

iL m (t0 ) + iL m (t1 ) Pin P

iL m ,avg = = (1 − 2D) N Io . (18) PF = =   in (28)
2 Vin Iin 1 π
Vin π 0 (iL b,avg )2 dωt
From (16) and (18),
where Iin is the RMS value of the input current ii .
Vd − Vb The input energy Ein absorbed for a half line period is the
iL m (t0 ) = (1 − 2D) N Io − DTs (19)
2Lm integral of the product of line voltage vi and average boost
Vd − Vb inductor current iL b, avg . Thus, we have
iL m (t1 ) = (1 − 2D) N Io + DTs . (20)
2Lm  1
2 f lin e

From (5) and (19), the primary current ip at t = t0 is expressed Ein = |vi | iL b,avg dt. (29)
0
as
For a half line period, the input energy Ein is equal to the
(1 − 2D) N Vo Ts Vo Ts output energy Eout at steady state as
ip (t0 ) = 2 (1 − D) N Io − − .
4Lo 4N Lm
(21) Ein = Eout . (30)

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 CHOI AND YOO: BRIDGELESS SINGLE-STAGE HALF-BRIDGE AC/DC CONVERTER
Fig. 5. Normalized voltage gain of the proposed converter.
Since the magnetizing inductor current iL m is continuous, the
output energy for a half line period is independent of the duty
ratio D. Then, the following relation is given as [28]
Po
Eout =
2fline
where Po is the output power. Using (1), (26), (29), (30), and
(31), the dc-link capacitor voltage Vd can be expressed in an
implicit form as
 1  
Po Lb fs 2 f lin e Vin2 |sin ωt|2
√ = √ dt. (32)
2Vd D2 fline 0 Vo − 2Vin |sin ωt|
The dc-link capacitor voltage Vd is dependent on the output
power Po . It can be calculated from (32) with a mathematical
software package since it is difficult to obtain a closed-form
solution.
C. Circuit Variation
Fig. 5 shows the normalized voltage gain Vo /Vd of the pro-
posed converter when N = 1 from (15). The voltage gain in
Fig. 5 is in a parabolic shape and symmetrical about 50% duty
ratio. Fig. 6 shows how the proposed bridgeless single-stage
PFC concept can be applied to other topology. The converter
in Fig. 6(a) has a flyback-type rectification circuit [29] at the
secondary side. It has the following relation between the output
voltage Vo and the dc-link capacitor voltage Vd :
Vo
= N D.
Vd
Fig. 6(b) shows the normalized voltage gain Vo /Vd of the
converter in Fig. 6(a) when N = 1 from (33). As the duty ratio
D increases, the normalized voltage gain will increase linearly.
Compared with the proposed converter in Fig. 1, the converter in
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3889
Fig. 6(a) has a wider duty ratio range. Compared to the proposed
converter in Fig. 1, the converter in Fig. 6(a) is more suitable for
the universal line input voltage applications due to its wide duty
ratio range. To verify the operation of the converter in Fig. 6(a)
for the universal line applications, its simulation results showing
the line input voltage vi , dc-link voltage Vd , and output voltage
Vo are shown in Fig. 6(c) and (d) for 250 W at 90 Vrm s and
265 Vrm s line voltage, respectively. Based on the simulation
results, the output voltage Vo is well regulated as Vo = 48 V,
and the dc-link voltage is under 450 V for 265 Vrm s line voltage.
V. EXPERIMENTAL RESULTS
The proposed converter in Fig. 1 has been built to verify its
performance with the following parameters:
1) line voltage vi : 90–150 Vrm s ;
2) output voltage Vo : 48 V;
3) output power Po : 250 W;
4) switching frequency fs : 50 kHz;
5) line filter inductor Lf : 1 mH;
6) line filter capacitor Cf : 2.2 μF;
7) boost inductor Lb : 50 μH;
8) magnetizing inductor Lm : 150 μH;
9) blocking capacitor Cb : 1 μF;
10) dc-link capacitor Cd : 220 μF;
11) output filter inductor Lo : 50 μH;
12) output filter capacitor Co : 2200 μF;
(31) 13) transformer turns ratio N : 0.4;
14) switch output capacitor CS : 500 pF.
The hardware circuit of the prototype is divided into two
parts: the microcontroller-based control circuit and power cir-
cuit. A single-chip microcontroller (Microchip, dsPIC30F3011)
is used for the control circuit. The output voltage is regulated
by a voltage mode controller [23]. The output voltage controller
is performed at the every switching period of 20 μs. The output
voltage is measured by using 10-bit analog-to-digital (A/D) con-
verter in the microcontroller. For the power switching devices,
S1 = S2 = FCP11N60, D1 = D2 = 1N5406, and Do 1 = Do 2 =
FFPF10UP20 S are used. Table I shows the voltage and current
stresses on the circuit components of the proposed converter for
the positive half line period. The transformer T is implemented
by using Samwha EER4242 S core (PL-11 ferrite material) with
the primary winding turns of NP = 20 and the secondary wind-
ing turns of NS = 8. The magnetizing inductor Lm = 150 μH
is realized with 0.3-mm air gap, which results in the leakage
inductor Llk = 1 μH.
Fig. 7 shows the output voltage Vo and line current ii at vi =
60 Hz/90 Vrm s for full-load condition. The measured power
factor is 0.98. The proposed converter draws almost sinusoidal
average input current with a little distortion from 90 Vrm s line
voltage. Vo is regulated as Vo = 48 V. Fig. 8 shows the normal-
(33)
ized average boost inductor current of the proposed converter
for a positive half line period. It is observed that there is a
distortion in the line current ii . The relation between the line
voltage vi and the average boost inductor current iL b, avg is non-
linear, as shown in (26). Due to the nonlinear relation between
vi and iL b, avg , the line current ii is not perfectly sinusoidal. This
 3890 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011

Fig. 6. Extension of the proposed concept to other bridgeless single-stage PFC circuits for universal-line input applications. (a) Circuit diagram of the converter.
(b) Normalized voltage gain of the converter. (c) Simulation results of the converter at 90 Vrm s line voltage. (d) Simulation results of the converter at 265 Vrm s
line voltage.

TABLE I
VOLTAGE AND CURRENT STRESSES ON THE CIRCUIT COMPONENTS OF THE
PROPOSED CONVERTER

Fig. 7. Experimental results: output voltage V o : 20 V/division; line current

ii : 2 A/division; line voltage v i : 250 V/division; time: 4 ms/division.

distortion depends on the ratio of Vin /Vd . The distortion will be
reduced as the ratio of Vin /Vd decreases.
Fig. 9 shows the boost inductor current iL b , voltage VD 1
across the diode D1 , and output filter inductor current iL o . Be-
cause the boost inductor current iL b is discontinuous, the volt-
age VD 1 across D1 pulsates relative to the ac line source with
the switching frequency. The high-frequency pulsating voltage
source may charge and discharge the equivalent parasitic ca-
pacitance between the dc-link ground and the ac line ground.
The output filter inductor current iL o is continuous. Fig. 10
shows the output voltage Vo and dc-link capacitor voltage Vd
at 90 Vrm s line voltage for full-load condition. It is observed
that the dc-link capacitor voltage Vd has 120 Hz voltage ripple
component. Meanwhile, the output voltage is tightly regulated
as Vo = 48 V. Fig. 11(a) shows the dc-link voltage trajectory
from no load to full load at 90 Vrm s line voltage. Fig. 11(b)

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 CHOI AND YOO: BRIDGELESS SINGLE-STAGE HALF-BRIDGE AC/DC CONVERTER 3891

Fig. 8. Normalized average boost inductor current of the proposed converter Fig. 10. Experimental results: output voltage V o : 50 V/division; dc-link volt-
for a positive half line period. age V d : 100 V/division, 10 ms/division.

Fig. 9. Experimental results: boost inductor current iL b : 15 A/division; volt-

age V D 1 across the diode D 1 : 100 V/division; output filter inductor current
iL o : 5 A/division, 4 μs/division.

shows the dc-link voltage trajectory from no load to full load at

150 Vrm s line voltage. The measured maximum dc-link voltage
is 355 V at 150 W for 150 Vrm s line voltage.
Fig. 12 shows the experimental waveforms at the full-load
ZVS operation. The ZVS operation is achieved by observing
that the drain-source voltage drops to zero before the gate turns
ON. Fig. 12(a) shows the primary current ip , gate signal voltage
vg s 1 , and switch voltage VS 1 . The primary current ip is negative
when VS 1 changes from Vd to zero. Before the gate signal
voltage vg s 1 is applied, the switch voltage VS 1 drops to zero. Fig. 11. DC-link voltage trajectory from no load to full load. (a) DC-link
The primary current ip flows through the body diode DS 1 of voltage trajectory at 90 Vrm s line voltage. (b) DC-link voltage trajectory at
150 Vrm s line voltage.
S1 when VS 1 is zero. ZVS of S1 is achieved when S1 is turned
ON. Fig. 12(b) shows the primary current ip , gate signal voltage
vg s 2 , and switch voltage VS 2 . Before the gate signal voltage vg s 2 The power efficiency was measured at 90 Vrm s line voltage be-
is applied, the switch voltage VS 2 drops to zero. The primary cause the power losses are significant especially at low line input
current ip flows through the body diode DS 2 of S2 when VS 2 is voltage. The two-stage converter using the conventional boost
zero. ZVS of S2 is achieved when S2 is turned ON. PFC converter [24], [25] with the APWM half-bridge dc-dc
Fig. 13(a) compares the efficiency of the proposed converter converter [26] achieves the efficiency of 91.2% for 250 W. The
with the efficiencies of the two-stage converters. The two-stage boost converter generates a high dc-link voltage around 380 V.
converters are designed for the universal line voltage ranges. The APWM half-bridge dc–dc converter generates a constant

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 3892
Fig. 12. Experimental results: waveforms at the full-load ZVS operation.
(a) Primary current ip : 10 A/division; gate signal voltage v g s 1 : 20 V/division;
switch voltage V S 1 : 250 V /division, 4 μs/division. (b) Primary current ip :
10 A/division; gate signal voltage v g s 2 : 20 V/division; switch voltage V S 2 :
250 V /division, 4 μs/division.
isolated output voltage of 48 V. The efficiency of the boost con-
verter is 95.5%. The efficiency of the APWM half-bridge dc–dc
converter is 95.5%. The two-stage converter using the bridge-
less PFC boost rectifier [27] with the APWM half-bridge dc–dc
converter [26] achieves the efficiency of 92.2% for 250 W. The
bridgeless boost rectifier generates 380 V from 90 Vrm s line
voltage. The efficiency of the boost converter is 96.5%. The
efficiency of the APWM half-bridge dc–dc converter is 95.5%.
On the other hand, the proposed converter achieves the effi-
ciency of 93.0% for 250 W. Fig. 13(b) shows the efficiency
comparison of the converters when the two-stage converters
are designed for 90 Vrm s line voltage. The two-stage converter
using the conventional boost PFC converter achieves the ef-
ficiency of 92.1% for 250 W. The boost converter generates
the dc-link voltage of 250 V from 90 Vrm s line voltage. The
APWM half-bridge dc–dc converter converts 250 V into 48 V.
The efficiency of the boost converter is 96.3%. The efficiency
of the APWM half-bridge dc–dc converter is 95.7%. The two-
stage converter using the bridgeless PFC boost rectifier achieves
the efficiency of 93.0% for 250 W. The bridgeless boost rectifier
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011
Fig. 13. Experimental results: measured efficiency of the proposed converter
compared with the efficiencies of the two-stage converters at 90 Vrm s line
voltage. (a) Measured efficiencies when the two-stage converters are designed
for the universal line voltage ranges. (b) Measured efficiencies when the two-
stage converters are designed with 250 V dc-link voltage for 90 Vrm s line
voltage. (c) Measured efficiencies when the two-stage converters are designed
with 200 V dc-link voltage for 90 Vrm s line voltage.
generates 250 V from 90 Vrm s line voltage. The efficiency of the
bridgeless boost rectifier is 97.2%. The efficiency of the APWM
half-bridge dc–dc converter is 95.7%. For a precise efficiency
comparison, the same power switching device (FCP11N60) is
used for the power switches of each dc–dc converter. The two-
stage converter, which is designed for 90 Vrm s line voltage
using the bridgeless PFC boost rectifier, achieves the same effi-
ciency as the proposed converter. Fig. 13(c) shows the efficiency
comparison when the two-stage converter using the bridgeless
PFC boost rectifier is designed with 200 V dc-link voltage for
90 Vrm s line voltage. At the rated power level, the efficiency
of the two-stage converter with 200 V is not higher than the
 CHOI AND YOO: BRIDGELESS SINGLE-STAGE HALF-BRIDGE AC/DC CONVERTER
TABLE II
MEASURED POWER FACTOR, DC-LINK VOLTAGE, AND POWER EFFICIENCY FOR
FULL-LOAD CONDITION
Fig. 14. Experimental results: measured efficiency of the proposed converter
compared with the efficiency of the previous single-stage converter at 90 Vrm s
line voltage.
efficiency of the two-stage converter with 250 V. The power
losses of the dc–dc converter increase as the dc-link voltage de-
creases. The current stress of the power switches increases as the
dc-link voltage decreases at the same power level for the two-
stage converter. Thus, it can be seen that the proposed converter
has the advantages such as less components and simpler circuit
structure compared to the two-stage converters. Table II sum-
marizes the measured full-load power factor, dc-link voltage,
and power efficiency of the proposed converter for 250 W.
Fig. 14 compares the efficiency of the proposed converter
with the efficiency of the previous single-stage converter in [9]
at 90 Vrm s line voltage. The single-stage converter in [9] is
a conventional single-stage half-bridge ac–dc converter with
a full-bridge diode rectifier. It also has a limited duty cycle
range as the proposed converter has. The voltage stress of the
power switches for the converter in [9] is the dc-link voltage,
which is higher than the peak line input voltage. Then, for
a significant efficiency comparison, the previous single-stage
converter has been built and tested for 250 W output power
level at 90 Vrm s line voltage. It has been optimally designed for
90 Vrm s line voltage with the same switching frequency as the
proposed converter. The power efficiency is measured at 90 Vrm s
line voltage because the power losses are the most significant at
the low line input voltage. The conventional single-stage half-
bridge ac–dc converter in [9] has the efficiency of 91.7% for
250 W. On the other hand, the proposed bridgeless single-stage
half-bridge ac–dc converter achieves the efficiency of 93.0% for
250 W. The efficiency of the proposed converter is higher than
the efficiency of the previous single-stage converter because
one power conversion stage is reduced without using any full-
bridge diode rectifier. Fig. 15 shows the measured line current
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3893
Fig. 15. Experimental results: measured line current harmonics at 100 Vrm s
line voltage.
harmonics at 100 Vrm s line voltage. The proposed converter can
comply with the IEC 1000-3-2 Class D specifications.
VI. CONCLUSION
As a new single-stage PFC scheme, this paper has proposed
a bridgeless single-stage half-bridge ac–dc converter. The pro-
posed converter integrates the bridgeless boost rectifier with the
APWM half-bridge dc–dc converter. The proposed converter
provides an isolated dc output voltage without using any full-
bridge diode rectifier. The proposed converter gives a high effi-
ciency by reducing the conduction losses and switching losses.
The proposed converter has the following features for the bridge-
less single-stage PFC ac–dc converters:
1) low conduction losses by essentially eliminating the full-
bridge diode rectifier;
2) reduced component counts by integrating two power con-
version stages;
3) low switching losses by the ZVS operation of power
switches;
4) simple control method for PFC and output voltage
regulation.
The performance of the proposed converter has been evalu-
ated by the experimental results based on a 250 W (48 V/5.2 A)
converter prototype. The proposed converter achieves a high-
efficiency of 93.0% and an almost unity power factor at 90 Vrm s
line voltage.
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Joo-Seung Yoo was born in Korea in 1986. He re-
ceived the B.S. degree in electronics engineering
from Chonbuk National University, Jeonju, Korea, in
2011. He is currently working toward the M.S. degree
in electronic engineering from Chonbuk National
University.
His research interest includes power converters for
energy conversion and storage systems.

Woo-Young Choi was born in Gwangju, Korea,

in 1979. He received the B.S. degree in electri-
cal engineering from Chonnam National University,
Gwangju, in 2004, and the Ph.D. degree in electronic
and electrical engineering from the Pohang Univer-
sity of Science and Technology, Pohang, Korea, in
2009.
From 2009 to 2010, he was a Postdoctoral Re-
search Fellow at Virginia Polytechnic Institute and
State University (Virginia Tech). Since 2010, he has
been with the Division of Electronic Engineering,
Chonbuk National University, Jeon-ju, Korea, where he is currently a Profes-
sor. His research interests include power converters for high-frequency power
conversion, display technology, and renewable energies.

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