2017 International Conference on Circuits, System and Simulation
Efficiency Improvement of Dual Mode DC-DC Buck Converter under Light Load
Using PTWS with a Zero Current Detector
Y oung-Ho Shin, Hak-Y un Kim, Jin-W on Kim, Seong-Y eol Choi, Y eong-Seuk Kim, Ho-Y ong Choi
Department of Semiconductor Engineering
Chungbuk National University
Cheongju, Republic of Korea
e-mail: rko147@cbnu.ac.kr
Abstract—This paper presents a dual-mode DC-DC buck
converter using power transistor width scaling (PTWS) with a
zero current detector to improve power efficiency under light
load. The buck converter is operated in a dual mode,
combining the switching frequency modulation (SFM) mode
which uses the voltage controlled oscillator (VCO) under light
load, with the PWM mode for heavy load. To enhance power
efficiency under light load a PTWS scheme is employed, in
which the inductor current is detected using a zero current
detector (ZCD) and then used to select the gate size of the
power switching transistor. The proposed circuit was designed
using a Magnachip 0.35m CMOS process. Simulation results
shows that our proposed converter has 81.3% ∼ 93% power
efficiency for output load currents of 10mA ∼ 250mA, which is
a 5.3% improvement compared to a simple SFM-PWM dual
mode and an 8.9% improvement compared to a PWM-only
mode under a light load of 10mA, respectively.
Keywords-DC-DC converter; buck converter; power
transistor width scaling; switching frequency modulation; dual-
mode
I. INTRODUCTION
In recent years, as the use of battery operated portable
devices has rapidly increased, it has been necessary to
develop highly efficient power management ICs (PMICs) to
ensure long battery life, which is required to meet the
demands of multiple functions in portable devices. Among
these PMICs, DC-DC converters are widely used in portable
devices because they provide high power efficiency [1-5]. In
portable communication devices such as mobile phones and
smart watches, etc., the load condition varies from light load
to heavy load depending on whether the device is operating
in standby mode or communication mode. Because such
portable communication devices have long usage time in the
standby mode, it is particularly important to improve the
efficiency of the DC-DC converter under light load [6].
To improve the efficiency of the DC-DC converter under
light load, pulse frequency modulation (PFM) mode is used
to reduce the switching loss [7]. However, previously some
DC-DC converters have operated with only a PW M mode,
so that the power efficiency is low under light load.
Therefore, some dual-mode approaches combining the PW M
mode and PFM mode have been proposed, to provide higher
efficiency over a wide load range [8-9]. However, the control
978-1-5386-0392-5/17/$31.00 ©2017 IEEE
circuit for switching between the PFM mode and the PW M
mode is typically complicated and large sized.
In general, a DC-DC converter requires a large sized
power switching transistor for stable operation under heavy
load [10-11]. However, the large sized power switching
transistor has a large gate capacitance, which under light load
results in high switching loss and a lot of power dissipation.
For this reason, reducing the size of the power switching
transistor is important in order to reduce power consumption
under light load.
To overcome the excess power consumption problem at
light load, some approaches have been proposed that vary the
width of the power transistor, depending on load current [10-
14]. However, additional complex circuits, such as an
inductor current detector, a rectification filter, and an analog
to digital converter (ADC) are needed to implement the load-
adaptive width scaling scheme.
In this paper, we propose a SFM-PW M dual mode DC-
DC buck converter using power transistor width scaling
(PTW S) to enhance power efficiency under light load. The
converter can be realized with simple circuits using a voltage
controlled oscillator (V CO) in the SFM-PW M dual mode,
and using a zero current detector (ZCD) in the PTW S.
This paper is organized as follows. A dual mode DC-DC
buck converter design is presented in Section II. Simulation
results of the proposed DC-DC buck converter are presented
in Section III. And finally, conclusions are drawn in Section
IV .
II. DESIGN OF DUA L -M ODE B UCK CONV ERTER USING
PTW S
This section introduces the design of a switching
frequency modulation (SFM) – pulse width modulation
(PW M) dual mode buck converter using power transistor
width scaling (PTW S). The DC-DC buck converter operates
in the SFM-PW M dual mode using a voltage controlled
oscillator (V CO). In addition, this buck converter selects the
width of the power switching transistor according to load
current using a simple PTW S controller with a zero current
detector (ZCD) to improve its power efficiency under light
load.
A. PTWS Dual-Mode Buck Converter
Figure 1 is a block diagram of the dual-mode DC-DC
buck converter using PTW S. The DC-DC converter consists
of a SFM-PW M controller which generates the switching
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signal of the power switching transistor, and a PTW S reduce switching loss, but under heavy load the DC-DC
controller which selects the width of the power switching converter has a large sized power switching transistor, to
transistor according to the load current using a ZCD for operate stably.
continuous conduction mode - discontinuous conduction By adopting the appropriate switching frequency and
mode (CCM-DCM) operation. switching transistor width depending on the load, the
converter has high power efficiency over the entire load
range.
B. Proposed PTWS
Figure 2 shows the proposed PTW S controller using
ZCD. The PTW S controller determines the different sizes of
the power switching transistor, and for this purpose is
segmented in two. The controller compares the number of
occurrences of ZCD output in the off interval of the high-
side switch to determine the load condition, and maintains
the PTW S value until the next term of the load condition
determination.
The signal of PTW S controller determines the size of the
power switching transistor. W hen the DC-DC converter is
under light load, the signal of the PTW S controller is low,
and only P (t) and N (t) power switching transistors are
turned on. In contrast, when DC-DC converter is under
Figure 1. A block diagram of the dual-mode DC-DC converter using PTWS heavy load, the signal of the PTW S controller is high and all
of the power switching transistors are turned on. The PTW S
The converter operates using a current-mode control that controller can be implemented simply using small sized
keeps the output voltage constant by detecting the output circuits because the ZCD can be implemented using an
voltage and the inductor current. W hen a load current is at existing circuit, without the additional circuit.
light load with less than the given load current, the converter
operates in the SFM mode. The SFM-PW M dual mode DC-
DC converter detects the output voltage of the error amplifier
and changes the frequency of the V CO. Then, the set clock
frequency is determined so that it is proportional to the load
current, and generates reset clock by detecting the inductor
peak current.
On the other hand, when the load current is at heavy load
with larger than the given load current, the converter
operates in the PW M method. The converter generates a
constant set clock irrespective of the load current, so that the
switching frequency is constant. Compared with the
conventional PFM-PW M dual mode, because our SFM- Figure 2. The proposed PTWS controller using ZCD
PW M dual mode doesn’t need a mode selection circuit, it
can be implemented with simple circuits with small area [9].
Our proposed DC-DC converter is segmented into two
power switching transistors using PTW S with a ZCD to
enhance the power efficiency of light load. Under light load,
when the size of the power switching transistor becomes
large, the switching loss increases due to the large gate
capacitance of the power switching transistor. Our PTW S
provides a means of reducing switching loss by selecting the
appropriate gate capacitance for the load.
Under light load the ZCD senses a negative current and
makes the DC-DC converter operate in the DCM, in which
the low-side switch of the power switching transistor is
turned off, to prevent negative inductor current from flowing
back to the source, and to reduce conduction loss.
The control circuit of the PTW S generates a control
signal to the gate driver to select a load-adaptive width for Figure 3. The waveform of the PTWS controller
the power switching transistor. Under light load the DC-DC (a) the load current 𝐼 , (b) the inductor current 𝐼 , (c) the ZCD output
voltage 𝑉 , (d) the PTWS controller output voltage 𝑉
converter has a small sized power switching transistor, to

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 Figure 3 shows the waveform of the PTW S controller
depending on load currents. In the case of a light load, the
inductor current I becomes a negative value, and the
output of ZCD, V , becomes high. A t this time, this value
is counted and the PTW S controller output V becomes
low. In contrast, for a heavy load, the output of ZCD, V ,
is not generated since the inductor current I is positive,
and the output of the PTW S controller V becomes high.
III. S IMULA TION R ESULTS
The proposed PTW S dual-mode DC-DC buck converter
was designed using the Magnachip 0.35μm CMOS process.
Figure 4 shows the output voltage simulation results for
an input voltage of 3.3V and a load current of 100mA. The
output voltage is variable from 1.4V to 2.1V , and the output
voltage ripple is 1mV to 2mV depending on the load.
Figure 4. Output voltages at a load current of 100mA
Figure 5. Control signals of PTWS controller according to load current
Fig. 5 shows the output signal of the PTW S controller
according to the load. The load switching current of the
PTW S controller is 80mA . W hen the load current is 10mA,
the output of the ZCD becomes high and operates as a DCM.
A t this time, the output of the PTW S controller becomes low,
and only the segmented power switching transistor P (t) and
N (t)are turned on, so that it has a small gate capacitance. In
contrast, when the load current becomes 80mA , the output of
the ZCD becomes low and operates as a CCM, the output of
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the PTW S controller becomes high, and all the power
switching transistors are turned on. The W /L size of the
segmented power switching transistor is 30,000μm/1μm for
high-side switches and 10,000μm/1μm for low-side switches.
Figure 6 shows the ramp signal of SFM-PW M controller
according to the load. The SFM-PW M reference load current
is 50mA, and when the load current is less than the reference
load current, it varies from 400kHz to 1.4MHz. W hen it is
larger than the set reference load current, it has a fixed
frequency of 1.4MHz.
Figure 6. Ramp signals of SFM-PWM controller
Figure 7 shows the power efficiency according to the
load current. Simulation results show that the power
efficiency of the PTW S dual mode DC-DC buck converter
with ZCD under a load range of 10mA ~ 250mA is 81.3% ~
93%. At a load current of 10mA, the PTW S method using
ZCD is 5.3% higher than a conventional SFM-PW M, and 8.9
% higher than PW M single mode.
Figure 7. Simulated power efficiency of PTWS dual-mode buck converter
using ZCD (𝑉 = 3.3  𝑉, 𝑉 = 1.8𝑉)
Table І shows a comparison of some DC-DC converters.
The results show that the power efficiency of the proposed
PTW S buck converter is higher than Lee [5] using a PFM-
PW M dual mode, and Trescases [14] using a method with
segmented power switching transistors and only the PW M
mode under light load. Also, the power efficiency of the
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