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This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2020.3002684, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 1

An Improved Discontinuous Space Vector


Modulation for Z-source Inverter with Reduced
Power Losses
Ibtissam Chaib, Student Member, IEEE, El Madjid Berkouk, Jean-Paul Gaubert, Member, IEEE,
Mostefa Kermadi, Member, IEEE, Nassereddine Sabeur, Saad Mekhilef, Senior Member, IEEE

 inverter topologies. One of them is the Z-source inverter


Abstract—This paper proposes a control strategy for a three-phase proposed by Peng [1].
Z-source inverter using a modified discontinuous space vector The Z-source inverter uses an impedance network (Z
modulation. The main advantages of the proposed control strategy network), to replace the traditional dc link. It employs an
are the enhanced output power quality and the compromise in the impedance network, that consists of split-inductors L1 and L2
reduction between conduction and switching losses. Furthermore.
and capacitors C1 and C2 connected in an X shape. It couples
The reduced switching losses are achieved by the elimination of
one switching transition in each half sector with a proper selection the inverter to the dc source, load, or another converter.
of the shoot-through state distribution. In addition, the reduced Therefore, the dc source can be a battery, a diode rectifier,
conduction losses are achieved by dividing all sectors equally into thyristor converter, fuel cell, an inductor, a capacitor, or a
30°. MATLAB/SIMULINK simulation is carried out to verify the combination of those [1]. Compared to the conventional two-
effectiveness of the proposed control strategy and compare it with level three-phase inverter which has six active vectors and two
the existing space vector modulation techniques that utilize zero vectors, the commutation cell of the two-level three-phase
distributions of four and six shoot-through vectors. PLECS Z-source inverter bridge has one extra state, called the shoot-
software is used for conduction and switching losses calculation. through state. This state can be generated when both switches
Compared to the other modulation techniques, the key features of
of any one phase leg are gated on. This state can be generated
the proposed control strategy are the improved boosting capability
of the output voltage, the low total harmonic distortion, the in seven different ways: shoot-through via any one phase leg,
reduced conduction and switching losses, and the reduced combinations of any two-phase leg, and all three-phase legs.
inductance current ripple. An experimental test-bench that The Z-source inverter advantageously uses the shoot-through
comprises of a three-phase Z-source inverter feeding an R load, states to buck and boost the dc bus voltage to the desired output
controlled by a dSPACE MicroLabBOX, is used to verify voltage. The equivalent circuit and the model of the Z-source
experimentally the effectiveness of the proposed control strategy. inverter have been studied in [1]. The Z-source inverter is
It is envisaged that the proposed control strategy can be very recently integrated into a wide range of applications: in
useful for electrical drive applications integrating three-phase Z- electrical and hybrid vehicles [2-4], in renewable power
source inverter due to its capability to improve the output
generation systems such as photovoltaic system [5-9], wind
waveform and reduce the harmonic distortions, switching and
conduction losses. turbine systems [10-12]. Furthermore, the Z-source inverter is
Index Terms— Z-source inverter, space vector, pulse width used as a multilevel inverter in [13-15].
modulation, shoot-through control, Discontinuous Space Vector To control the duty cycle of the shoot-through, researchers
Modulation. investigated several modified and space vector pulse width
modulation (SVPWM) techniques [16]. In conventional carrier-
I. INTRODUCTION based PWM methods, the switching sequence is modified by
In power conversion systems, the traditional inverter can introducing the shoot-through into the vectors state without
provide only buck output voltage and its maximum output compromising the active states. Hence a several modified PWM
voltage cannot exceed the dc-link voltage. In two-level were proposed: simple boost control [1]. maximum boost
inverters, the upper and the lower power switch of each phase control [17], constant boost control [18] and maximum constant
leg cannot be turned on at the same time. Otherwise, shoot- boost control [19]. Each strategy has its advantages and
through would occur and the power semiconductor switching inconveniences that were discussed and compared in terms of
devices will be destroyed. To overcome such limitations, switching losses, current ripple, total harmonic distortion THD
several recent research studies proposed different improved and boosting ability in [16, 20, 21]. However, the major
common drawback in all the above-mentioned strategies is the

Manuscript received January 29, 2020; revised March 10, 2020; accepted J. P. Gaubert is with the Automatic Control and Industrial Data Processing
May 24, 2020. This work was supported by National Polytechnic School of Laboratory, University of Poitiers, France
Algiers (ENP), Algeria and University of Malaya, Malaysia, under Impact (e-mail: jean.paul.gaubert@univpoitiers.fr).
Oriented Interdisciplinary Research Grant (IIRG): IIRG011A-2019, and M. Kermadi (Corresponding Author), N. Sabeur and S. Mekhilef are with
Ministry of Higher Education, Malaysia under Large Research Grant Scheme the Power Electronics and Renewable Energy Research Laboratory (PEARL),
(LRGS): LR008-2019. Department of Electrical Engineering, University of Malaya, Kuala Lumpur
I. Chaib and E. M. Berkouk are with the Laboratory of Process Control 50603, Malaysia. (e-mails: mostefa@um.edu.my, nasser@um.edu.my,
(LCP), National Polytechnic School of Algiers (ENP), 16200, Algeria (e-mails: saad@um.edu.my).
ibtissam.chaib@g.enp.edu.dz, el_madjid.berkouk@g.enp.edu.dz).

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2020.3002684, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 2

fact that the generation of the shoot-through can be occurred by The remainder of this paper is organized as follows: Section
the combination of the three legs, which increases the switching II presents a brief description of the Z-source inverter (ZSI). In
losses, although the shoot-through can be generated only by one Section III, ZSVPWM with of 4 and 6 shoot-through states
leg. To overcome the limitations of modified PWM, authors in distributions are reviewed. The proposed DZSVPWM is
[22] proposed a modified space vector PWM (SVPWM) for the described in Section IV. Comparative simulation with 4-
Z-source inverter, in which the shoot-through can be generated ZSVPWM and 6-ZSVPWM is made in Section V. Hardware
by using only one leg. As highlighted in [23], the SVPWM is results and discussions are presented in Section VI. The
easy to implement and has better performance than the modified conclusion is presented in Section VII.
PWM with reduced total harmonic distortion and lower current
ripple. The modified SVPWM for Z-source inverter II. THE Z-SOURCE INVERTER
(ZSVPWM) gives the possibility to find the best distribution of Fig. 1 shows the topology of the Z-source inverter. It
the shoot-through state between the vectors state to reduce the consists of an impedance network: inductors L1 and L2 and
switching losses by using only one switch in each transition. capacitors C1 and C2 connected in X shape linked with a dc
Hence, many ZSVPWMs have been developed to control the source. The impedance network is feeding a three-phase
duty ratio of the shoot-through [24-26]. In recent literature, inverter. The latter supply a resistive load through an LC filter.
ZSVPWM techniques with four shoot-through vectors The Z-source inverter has two main operating modes, shown in
distribution (4-ZSVPWM) and 6 shoot-through distribution (6- Fig. 2. Fig. 2(a) shows the equivalent circuit during the shoot-
ZSVPWM) were presented in [27, 28], and in [29], through state where the upper and the lower switches of any
respectively. Both 4-ZSVPWM and 6-ZSVPWM have 12 legs are turns on. Q represents the equivalent switch during the
switching transitions. The advantage of the 6-ZSVPWM is that shoot-through state. Fig. 2(b) shows the equivalent circuit
it uses only one leg to generate the shoot-through in each during the non-shoot-through state where the inverter bridge
switching cycle while the 4-ZSVPWM uses two legs separately works as a traditional inverter [1].
to generate the shoot-through state for each switching cycle. As verified in detail in [1], the basic principle relationship for
Despite having high performance, ZSVPWMs suffer from ZSI is:
minimal power transfer due to the utilization of zero voltage 1−d T
Vc1 = Vc2 = Vc = V , d = sht (1)
vectors (000) and (111) in all sectors. In addition, ZSVPWM 1−2d dc T
suffers from high THD since all the switches have at least two Where
1
transitions in each switches cycle [30]. To enhance the V = 𝑉 = BVdc non shoot − through state
switching losses, researches proposed the discontinuous Space { i 1−2d 𝑑𝑐 (2)
Vi = 0 shoot − through state
Vector pulse width modulation D-ZSVPWM for the Z-source
inverter in [30-32]. Despite the efficiency of the D-ZSVPWM 1
in terms of reducing the switching losses and maximizing the 𝐵= (3)
1−2𝑑
power transfer, the conduction losses are appeared to be a
challenging problem. This is due to holding on the switches in where 𝑉𝑐1 and 𝑉𝑐2 are capacitors voltage of impedance network
full conduction throughout the 60° interval [33]. which are the same due to circuit symmetry. B is the boost
To overcome the above-mentioned limitations, this work factor of ZSI. 𝑉𝑑𝑐 and 𝑉𝑖 denote the input and output voltages
proposes an improved discontinuous space vector pulse width of impedance network respectively. d is the shoot-through duty
modulation (ID-ZSVPWM) to control the Z-source inverter. To 𝑇
ratio d = 𝑠ℎ𝑡⁄𝑇 ; 𝑇𝑠ℎ𝑡 is the total shoot-through time interval; 𝑇
reduce the conduction losses and maintain low switching losses,
each sector 60° is split by two, thus dividing the alpha-beta is the control cycle.
plane by 12 sectors of 30°. By doing so, the switches stay in full VL
D
conduction only for 30° instead of 60°. In the proposed ID- iL
L1
ZSVPWM, the shoot-through states are introduced without C1 C2
s1 s2 s3
Lf RL
compromising the active states or affecting the invariable a
Vc Vi b
switches in each switching cycle. The proposed ID-ZSVPWM Vdc
c
N

has the following merits: 1) enhanced output waveforms quality Cf


s4 s5 s6
and reduced THD due to the wise vectors’ distribution, 2) L2

reduced conduction losses due to the sectors divisions into


subsectors, and 3) ensured maximum power transfer is
guaranteed due to the minimal use of the zero states. The Fig. 1. Block diagram of the Z-source inverter.
L1 L1
effectiveness of the proposed control strategy is verified D iL iLoad idc D iL iLoad
through simulation using MATLAB/SIMULINK and PLECS
Vc Q
software. Besides, an experimental test is carried out using a Vdc Vi
RLoad
Vdc Vc
C Q
Vi
RLoad

reduced scale Z-source inverter laboratory prototype controlled


by dSPACE MicroLabBOX to validate the simulation.
(a) (b)
Fig. 2. Equivalent circuits of the Z-source inverter:
(a) shoot-through state
(b) Non shoot-through state.

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of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 3

III. CONVENTIONAL Z-SOURCE SPACE VECTOR PULSE WIDTH 𝑇0


MODULATION ZSVPWM 𝑑𝑚𝑎𝑥 = ( ) =1−𝑟 (9)
𝑇𝑠 𝑚𝑖𝑛
The traditional SVPWM is defined by eight (8) vectors, six (6)
active vectors and two (2) zero vectors. The active vectors By replacing (7) in (8), dmax can be rewritten as follows:
divide the space vector plane into six (6) equal magnitude √3 (10)
sectors, as shown in Fig. 3. The magnitudes are normalized with 𝑑𝑚𝑎𝑥 = 1 −𝑚
2
respect to the dc bus voltage 𝑉𝑑𝑐 [34]. The time interval of the The boosting factor, denoted by B, is calculated using the
active and the zero vectors can be defined as [35] [36]: following equation:
1
𝜋 𝜋
𝑇1 = 𝑇𝑠 𝑟 sin [ − 𝜃 + (𝑖 − 1)] 𝐵= (11)
3 3 √3. 𝑚 − 1
𝜋 (4)
𝑇2 = 𝑇𝑠 𝑟 sin [𝜃 + (𝑖 − 1)] Due to the significant capabilities of the implementation of the
3
{ 𝑇0 = 𝑇𝑠 − 𝑇1 − 𝑇2 SVPWM in discrete systems, it has been widely used for the Z-
β-axis source inverter. Therefore, researchers modified the SVPWM
by introducing the shoot-through states into the zero vectors
V3(010) V2(110)
without compromising the active states. Two main control
III
II strategies were proposed in the literature: 4-ZSVPWM where
T2 Uref
V0(000)
the desired total shoot-through time interval is equally divided
V4(011)
V7(111)
I V1(100) into four (4) parts per control cycle as shown in Fig. 4 [27]. 6-
T1 α-axis ZSVPWM where the desired total shoot-through time interval
IV
VI
is equally divided into six (6) parts per control cycle as shown
V
in Fig. 5 [29].
V5(001) V6(101)
S1

S2
(a)
S3
S1
S4
S2
S3 S5
S4
S5 S6

S6
T1/2 T2/2 T2/2 T1/2
(T0-Tsh)/4 (T0-Tsh)/4 (T0-Tsh)/4 (T0-Tsh)/4

T0/4 T1/2 T2/2 T0/4 T0/4 T2/2 T1/2 T0/4 Ts/2 Ts/2

Ts/2 Ts/2 Fig. 4. Switching sequence for 4-ZSVPWM in sector 1.


(b)
Fig. 3. SVM for traditional VSIs. (a) Basic voltage space vectors. (b)
S1
Switching time sequence.
S2
𝑇1 𝑇2
𝑈𝑟𝑒𝑓 = 𝑈1 + 𝑈2 (5) S3

𝑇𝑠 𝑇𝑠 S4
where 𝑖 ∈ {1,2, … ,6} denotes the 𝑖𝑡ℎ sector; T0 is the time S5
interval of the zero vector U0 ; T1 and T2 are the time intervals
of active vectors U1 and U2 , respectively. θ is the inclined
S6

angle of the voltage reference vector Uref , Vi is the dc-bus T1/2 T2/2 T2/2 T1/2

voltage. r is given as follows: T0/4 -Tsh/6 T0/4 -Tsh/6 T0/4 -Tsh/6 T0/4 -Tsh/6

𝑈𝑟𝑒𝑓 Ts/2 Ts/2

𝑟 = √3 (6)
𝑉𝑖 Fig. 5. Switching sequence for 6-ZSVPWM in sector 1.
Since 𝑇0 -𝑑𝑇𝑠 ≥ 0, the following condition can be always
guaranteed: IV. PROPOSED ID-ZSVPWM
𝑇0 (7) The proposed ID-ZSVPWM aims to reduce the total harmonic
𝑑≤
𝑇𝑠 distortion of the output signal by and compromise between the
conduction losses reduction and the reduction of switching
The modulation index m is given by losses. This objective is achieved by the elimination of one
Uref switching transition in each half sector for 30° with a proper
𝑚= (8)
Vi ⁄2 selection of the shoot-through state distribution. In this strategy,
dmax denotes the maximum of the duty cycle, it can be calculated each sector is divided into two sub-sectors. Hence the number
using the following equation: of sectors becomes 12 sectors of 30° for each one as shown in

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of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 4

Fig. 6. Each subsector has only one zero vector either 𝑉0 (000)
or 𝑉1 (111) at the beginning or the end of each switching
S1
sequence. Table 1 list the switching sequence of the proposed
ID-ZSVPWM and the switching sequence of the conventional S2
Z-source SVPWM. S3

TABLE 1 S4
SWITCHING SEQUENCE IN SIX SECTORS S5
Sector Conventional sequence ID-ZSVPWM sequence
S6
(𝑉0 𝑉1 𝑉2 𝑉1,𝑉1 𝑉2 𝑉1 𝑉0)
(𝑉0 𝑉1 𝑉2 𝑉7,𝑉7 𝑉2 𝑉1 𝑉0) V0 V1 V2 V1 V1 V2 V1 V0
Vth Vth Vth Vth
I
(𝑉7 𝑉2 𝑉1 𝑉2,𝑉2 𝑉1 𝑉2 𝑉7) T1/4 T2/2 T1/4 T1/4 T2/2 T1/4
(𝑉7 𝑉2 𝑉3 𝑉2 ,𝑉2 𝑉3 𝑉2 𝑉7 ) T0/2-Tsh/4 T0/2-Tsh/4
II (𝑉0 𝑉3 𝑉2 𝑉7 ,𝑉7 𝑉2 𝑉3 𝑉0 )
(𝑉0 𝑉3 𝑉2 𝑉3 ,𝑉3 𝑉2 𝑉3 𝑉0 ) Ts/2 Ts/2

(𝑉0 𝑉3 𝑉4 𝑉3,𝑉3 𝑉4 𝑉3 𝑉0 ) (a)


III (𝑉0 𝑉3 𝑉4 𝑉7,𝑉7 𝑉4 𝑉3 𝑉0 )
(𝑉7 𝑉4 𝑉3 𝑉4,𝑉4 𝑉3 𝑉4 𝑉7)
(𝑉7 𝑉4 𝑉5 𝑉4,𝑉4 𝑉5 𝑉4 𝑉7)
IV (𝑉0 𝑉5 𝑉4 𝑉7,𝑉7 𝑉4 𝑉5 𝑉0 )
(𝑉0 𝑉5 𝑉4 𝑉5,𝑉5 𝑉4 𝑉5 𝑉0 ) S1
(𝑉0 𝑉5 𝑉6 𝑉5 ,𝑉5 𝑉6 𝑉5 𝑉0 )
V (𝑉0 𝑉5 𝑉6 𝑉7 ,𝑉7 𝑉6 𝑉5 𝑉0 ) S2
(𝑉7 𝑉6 𝑉5 𝑉6 ,𝑉6 𝑉5 𝑉6 𝑉7 )
(𝑉7 𝑉6 𝑉1 𝑉6,𝑉6 𝑉1 𝑉6 𝑉7) S3
VI (𝑉0 𝑉1 𝑉6 𝑉7,𝑉7 𝑉6 𝑉1 𝑉0)
(𝑉0 𝑉1 𝑉6 𝑉1,𝑉1 𝑉6 𝑉1 𝑉0) S4
β-axis S5
V3(010) V2(110)

(0323,3230) (7232,2327) S6
V7 Vth V2 Vth V1 V2 V2 V1 Vth V2 Vth V7

(0343,3430) (7212,2127) I T2/4 T1/2 T2/4 T1/2


T2/4 T2/4
T0/2-Tsh/4 T0/2-Tsh/4
II Ts/2 Ts/2

III Uref
(b)
(7434,4347) T2
(0121,1210) Fig. 7. Switching sequence for ID-ZSVPWM in sector1 (a) when 𝜃 < 30° (b)
V0(000) when 𝜃 > 30°.
V7(111) 30°
V4(011) V1(100)
T1 α-axis V. RESULTS & DISCUSSION
IV
(7454,4547)
VI (0161,1610) To evaluate the performance of the proposed ID-ZSVPWM
V strategy, simulation using Matlab/SIMULINK software and
experiment are carried out. As shown in Fig.8, the system
(0545,5450) (7616,6167) consists of a Z-source inverter linked with a dc source, feeding
(0565,5650) (7656,6567)
a three-phase resistive load through an LC filter. The main
parameters of the described system are listed in Table 3. This
V5(001) V6(101) simulation aims to compare the proposed strategy with 4-
ZSVPWM and 6-ZSVPWM, in term of the dc-bus voltage
boosting, and the current and voltage THD reduction. The
Fig. 6. voltage space vectors for the ID-ZSVPWM strategy.
obtained simulation results are listed in Table.4.
The simulation results in continuous time mode for the 4-
Unlike in the conventional Z-source SVPWM the shoot-
ZSVPWM, 6-ZSVPWM, and ID-ZSVPWM, are plotted in Fig.
through state is distributed properly in the proposed ID-
9, Fig. 10 and Fig. 11 respectively, where the inverter dc-bus
ZSVPWM, without changing the state of the maintained
switches in each switching cycle. Table 2 lists the switching Vi , the Z-source capacitor voltage Vc , and the input DC-source
sequence and the distribution of the shoot-through state in each voltage Vdc are plotted in figure part (a), the inductance current
subsector for a half switching cycle. Four shoot-through states IL is shown in figure part (b), and the current and voltage output
are inserted in each switching cycle without affecting the active FFT analysis are shown in figure parts (c) and (d) respectively.
states with a duration of 𝑇𝑠ℎ ⁄4 without affecting the active For Vdc=10 V, d=0.3 and a modulation index m=0.8, the
states. The proposed switching sequence for the ID-ZSVPWM boost factor for 4-ZSVPWM is equal to 𝐵4−ZSVPWM = 1.9 and
for the first sub-sector is shown in Fig. 7(a) and Fig. 7(b) the 𝑇𝐻𝐷4−ZSVPWM = 0.74% as shown in Fig. 9.
respectively. as shown in Fig. 7, in the first sub-sectors S3 is Although, for the 6-ZSVPWM strategy, the boost factor is
maintained off and S6 is maintained on. In the second sub-
increased to 𝐵6−ZSVPWM = 2.54, and the THD is reduced
sector, S1 is maintained on and S4 is maintained off. And this
procedure repeats in each sub-sector (30°) for different legs. 𝑇𝐻𝐷6−ZSVPWM = 0.7% as shown in Fig.10, the proposed
This procedure ensures the reduction of conduction losses and strategy shows better results. where the boost factor is increased
maintain lower switching losses. to 𝐵ID−ZSVPWM = 2.6, with an improved 𝑇𝐻𝐷ID−ZSVPWM =
0.17% as shown in Fig.11 The current output THD and the
voltage output THD show the same patterns due to the resistive
load.

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of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 5

TABLE 2
THE DISTRIBUTION OF THE SHOOT-THROUGH STATES BETWEEN THE SWITCHING SEQUENCES FOR THE ID-ZSVPWM
Sector subsector switches 𝐓𝟎 𝐓𝐭𝐡 𝐓𝟏 𝐓𝐭𝐡 𝐓𝟐 𝐓𝟏
Sector I (𝑉0 𝑉1 𝑉2 𝑉1,𝑉1 𝑉2 𝑉1 𝑉0) (S1 S2 S3 ) 000 100 100 110 110 100
(S4 S5 S6 ) 111 111 011 011 001 011
(𝑉7 𝑉2 𝑉1 𝑉2,𝑉2 𝑉1 𝑉2 𝑉7) (S1 S2 S3 ) 111 111 110 110 100 110
(S4 S5 S6 ) 000 001 001 011 011 001
Sector II (𝑉7 𝑉2 𝑉3 𝑉2 ,𝑉2 𝑉3 𝑉2 𝑉7 ) (S1 S2 S3 ) 111 111 110 110 010 110
(S4 S5 S6 ) 000 001 001 101 101 001
(𝑉0 𝑉3 𝑉2 𝑉3 ,𝑉3 𝑉2 𝑉3 𝑉0 ) (S1 S2 S3 ) 000 010 010 110 110 010
(S4 S5 S6 ) 111 111 101 101 001 101
Sector III (𝑉0 𝑉3 𝑉4 𝑉3,𝑉3 𝑉4 𝑉3 𝑉0 ) (S1 S2 S3 ) 000 010 010 011 011 010
(S4 S5 S6 ) 111 111 101 101 100 101
(𝑉7 𝑉4 𝑉3 𝑉4,𝑉4 𝑉3 𝑉4 𝑉7) (S1 S2 S3 ) 111 111 011 011 010 011
(S4 S5 S6 ) 000 100 100 101 101 100
Sector IV (𝑉7 𝑉4 𝑉5 𝑉4,𝑉4 𝑉5 𝑉4 𝑉7) (S1 S2 S3 ) 111 111 011 011 001 011
(S4 S5 S6 ) 000 100 100 110 110 100
(𝑉0 𝑉5 𝑉4 𝑉5,𝑉5 𝑉4 𝑉5 𝑉0 ) (S1 S2 S3 ) 000 001 001 011 011 001
(S4 S5 S6 ) 111 111 110 110 100 110
Sector V (𝑉0 𝑉5 𝑉6 𝑉5 ,𝑉5 𝑉6 𝑉5 𝑉0 ) (S1 S2 S3 ) 000 001 001 101 101 001
(S4 S5 S6 ) 111 111 110 110 010 110
(𝑉7 𝑉6 𝑉5 𝑉6 ,𝑉6 𝑉5 𝑉6 𝑉7 ) (S1 S2 S3 ) 111 111 101 101 001 101
(S4 S5 S6 ) 000 010 010 110 110 010
Sector VI (𝑉7 𝑉6 𝑉1 𝑉6,𝑉6 𝑉1 𝑉6 𝑉7) (S1 S2 S3 ) 111 111 101 101 100 101
(S4 S5 S6 ) 000 010 010 011 011 010
(𝑉0 𝑉1 𝑉6 𝑉1,𝑉1 𝑉6 𝑉1 𝑉0) (S1 S2 S3 ) 000 100 100 101 101 100
(S4 S5 S6 ) 111 111 011 011 010 011

The proposed ID-ZSVPWM has the highest boost factor MicroLabBOX controls the switches through an IGBT Driver
𝐵ID−ZSVPWM = 2.6, the lowest total harmonic distortion, and an SKHI 23/12 (R) with a switching frequency equals to 𝑓𝑠𝑤 =2.5
acceptable inductance current ripple ∆𝐼𝐿𝑍 = 0.325A. Thus, the kHz and a sampling time equal to 𝑓𝑠 =25 kHz.
proposed ID-ZSVPWM outperforms the other methods in terms The obtained experimental results are listed in Table. 5 for a
of 1) enhancing the signal quality of the ac output voltage modulation index m=0.8 and a duty cycle equal to d=0.3, as
waveform (reduced THD), 2) ensuring the highest boost factor
of the dc-link voltage, and 3) maintaining a good current ripple shown in Fig. 13. The measurement of the dc-Bus ( 𝑉𝑑𝑐 (𝑣),
in the inductance. 𝑉𝑐 (𝑣), 𝑉𝑖 (𝑣); 𝐼𝐿 (𝐴)) are presented in Fig.13 (a) and Fig.13 (b).
D iL
VL
Electrical Diagram In addition, the zoomed waveform of 𝑉𝑑𝑐 , 𝑉𝑖 , 𝑉𝑐 , and the
inductor current 𝐼𝐿 within five (5) control cycles (2e-3 s) are
L1
s1 s2 s3
C1 C2 Lf RL

Vdc Vc Vi a iLoad plotted in Fig. 13 (c). It can be seen from Fig. 13(a) and Fig.
b N
c 13(b) that the ID-ZSVPWM present a small current inductor
ripple value ∆𝐼𝐿ID−ZSVPWM = 0.47A. Beside the voltage 𝑉𝑖 (𝑣)
s4 s5 s6 Cf
L2

Vref
Va
Vα Im
Uref
T1 equals to 16.5V, the voltage 𝑉𝑐 (𝑣) equals 13.9V, resulting in a
αβ V3(010) V2(110)
T2
Vb V4(011) V1(100)
Switching
Switching pulses
boost factor equals to 1.65. The digital controller successfully
Vβ Re
times T0
Vc abc V5(001) V6(101)
θ calculator Tsh
for each phase generates the appropriate switching gate signals to achieve the
Control Diagram
desired output waveform. From the waveforms of Fig. 13(c), it
Fig. 8. Complete block diagram of Z-source system.
can be seen that the switching sequence presented in Fig. 7 is
successfully generated using the ID-ZSVPWM. The
TABLE 3 distribution of the ST into four periods per control cycle appears
SIMULATION PARAMETERS in the experimental waveforms, and 𝑉𝑖 becomes zero and 𝐼𝐿
𝑉𝑑𝑐 m d 𝐿𝑧 𝐶𝑧 𝑓𝑠𝑤 𝑓𝑠 𝐿𝑓 𝐶𝑓 RL increases during ST periods. The measurement of the AC-Bus
2.5 25
10 V 0.8 0.3 5mH 3.3mF
kHz kHz
20mH 110μF 20.7Ω (the current load 𝐼𝑙𝑜𝑎𝑑 (𝐴), the line to line voltage 𝑉𝑎𝑏 (𝑣), the
phase voltage 𝑉𝑎𝑛 (𝑣), resistive load voltage 𝑉𝑅𝑒𝑠 (𝑣)) are
To validate the proposed strategy experimentally, a prototype presented in Fig. 13(d), where the voltage across the resistor is
of Z-source inverter feeding a three-phase resistive load ̂ 𝑅𝑒𝑠 = 10 𝑉 , the phase voltage is 𝑉𝑎𝑛 (𝑣) = 12.8 𝑉. Hence,
𝑉
through an LC filter was built as shown in Fig. 12. The
the inverter factor is G=1.28 which is nearly equal to the
operation parameters used in the simulation and listed in Table
theoretic value. The simulation and experimental results are
3 are used for the experiment. A Chroma 62150H-600S/1000S
Solar Array Simulator was used as a dc power supply. The similar, which validate the performance of the proposed control
proposed ID-ZSVPWM strategy is implemented through a scheme.
dSPACE MicroLabBOX controller. The dSPACE

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 6

𝑽𝒊 (𝒗) 𝑽𝒄 (𝒗) 𝑽𝒅𝒄 (𝒗)

(a) (b)

(c) (d)
Fig. 9. 4-ZSVPWM Simulation results (a) 𝑉𝑑𝑐 (𝑣), 𝑉𝑐 (𝑣), 𝑉𝑖 (𝑣) voltages; (b) inductance current 𝐼𝐿 (𝐴); (c) current FFT analysis; (d) voltage FFT
𝑽 (𝒗) 𝑽𝒄 (𝒗) analysis.
𝒊

𝑽𝒅𝒄 (𝒗)

(a) (b)

(c) (d)
Fig. 10. 6-ZSVPWM Simulation results (a) 𝑉𝑑𝑐 (𝑣), 𝑉𝑐 (𝑣), 𝑉𝑖 (𝑣) voltages; (b) inductance current 𝐼𝐿 (𝐴);(c) current FFT analysis; (d) voltage FFT
analysis.

𝑽𝒊 (𝒗) 𝑽𝒄 (𝒗) 𝑽𝒅𝒄 (𝒗)

(a) (b)

(c) (d)
Fig. 11. ID-ZSVPWM Simulation results (a) 𝑉𝑑𝑐 (𝑣), 𝑉𝑐 (𝑣), 𝑉𝑖 (𝑣) voltages; (b) inductance current 𝐼𝐿 (𝐴);
(c) current FFT anlysis; (d) voltage FFT anlysis.

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of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 7

PLECS software is used to measure and compare the


conduction and switching losses dissipated by the six switches
3Phase inverter
IGBT IKQ120N60T in the steady-state for a rated power of 3
KW. For each strategy, the measurements are taken for a
different modulation index values [0.7-1.1] as shown in Fig.14.
The measurement of switching losses, conduction losses, and
Z-source dSPACE total power losses are shown in Fig. 14(a), Fig. 14 (b), and Fig.
Load MicroLabBox
impedance 14 (c), respectively. It can be concluded from Fig. 14(c) that the
power losses increase with the rise of the modulation index in
all three strategies. This can be attributed to the increase of
Oscilloscope
power transfer with the height of 𝑇1 and 𝑇2 . Furthermore, the
rate of power losses for high modulation index are 8.83%,
Host computer Dc power supply 9.54% and 6.33% for 4-ZSVPWM, 6-ZSVPWM, and ID-
Fig.12. Hardware prototype. ZSVPWM, respectively. As can be seen from the analysis of
the power losses, the proposed ID-ZSVPWM ensures the
lowest power losses rate for high modulation index. At m=0.7,
the power losses of ID-ZSVPWM equals 118.82W while for 4-
𝑰𝑳 (𝑨)
ZSVPWM, it equals 106.52W. Hence, the losses of 4-
𝑽𝒊 (𝒗)
ZSVPWM are 10.36% less than that of using ID-ZSVPWM.
𝑽𝒄 (𝒗) 𝑽𝒅𝒄 (𝒗) Nevertheless, the values are very close to each other. However,
for a higher modulation index, the advantages of the proposed
in reducing the power losses appear. If we take m=1.1, the
power losses of the proposed ID-ZSVPWM is lower by 28.28%
than that achieved using 4-ZSVPWM.
(a)
TABLE 5
EXPERIMENTAL RESULTS
G 1.28
𝑰𝑳 (𝑨)
𝑽𝒊 (𝒗) B 1.65

𝑽𝒄 (𝒗) 𝑽𝒅𝒄 (𝒗)


𝑽𝒄 (V) 13.9
𝑽𝒊 (V) 16.5
𝑽𝑹𝒆𝒔𝒎𝒂𝒙 (V) 10
𝑽𝒂𝒏𝒎𝒂𝒙 (V) 12.8
𝑽𝒂𝒃𝒎𝒂𝒙 (V) 16.5
𝑰𝑳𝒐𝒂𝒅𝒎𝒂𝒙 (A) 0.53
(b)
𝑰𝑳𝒎𝒊𝒏 (A) 0.73
𝑰𝑳𝒎𝒂𝒙 (A) 12
∆𝑰𝑳 (A) 0.47
∆𝑰𝑳⁄𝑰𝑳 0.487

The power loss of the inverter main bridge as a function of


switching frequency for m = 0.8 and d = 0.3 is plotted in Fig.
15. The switching losses increase when the switching frequency
(c) increases and becomes significant after 20 kHz for all the
𝑰𝑳𝒐𝒂𝒅 (𝑨) strategies. Besides, 6-ZSPWM has the highest switching losses
𝑽𝒂𝒃 (𝒗)
due to the number of transitions per control cycle (6 times
shoot-through), 4-ZSVPWM and the ID-ZSVPWM have a
close dissipated power with a better performance of the
proposed strategy. Moreover, Fig. 15(a) shows that the
conduction losses are almost constant for all the strategies
𝑽𝑹𝒆𝒔 (𝒗)
𝑽𝒂𝒏 (𝒗)
regardless the changing the switching frequency. This means
that the changing of the switching frequency changes only the
switching losses and has no influence on the conduction losses.
(d)
Fig. 13. Experimental results for the ID-ZSVPWM m=0.8: The results show that beyond all the cited strategies, the ID-
(a) (b) (c): DC-Bus measurement. (d): AC-Bus measurement. ZSVPWM is the best compromise between switching losses
and conduction losses, without reducing the signal output
quality especially for the high modulation index, which
confirms the efficiency of the proposed strategy.

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 8

4-ZSVPWM 6-ZSVPWM ID-ZSVPWM


250 4-ZSVPWM 6-ZSVPWM ID-ZSVPWM
2000

Power Losses (w)


200
Switching Losses

1500
150
1000
100
500
50
0
0
5 10
20 30 50 100
0,7 0,8 0,9 1,1 Frequency (kHz)
Modulation index
(c)
(a) Fig. 15. Power loss in the main bridge inverter versus the switching frequency
4-ZSVPWM 6-ZSVPWM ID-ZSVPWM (a): switching losses, (b): conduction losses, and (c): total power losses.
60
Conduction Losses

40 VI. CONCLUSION
In this investigation, the aim is to assess a new proposed
20 strategy, for the three-phase Z-source inverter named ID-
ZSVPWM. The most challenging problem in the control
0 strategy for the Z-source inverter is to provide a good signal
0,7 0,8 0,9 1,1
Modulation index quality with reduced power losses. The proposed ID-ZSVPWM
(b) reduces the conduction losses and maintains lower switching
4-ZSVPWM 6-ZSVPWM ID-ZSVPWM losses by 1) the division of each sector to two subsectors of 30°,
400
2) maintaining two switches of one leg (one is on while the
other is off) in the steady-state of each subsector, and 3) with
Power Losses

300
wise distribution of four (4) shoot-through state in the switching
200
period. The ID-ZSVPWM has been compared with the 4-
100 ZSVPWM and 6-ZSVPWM strategies, it has been shown from
MATLAB simulation, PLECS measurements and experimental
0
results that the proposed ID-ZSVPWM strategy has lower
0,8 0,9 0,7 1,1
Modulation index conduction losses, lower switching losses for the high
(c) modulation index, and has a lower current/voltage THD, lower
Fig. 14. Power losses in the main bridge versus the modulation index current ripple in the inductors, and higher boost factor.
(a): switching losses, (b): conduction losses, and (c): total power losses.
ACKNOWLEDGMENT
The authors would like to thank National Polytechnic School
of Algiers (ENP), Algeria and University of Malaya, Malaysia,
4-ZSVPWM 6-ZSVPWM ID-ZSVPWM for providing financial support under Impact Oriented
100
Conduction Losses (w)

80
Interdisciplinary Research Grant (IIRG): IIRG011A-2019, and
Ministry of Higher Education, Malaysia under Large Research
60
Grant Scheme (LRGS): LR008-2019.
40
20
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of Emerging and Selected Topics in Power Electronics
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of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 10

Utilisation (EPQU), 2011 11th International


Jean-Paul Gaubert He received the Engineer’s degree
Conference on, 2011, pp. 1-7.
from the University of Clermont-Ferrand, France, in
[30] B. Barathy, A. Kavitha, and T. Viswanathan, 1988, the M. Sc. and the Ph.D. degrees from the
"Effective space vector modulation switching University of Science and Technology of LILLE,
sequence for three phase Z source inverters," IET France, in 1990 and 1992 respectively, and
accreditation to supervise research from University of
Power Electronics, vol. 7, pp. 2695-2703, 2014.
Poitiers in 2012, all in Electrical Engineering. He is
[31] N. Sabeur, S. Mekhilef, and A. Masaoud, "A actually full Professor at Poitiers University and
Simplified Time-Domain Modulation Scheme-Based member of the Laboratory of Information Technology
Maximum Boost Control for Three-Phase Quasi-Z and Automatic control for the Systems (LIAS), Poitiers Graduate School of
Engineering (ENSIP). His current research interests are modeling and
Source Inverters," IEEE Journal of Emerging and
advanced control of power converters and power electronics systems and
Selected Topics in Power Electronics, vol. 6, pp. 760- their digital control techniques. The derived topics deal with power quality
769, 2017. such as active power filters, PWM rectifiers or renewable energy systems. He
[32] A. A. Abduallah, A. Iqbal, M. Meraj, L. Ben-Brahim, is a member of IEEE and EPE association.
R. Alammari, and H. Abu-Rub, "Discontinuous space
Mostefa Kermadi (M’20) received Engineering
vector pulse width modulation techniques for a five- (Dipl. Ing.) and Master degree in Control Engineering
phase quasi Z-source inverter," in IECON 2015-41st in 2012, and PhD in Automatic Control in 2018, all
Annual Conference of the IEEE Industrial Electronics from National Polytechnic School (ENP) of Algiers,
Algeria. During his PhD work, he was a visiting
Society, 2015, pp. 004205-004210.
researcher at the Centre of Electrical Energy Systems
[33] M. H. Bierhoff and F. W. Fuchs, "Semiconductor (CEES), Universiti Teknologi Malaysia (UTM),
losses in voltage source and current source IGBT Malaysia, from December 2016 to July 2018. He is
converters based on analytical derivation," in 2004 currently a Post-doctoral Research Fellow with the
Power Electronics and Renewable Energy Research Laboratory (PEARL),
IEEE 35th Annual Power Electronics Specialists
Department of Electrical Engineering, University of Malaya, Malaysia. His
Conference (IEEE Cat. No. 04CH37551), 2004, pp. research interests include modern control in power electronic converters,
2836-2842. power conversion and management in renewable energy systems.
[34] G. Narayanan, D. Zhao, H. K. Krishnamurthy, R.
Nassereddine Sabeur received the M.S. degree in
Ayyanar, and V. Ranganathan, "Space vector based
electrical engineering from the University of Setif,
hybrid PWM techniques for reduced current ripple," Sétif, Algeria, in 2010, and the Ph.D. degree from the
IEEE Transactions on Industrial Electronics, vol. 55, University of Malaya, Kuala Lumpur, Malaysia in
pp. 1614-1627, 2008. 2018. He has been a Research Assistant with the Power
Electronics and Renewable Energy Research
[35] Y. Liu, B. Ge, H. Abu-Rub, and F. Z. Peng, "Overview
Laboratory, University of Malaya. He is currently a
of space vector modulations for three-phase Z- Post-Doctoral Research Fellow at the University of
source/quasi-Z-source inverters," IEEE Transactions Malaya, His current research interests include power electronics, networks
on Power Electronics, vol. 29, pp. 2098-2108, 2013. communications, control of power converters, renewable energy, and Ad hoc
systems.
[36] B. Mirafzal, M. Saghaleini, and A. K. Kaviani, "An
SVPWM-based switching pattern for stand-alone and SAAD MEKHILEF (Senior Member, IEEE)
grid-connected three-phase single-stage boost received the B.Eng. degree in electrical engineering
inverters," IEEE Transactions on Power Electronics, from the University of Setif, Setif, Algeria in 1995,
and the master’s degree in engineering science and the
vol. 26, pp. 1102-1111, 2011.
Ph.D. degree in electrical engineering from the
University of Malaya, Kuala Lumpur, Malaysia, in
Chaib Ibtissam was born in Algeria in 1991. She 1998 and 2003, respectively. He is currently a
received Engineering (Dipl. Ing.) and Master degree in Professor and the Director of the Power Electronics
Control Engineering in 2015 from National Polytechnic and Renewable Energy Research Laboratory,
School (ENP) of Algiers, Algeria. She is actually a PhD Department of Electrical Engineering, University of
student in Automatic Control in the same school. Her Malaya. He is the Dean of the Faculty of Engineering, University of Malaya,
current research interests are control in power electronic and Distinguished Adjunct Professor with the Faculty of Science, Engineering
converters, power conversion and management in and Technology, School of Software and Electrical Engineering, Swinburne
renewable energy systems. University of Technology, VIC, Australia. He has authored or coauthored of
more than 400 publications in international journals and conference
proceedings. His current research interests include power converter topologies,
El Madjid Berkouk was born in Algeria in 1968. He control of power converters, renewable energy, and energy efficiency
received the Engineering degree in electrical
engineering from the Ecole Nationale Polytechnique
of Algiers, Algiers, Algeria, in 1991, the M.S. degree
in electrical engineering from the Ecole Nationale
Supérieure d’Electrotechnique, d’Electronique,
d’Informatique, d’Hydraulique et des
Télécommunications, Toulouse, France, in 1992, and
the Ph.D. degree in electrical engineering from the
Conservatoire National des Arts et Métiers, Paris, France, in 1995. From 1993
to 1996, he was teaching with the University of Paris XI, Paris, France. Since
1996, he has been a Professor with the Ecole Nationale Polytechnique of
Algiers. He has authored or coauthored more than 200 papers. His research
interests include power electronics, electrical drives, and renewable energy.
Prof. Berkouk is a member of the Algerian Academy of Science and
Technology. He has received several international awards.

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