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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2020.3002684, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 1
Manuscript received January 29, 2020; revised March 10, 2020; accepted J. P. Gaubert is with the Automatic Control and Industrial Data Processing
May 24, 2020. This work was supported by National Polytechnic School of Laboratory, University of Poitiers, France
Algiers (ENP), Algeria and University of Malaya, Malaysia, under Impact (e-mail: jean.paul.gaubert@univpoitiers.fr).
Oriented Interdisciplinary Research Grant (IIRG): IIRG011A-2019, and M. Kermadi (Corresponding Author), N. Sabeur and S. Mekhilef are with
Ministry of Higher Education, Malaysia under Large Research Grant Scheme the Power Electronics and Renewable Energy Research Laboratory (PEARL),
(LRGS): LR008-2019. Department of Electrical Engineering, University of Malaya, Kuala Lumpur
I. Chaib and E. M. Berkouk are with the Laboratory of Process Control 50603, Malaysia. (e-mails: mostefa@um.edu.my, nasser@um.edu.my,
(LCP), National Polytechnic School of Algiers (ENP), 16200, Algeria (e-mails: saad@um.edu.my).
ibtissam.chaib@g.enp.edu.dz, el_madjid.berkouk@g.enp.edu.dz).
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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 2
fact that the generation of the shoot-through can be occurred by The remainder of this paper is organized as follows: Section
the combination of the three legs, which increases the switching II presents a brief description of the Z-source inverter (ZSI). In
losses, although the shoot-through can be generated only by one Section III, ZSVPWM with of 4 and 6 shoot-through states
leg. To overcome the limitations of modified PWM, authors in distributions are reviewed. The proposed DZSVPWM is
[22] proposed a modified space vector PWM (SVPWM) for the described in Section IV. Comparative simulation with 4-
Z-source inverter, in which the shoot-through can be generated ZSVPWM and 6-ZSVPWM is made in Section V. Hardware
by using only one leg. As highlighted in [23], the SVPWM is results and discussions are presented in Section VI. The
easy to implement and has better performance than the modified conclusion is presented in Section VII.
PWM with reduced total harmonic distortion and lower current
ripple. The modified SVPWM for Z-source inverter II. THE Z-SOURCE INVERTER
(ZSVPWM) gives the possibility to find the best distribution of Fig. 1 shows the topology of the Z-source inverter. It
the shoot-through state between the vectors state to reduce the consists of an impedance network: inductors L1 and L2 and
switching losses by using only one switch in each transition. capacitors C1 and C2 connected in X shape linked with a dc
Hence, many ZSVPWMs have been developed to control the source. The impedance network is feeding a three-phase
duty ratio of the shoot-through [24-26]. In recent literature, inverter. The latter supply a resistive load through an LC filter.
ZSVPWM techniques with four shoot-through vectors The Z-source inverter has two main operating modes, shown in
distribution (4-ZSVPWM) and 6 shoot-through distribution (6- Fig. 2. Fig. 2(a) shows the equivalent circuit during the shoot-
ZSVPWM) were presented in [27, 28], and in [29], through state where the upper and the lower switches of any
respectively. Both 4-ZSVPWM and 6-ZSVPWM have 12 legs are turns on. Q represents the equivalent switch during the
switching transitions. The advantage of the 6-ZSVPWM is that shoot-through state. Fig. 2(b) shows the equivalent circuit
it uses only one leg to generate the shoot-through in each during the non-shoot-through state where the inverter bridge
switching cycle while the 4-ZSVPWM uses two legs separately works as a traditional inverter [1].
to generate the shoot-through state for each switching cycle. As verified in detail in [1], the basic principle relationship for
Despite having high performance, ZSVPWMs suffer from ZSI is:
minimal power transfer due to the utilization of zero voltage 1−d T
Vc1 = Vc2 = Vc = V , d = sht (1)
vectors (000) and (111) in all sectors. In addition, ZSVPWM 1−2d dc T
suffers from high THD since all the switches have at least two Where
1
transitions in each switches cycle [30]. To enhance the V = 𝑉 = BVdc non shoot − through state
switching losses, researches proposed the discontinuous Space { i 1−2d 𝑑𝑐 (2)
Vi = 0 shoot − through state
Vector pulse width modulation D-ZSVPWM for the Z-source
inverter in [30-32]. Despite the efficiency of the D-ZSVPWM 1
in terms of reducing the switching losses and maximizing the 𝐵= (3)
1−2𝑑
power transfer, the conduction losses are appeared to be a
challenging problem. This is due to holding on the switches in where 𝑉𝑐1 and 𝑉𝑐2 are capacitors voltage of impedance network
full conduction throughout the 60° interval [33]. which are the same due to circuit symmetry. B is the boost
To overcome the above-mentioned limitations, this work factor of ZSI. 𝑉𝑑𝑐 and 𝑉𝑖 denote the input and output voltages
proposes an improved discontinuous space vector pulse width of impedance network respectively. d is the shoot-through duty
modulation (ID-ZSVPWM) to control the Z-source inverter. To 𝑇
ratio d = 𝑠ℎ𝑡⁄𝑇 ; 𝑇𝑠ℎ𝑡 is the total shoot-through time interval; 𝑇
reduce the conduction losses and maintain low switching losses,
each sector 60° is split by two, thus dividing the alpha-beta is the control cycle.
plane by 12 sectors of 30°. By doing so, the switches stay in full VL
D
conduction only for 30° instead of 60°. In the proposed ID- iL
L1
ZSVPWM, the shoot-through states are introduced without C1 C2
s1 s2 s3
Lf RL
compromising the active states or affecting the invariable a
Vc Vi b
switches in each switching cycle. The proposed ID-ZSVPWM Vdc
c
N
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of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 3
S2
(a)
S3
S1
S4
S2
S3 S5
S4
S5 S6
S6
T1/2 T2/2 T2/2 T1/2
(T0-Tsh)/4 (T0-Tsh)/4 (T0-Tsh)/4 (T0-Tsh)/4
T0/4 T1/2 T2/2 T0/4 T0/4 T2/2 T1/2 T0/4 Ts/2 Ts/2
𝑇𝑠 𝑇𝑠 S4
where 𝑖 ∈ {1,2, … ,6} denotes the 𝑖𝑡ℎ sector; T0 is the time S5
interval of the zero vector U0 ; T1 and T2 are the time intervals
of active vectors U1 and U2 , respectively. θ is the inclined
S6
angle of the voltage reference vector Uref , Vi is the dc-bus T1/2 T2/2 T2/2 T1/2
voltage. r is given as follows: T0/4 -Tsh/6 T0/4 -Tsh/6 T0/4 -Tsh/6 T0/4 -Tsh/6
𝑟 = √3 (6)
𝑉𝑖 Fig. 5. Switching sequence for 6-ZSVPWM in sector 1.
Since 𝑇0 -𝑑𝑇𝑠 ≥ 0, the following condition can be always
guaranteed: IV. PROPOSED ID-ZSVPWM
𝑇0 (7) The proposed ID-ZSVPWM aims to reduce the total harmonic
𝑑≤
𝑇𝑠 distortion of the output signal by and compromise between the
conduction losses reduction and the reduction of switching
The modulation index m is given by losses. This objective is achieved by the elimination of one
Uref switching transition in each half sector for 30° with a proper
𝑚= (8)
Vi ⁄2 selection of the shoot-through state distribution. In this strategy,
dmax denotes the maximum of the duty cycle, it can be calculated each sector is divided into two sub-sectors. Hence the number
using the following equation: of sectors becomes 12 sectors of 30° for each one as shown in
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of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 4
Fig. 6. Each subsector has only one zero vector either 𝑉0 (000)
or 𝑉1 (111) at the beginning or the end of each switching
S1
sequence. Table 1 list the switching sequence of the proposed
ID-ZSVPWM and the switching sequence of the conventional S2
Z-source SVPWM. S3
TABLE 1 S4
SWITCHING SEQUENCE IN SIX SECTORS S5
Sector Conventional sequence ID-ZSVPWM sequence
S6
(𝑉0 𝑉1 𝑉2 𝑉1,𝑉1 𝑉2 𝑉1 𝑉0)
(𝑉0 𝑉1 𝑉2 𝑉7,𝑉7 𝑉2 𝑉1 𝑉0) V0 V1 V2 V1 V1 V2 V1 V0
Vth Vth Vth Vth
I
(𝑉7 𝑉2 𝑉1 𝑉2,𝑉2 𝑉1 𝑉2 𝑉7) T1/4 T2/2 T1/4 T1/4 T2/2 T1/4
(𝑉7 𝑉2 𝑉3 𝑉2 ,𝑉2 𝑉3 𝑉2 𝑉7 ) T0/2-Tsh/4 T0/2-Tsh/4
II (𝑉0 𝑉3 𝑉2 𝑉7 ,𝑉7 𝑉2 𝑉3 𝑉0 )
(𝑉0 𝑉3 𝑉2 𝑉3 ,𝑉3 𝑉2 𝑉3 𝑉0 ) Ts/2 Ts/2
(0323,3230) (7232,2327) S6
V7 Vth V2 Vth V1 V2 V2 V1 Vth V2 Vth V7
III Uref
(b)
(7434,4347) T2
(0121,1210) Fig. 7. Switching sequence for ID-ZSVPWM in sector1 (a) when 𝜃 < 30° (b)
V0(000) when 𝜃 > 30°.
V7(111) 30°
V4(011) V1(100)
T1 α-axis V. RESULTS & DISCUSSION
IV
(7454,4547)
VI (0161,1610) To evaluate the performance of the proposed ID-ZSVPWM
V strategy, simulation using Matlab/SIMULINK software and
experiment are carried out. As shown in Fig.8, the system
(0545,5450) (7616,6167) consists of a Z-source inverter linked with a dc source, feeding
(0565,5650) (7656,6567)
a three-phase resistive load through an LC filter. The main
parameters of the described system are listed in Table 3. This
V5(001) V6(101) simulation aims to compare the proposed strategy with 4-
ZSVPWM and 6-ZSVPWM, in term of the dc-bus voltage
boosting, and the current and voltage THD reduction. The
Fig. 6. voltage space vectors for the ID-ZSVPWM strategy.
obtained simulation results are listed in Table.4.
The simulation results in continuous time mode for the 4-
Unlike in the conventional Z-source SVPWM the shoot-
ZSVPWM, 6-ZSVPWM, and ID-ZSVPWM, are plotted in Fig.
through state is distributed properly in the proposed ID-
9, Fig. 10 and Fig. 11 respectively, where the inverter dc-bus
ZSVPWM, without changing the state of the maintained
switches in each switching cycle. Table 2 lists the switching Vi , the Z-source capacitor voltage Vc , and the input DC-source
sequence and the distribution of the shoot-through state in each voltage Vdc are plotted in figure part (a), the inductance current
subsector for a half switching cycle. Four shoot-through states IL is shown in figure part (b), and the current and voltage output
are inserted in each switching cycle without affecting the active FFT analysis are shown in figure parts (c) and (d) respectively.
states with a duration of 𝑇𝑠ℎ ⁄4 without affecting the active For Vdc=10 V, d=0.3 and a modulation index m=0.8, the
states. The proposed switching sequence for the ID-ZSVPWM boost factor for 4-ZSVPWM is equal to 𝐵4−ZSVPWM = 1.9 and
for the first sub-sector is shown in Fig. 7(a) and Fig. 7(b) the 𝑇𝐻𝐷4−ZSVPWM = 0.74% as shown in Fig. 9.
respectively. as shown in Fig. 7, in the first sub-sectors S3 is Although, for the 6-ZSVPWM strategy, the boost factor is
maintained off and S6 is maintained on. In the second sub-
increased to 𝐵6−ZSVPWM = 2.54, and the THD is reduced
sector, S1 is maintained on and S4 is maintained off. And this
procedure repeats in each sub-sector (30°) for different legs. 𝑇𝐻𝐷6−ZSVPWM = 0.7% as shown in Fig.10, the proposed
This procedure ensures the reduction of conduction losses and strategy shows better results. where the boost factor is increased
maintain lower switching losses. to 𝐵ID−ZSVPWM = 2.6, with an improved 𝑇𝐻𝐷ID−ZSVPWM =
0.17% as shown in Fig.11 The current output THD and the
voltage output THD show the same patterns due to the resistive
load.
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of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 5
TABLE 2
THE DISTRIBUTION OF THE SHOOT-THROUGH STATES BETWEEN THE SWITCHING SEQUENCES FOR THE ID-ZSVPWM
Sector subsector switches 𝐓𝟎 𝐓𝐭𝐡 𝐓𝟏 𝐓𝐭𝐡 𝐓𝟐 𝐓𝟏
Sector I (𝑉0 𝑉1 𝑉2 𝑉1,𝑉1 𝑉2 𝑉1 𝑉0) (S1 S2 S3 ) 000 100 100 110 110 100
(S4 S5 S6 ) 111 111 011 011 001 011
(𝑉7 𝑉2 𝑉1 𝑉2,𝑉2 𝑉1 𝑉2 𝑉7) (S1 S2 S3 ) 111 111 110 110 100 110
(S4 S5 S6 ) 000 001 001 011 011 001
Sector II (𝑉7 𝑉2 𝑉3 𝑉2 ,𝑉2 𝑉3 𝑉2 𝑉7 ) (S1 S2 S3 ) 111 111 110 110 010 110
(S4 S5 S6 ) 000 001 001 101 101 001
(𝑉0 𝑉3 𝑉2 𝑉3 ,𝑉3 𝑉2 𝑉3 𝑉0 ) (S1 S2 S3 ) 000 010 010 110 110 010
(S4 S5 S6 ) 111 111 101 101 001 101
Sector III (𝑉0 𝑉3 𝑉4 𝑉3,𝑉3 𝑉4 𝑉3 𝑉0 ) (S1 S2 S3 ) 000 010 010 011 011 010
(S4 S5 S6 ) 111 111 101 101 100 101
(𝑉7 𝑉4 𝑉3 𝑉4,𝑉4 𝑉3 𝑉4 𝑉7) (S1 S2 S3 ) 111 111 011 011 010 011
(S4 S5 S6 ) 000 100 100 101 101 100
Sector IV (𝑉7 𝑉4 𝑉5 𝑉4,𝑉4 𝑉5 𝑉4 𝑉7) (S1 S2 S3 ) 111 111 011 011 001 011
(S4 S5 S6 ) 000 100 100 110 110 100
(𝑉0 𝑉5 𝑉4 𝑉5,𝑉5 𝑉4 𝑉5 𝑉0 ) (S1 S2 S3 ) 000 001 001 011 011 001
(S4 S5 S6 ) 111 111 110 110 100 110
Sector V (𝑉0 𝑉5 𝑉6 𝑉5 ,𝑉5 𝑉6 𝑉5 𝑉0 ) (S1 S2 S3 ) 000 001 001 101 101 001
(S4 S5 S6 ) 111 111 110 110 010 110
(𝑉7 𝑉6 𝑉5 𝑉6 ,𝑉6 𝑉5 𝑉6 𝑉7 ) (S1 S2 S3 ) 111 111 101 101 001 101
(S4 S5 S6 ) 000 010 010 110 110 010
Sector VI (𝑉7 𝑉6 𝑉1 𝑉6,𝑉6 𝑉1 𝑉6 𝑉7) (S1 S2 S3 ) 111 111 101 101 100 101
(S4 S5 S6 ) 000 010 010 011 011 010
(𝑉0 𝑉1 𝑉6 𝑉1,𝑉1 𝑉6 𝑉1 𝑉0) (S1 S2 S3 ) 000 100 100 101 101 100
(S4 S5 S6 ) 111 111 011 011 010 011
The proposed ID-ZSVPWM has the highest boost factor MicroLabBOX controls the switches through an IGBT Driver
𝐵ID−ZSVPWM = 2.6, the lowest total harmonic distortion, and an SKHI 23/12 (R) with a switching frequency equals to 𝑓𝑠𝑤 =2.5
acceptable inductance current ripple ∆𝐼𝐿𝑍 = 0.325A. Thus, the kHz and a sampling time equal to 𝑓𝑠 =25 kHz.
proposed ID-ZSVPWM outperforms the other methods in terms The obtained experimental results are listed in Table. 5 for a
of 1) enhancing the signal quality of the ac output voltage modulation index m=0.8 and a duty cycle equal to d=0.3, as
waveform (reduced THD), 2) ensuring the highest boost factor
of the dc-link voltage, and 3) maintaining a good current ripple shown in Fig. 13. The measurement of the dc-Bus ( 𝑉𝑑𝑐 (𝑣),
in the inductance. 𝑉𝑐 (𝑣), 𝑉𝑖 (𝑣); 𝐼𝐿 (𝐴)) are presented in Fig.13 (a) and Fig.13 (b).
D iL
VL
Electrical Diagram In addition, the zoomed waveform of 𝑉𝑑𝑐 , 𝑉𝑖 , 𝑉𝑐 , and the
inductor current 𝐼𝐿 within five (5) control cycles (2e-3 s) are
L1
s1 s2 s3
C1 C2 Lf RL
Vdc Vc Vi a iLoad plotted in Fig. 13 (c). It can be seen from Fig. 13(a) and Fig.
b N
c 13(b) that the ID-ZSVPWM present a small current inductor
ripple value ∆𝐼𝐿ID−ZSVPWM = 0.47A. Beside the voltage 𝑉𝑖 (𝑣)
s4 s5 s6 Cf
L2
Vref
Va
Vα Im
Uref
T1 equals to 16.5V, the voltage 𝑉𝑐 (𝑣) equals 13.9V, resulting in a
αβ V3(010) V2(110)
T2
Vb V4(011) V1(100)
Switching
Switching pulses
boost factor equals to 1.65. The digital controller successfully
Vβ Re
times T0
Vc abc V5(001) V6(101)
θ calculator Tsh
for each phase generates the appropriate switching gate signals to achieve the
Control Diagram
desired output waveform. From the waveforms of Fig. 13(c), it
Fig. 8. Complete block diagram of Z-source system.
can be seen that the switching sequence presented in Fig. 7 is
successfully generated using the ID-ZSVPWM. The
TABLE 3 distribution of the ST into four periods per control cycle appears
SIMULATION PARAMETERS in the experimental waveforms, and 𝑉𝑖 becomes zero and 𝐼𝐿
𝑉𝑑𝑐 m d 𝐿𝑧 𝐶𝑧 𝑓𝑠𝑤 𝑓𝑠 𝐿𝑓 𝐶𝑓 RL increases during ST periods. The measurement of the AC-Bus
2.5 25
10 V 0.8 0.3 5mH 3.3mF
kHz kHz
20mH 110μF 20.7Ω (the current load 𝐼𝑙𝑜𝑎𝑑 (𝐴), the line to line voltage 𝑉𝑎𝑏 (𝑣), the
phase voltage 𝑉𝑎𝑛 (𝑣), resistive load voltage 𝑉𝑅𝑒𝑠 (𝑣)) are
To validate the proposed strategy experimentally, a prototype presented in Fig. 13(d), where the voltage across the resistor is
of Z-source inverter feeding a three-phase resistive load ̂ 𝑅𝑒𝑠 = 10 𝑉 , the phase voltage is 𝑉𝑎𝑛 (𝑣) = 12.8 𝑉. Hence,
𝑉
through an LC filter was built as shown in Fig. 12. The
the inverter factor is G=1.28 which is nearly equal to the
operation parameters used in the simulation and listed in Table
theoretic value. The simulation and experimental results are
3 are used for the experiment. A Chroma 62150H-600S/1000S
Solar Array Simulator was used as a dc power supply. The similar, which validate the performance of the proposed control
proposed ID-ZSVPWM strategy is implemented through a scheme.
dSPACE MicroLabBOX controller. The dSPACE
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(a) (b)
(c) (d)
Fig. 9. 4-ZSVPWM Simulation results (a) 𝑉𝑑𝑐 (𝑣), 𝑉𝑐 (𝑣), 𝑉𝑖 (𝑣) voltages; (b) inductance current 𝐼𝐿 (𝐴); (c) current FFT analysis; (d) voltage FFT
𝑽 (𝒗) 𝑽𝒄 (𝒗) analysis.
𝒊
𝑽𝒅𝒄 (𝒗)
(a) (b)
(c) (d)
Fig. 10. 6-ZSVPWM Simulation results (a) 𝑉𝑑𝑐 (𝑣), 𝑉𝑐 (𝑣), 𝑉𝑖 (𝑣) voltages; (b) inductance current 𝐼𝐿 (𝐴);(c) current FFT analysis; (d) voltage FFT
analysis.
(a) (b)
(c) (d)
Fig. 11. ID-ZSVPWM Simulation results (a) 𝑉𝑑𝑐 (𝑣), 𝑉𝑐 (𝑣), 𝑉𝑖 (𝑣) voltages; (b) inductance current 𝐼𝐿 (𝐴);
(c) current FFT anlysis; (d) voltage FFT anlysis.
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1500
150
1000
100
500
50
0
0
5 10
20 30 50 100
0,7 0,8 0,9 1,1 Frequency (kHz)
Modulation index
(c)
(a) Fig. 15. Power loss in the main bridge inverter versus the switching frequency
4-ZSVPWM 6-ZSVPWM ID-ZSVPWM (a): switching losses, (b): conduction losses, and (c): total power losses.
60
Conduction Losses
40 VI. CONCLUSION
In this investigation, the aim is to assess a new proposed
20 strategy, for the three-phase Z-source inverter named ID-
ZSVPWM. The most challenging problem in the control
0 strategy for the Z-source inverter is to provide a good signal
0,7 0,8 0,9 1,1
Modulation index quality with reduced power losses. The proposed ID-ZSVPWM
(b) reduces the conduction losses and maintains lower switching
4-ZSVPWM 6-ZSVPWM ID-ZSVPWM losses by 1) the division of each sector to two subsectors of 30°,
400
2) maintaining two switches of one leg (one is on while the
other is off) in the steady-state of each subsector, and 3) with
Power Losses
300
wise distribution of four (4) shoot-through state in the switching
200
period. The ID-ZSVPWM has been compared with the 4-
100 ZSVPWM and 6-ZSVPWM strategies, it has been shown from
MATLAB simulation, PLECS measurements and experimental
0
results that the proposed ID-ZSVPWM strategy has lower
0,8 0,9 0,7 1,1
Modulation index conduction losses, lower switching losses for the high
(c) modulation index, and has a lower current/voltage THD, lower
Fig. 14. Power losses in the main bridge versus the modulation index current ripple in the inductors, and higher boost factor.
(a): switching losses, (b): conduction losses, and (c): total power losses.
ACKNOWLEDGMENT
The authors would like to thank National Polytechnic School
of Algiers (ENP), Algeria and University of Malaya, Malaysia,
4-ZSVPWM 6-ZSVPWM ID-ZSVPWM for providing financial support under Impact Oriented
100
Conduction Losses (w)
80
Interdisciplinary Research Grant (IIRG): IIRG011A-2019, and
Ministry of Higher Education, Malaysia under Large Research
60
Grant Scheme (LRGS): LR008-2019.
40
20
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of Emerging and Selected Topics in Power Electronics
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