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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
A Design Procedure for High-Efficiency and
Compact-Size 5–10-W MMIC Power Amplifiers in
GaAs pHEMT Technology
Gholamreza Nikandish, Student Member, IEEE, and Ali Medi, Senior Member, IEEE
Abstract—This paper presents the design procedure of mono-
lithic microwave integrated circuit (MMIC) high-power amplifiers
(HPAs) as well as implementation of high-efficiency and compact-
size HPAs in a 0.25- m AlGaAs–InGaAs pHEMT technology. Pre-
sented design techniques used to extend bandwidth, improve effi-
ciency, and reduce chip area of the HPAs are described in detail.
The first HPA delivers 5 W of output power with 40% power-added
efficiency (PAE) in the frequency band of 8.5–12.5 GHz, while pro-
viding 20 dB of small-signal gain. The second HPA delivers 8 W of
output power with 35% PAE in the frequency band of 7.5–12 GHz,
while maintaining a small-signal gain of 17.5 dB. The 8-W HPA
chip area is 8.8 mm , which leads to the maximum power/area ratio
of 1.14 W/mm . These are the lowest area and highest power/area
ratio reported in GaAs HPAs operating within the same frequency
band.
Index Terms—GaAs pHEMT, high-power amplifier (HPA),
monolithic microwave integrated circuit (MMIC) power amplifier,
stability.
I. INTRODUCTION
H IGH-POWER amplifiers (HPAs) find widespread appli-
cations in communication systems, such as base stations
of wireless communications, satellite downlinks, and transmit-
receive (T/R) modules of phased array radars. Monolithic mi-
crowave integrated circuit (MMIC) HPAs offers compact size,
high operation frequency, high reliability, and less chip-to-chip
variations compared with their hybrid counterparts. Given these
advantages, MMIC HPAs are gradually replacing hybrid and
vacuum tube HPAs in various applications.
The HPA output power, efficiency, bandwidth, and chip area
are the most important parameters. Several MMIC HPAs in
GaAs pHEMT and heterojunction bipolar transistor (HBT)
technologies have been reported in the -band frequency
range [1]–[14]. Typical performances are 5–10 W output power
and 40% power-added efficiency (PAE). Higher PAE values
are also reported, e.g., [3], [9], [11], and [12], but most results
have been achieved in a narrow frequency band. The chip area
is another important aspect of HPAs that directly affects the
fabrication and production costs and yield. The lowest chip
area values reported for -band GaAs HPAs are 9 mm for an
Manuscript received February 20, 2013; revised June 20, 2013; accepted June
24, 2013.
The authors are with the Department of Electrical Engineering, Sharif Univer-
sity of Technology, Tehran 11155-9517, Iran (e-mail: nikandish@ee.sharif.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2013.2271997
0018-9480/$31.00 © 2013 IEEE
1
8.7-W HBT HPA in [13] and 11 mm for a 10-W pHMET HPA
in [2]. Moreover, the highest reported values for the output
power per chip area are 0.97 W/mm in the pulse mode [2], [13]
and 0.74 W/mm in the CW mode [3]. However, these designs
have narrow bandwidths, e.g. 2 GHz in [2] and less than 1 GHz
in [3] and [13]. Thus, achieving high PAE or high output power
per chip area in a wide bandwidth still has remained as a design
challenge.
In this paper, the design procedure of MMIC HPAs is pre-
sented in detail and two high performance HPAs are designed
in a 0.25- m AlGaAs–InGaAs pHEMT technology. Section II
describes features of the technology used for implementation
of the HPAs. In Section III, the design procedure of the HPAs
is described in detail. The design of output and input stages
of HPA, thermal simulations to ensure HPA reliability, the de-
sign of impedance-matching networks, and large-signal stability
simulations of HPA are given in this section. The measurement
results of the two HPAs are presented in Section IV.
II. TECHNOLOGY
GaAs HEMT and HBT technologies are conventionally em-
ployed for implementation of HPAs, while GaN HEMT tech-
nology has recently entered this realm as a promising alterna-
tive for achieving higher levels of output power and efficiency.
Several considerations affect the choice of suitable process for
implementation of a specific HPA design. GaN process provides
much higher output power compared to the GaAs process. This
is enabled by higher breakdown voltage of transistors, which al-
lows the use of higher supply voltages. This higher output power
density leads to greatly reduced chip area. In spite of these ad-
vantages, fabrication cost of GaN process is excessively higher
than that of GaAs process. GaAs HBT technologies can provide
higher power densities compared to their HEMT counterparts,
but thermal problems in high-power density devices can reduce
reliability of HPA [1]. GaAs pHEMT is the most common tech-
nology used in the design of HPAs and provides a good com-
promise between output power, reliability, and fabrication cost
[6].
In this work, an AlGaAs-InGaAs pHEMT technology with
0.25- m gate length on a 100- m-thick substrate is adopted
for implementation of HPAs. The cutoff frequency of the
process is around 60 GHz. The drain-gate breakdown voltage
is 18 V. The maximum output power of an 8 150- m device
biased at 0.8 V and 8 V (110-mA/mm cur-
rent density and 340-mS/mm peak transconductance) is 29 dBm
at 10 GHz. The associated gain and PAE are 9 dB and 38%,
respectively. The process offers two metal layers with 1- and
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2 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 1. Architecture of a two-stage HPA.
4- m thickness, air bridges, and ground back-vias. Moreover,
metal–insulator–metal (MIM) SiN capacitors with 650-pF/mm
density, thin film, and mesa resistors with 50- and 140- sq
sheet resistances are available in the process.
III. HPA DESIGN
A. Determination of the Number of Stages
In the first step of HPA design, the number of required
amplifier stages should be determined. This conventionally
is chosen based on overall power gain of HPA. For example,
an 8 150- m transistor biased under the conditions given
in Section II provides 9-dB large-signal power gain near
saturation. If HPA includes two stages, overall power gain
would be around 18 dB. It should be noted that losses of the
impedance-matching networks at the input and output of HPA
as well as between the two stages reduce the power gain. Also,
it is possible to improve the power gain by adopting smaller
width transistors, which have lower gate loss in the input stage.
More amplifier stages can be used to achieve higher overall
power gain. However, as will be discussed in Section III-E,
HPA bandwidth and chip area can be compromised due to
required additional impedance matching networks.
In the current design, a large-signal power gain of approxi-
mately 12 dB is considered sufficient for HPA. Further power
gain is provided by a driver amplifier preceding the HPA. As
the power gain provided by two stages is sufficient here, both
HPAs include two stages, an output stage providing the target
output power while an input stage driving the output stage de-
vices. Architecture of the HPAs is depicted in Fig. 1. It includes
three impedance-matching networks, namely input-matching
network (IMN), inter-stage-matching network (ISMN), and
output-matching network (OMN). These networks also serve as
a power combiner or divider as well as biasing networks. The
output and input stages employ multiple transistors to boost the
output power of HPA. Details of HPA design are described in
the following subsections.
B. Output Stage Design
For design of the output stage, the bias condition, size, and the
number of output stage transistors should be determined based
on required total output power. The optimum load and source
impedances of these transistors are determined by iterative load
pull and source pull simulations to achieve maximum output
power or efficiency. This is discussed in detail in Section III-E.
The maximum drain voltage allowed by the process for reliable
operation, 8 V, is used to minimize bias current required for a
given output power. Transistors exhibit peak transconductance
of 340 mS/mm at 0.8 V and 8 V. Simulations
indicate that output power of transistors is almost insensitive to
the gate bias voltage around this operating point. Thus, transis-
tors are biased at these voltages to maximize their output power
as well as power gain.
The output power of multiple transistors must be combined
to achieve the target output power. For the HPA architecture
shown in Fig. 1, the output power is given by
(1)
where and denote the number of transistors in the output
stage and the saturated output power of each transistor, respec-
tively. is loss of the OMN, which should be minimized as it
directly degrades the output power. The exact value of can
be determined only after complete design of the OMN. Based on
the values reported in literature, a typical value of 0.5–1 dB can
be used as a prediction in primary calculations. Using a larger
width transistor (higher ) helps to obtain the target output
power with less number of devices. Conventionally, the width
of the HPA chip is determined by the number of devices used in
the output stage. Thus, the chip area can be saved by using larger
width devices. For example, two devices with 4 150- m and
8 75- m width have same total widths and provide roughly
the same output power. But, in process used in the current de-
sign, the layout of the first device has 155- m width while that
of the latter is 270 m. The maximum possible width of tran-
sistors in a process can be limited either by the lack of accu-
rate large-signal models or by fabrication limitation due to de-
graded reliability. In the current design, the process design kit
(PDK) offers measured load pull data for transistor widths up
to 8 150 m with 29-dBm output power. However, the max-
imum transistor width allowed by design rules of the process is
8 290 m, which lacks the measured load pull data. Using a
scalable model for equivalent circuit components of this device,
its maximum output power is extrapolated to be around 31 dBm.
In this paper, two HPAs are designed based on the above two
choices for selection of width of the output stage transistors.
The first HPA is targeted for 5-W output power. Using (1) with
29 dBm (0.79 W) and 1 dB (1.25), the number
of transistors is determined as
(2)
Therefore, eight transistors are used in the output stage. The
second HPA is designed for 8-W output power. Using (1) with
31 dBm (1.25 W) and 1 dB (1.25), the number
of transistors in the output stage is derived as . In fact, a
conservative value of 1 dB was assumed in the above
calculations to ensure that target output power can be achieved.
Another design concern of HPAs is the transistor instability.
The common-source structure that is commonly used in HPAs is
potentially unstable in low frequencies due to its high gain. The
stability -factor for an 8 150- m device, shown in Fig. 2(a),
indicates that the device is potentially unstable in frequencies
below 12.5 GHz. There are several compensation methods to
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NIKANDISH AND MEDI: DESIGN PROCEDURE FOR HIGH-EFFICIENCY AND COMPACT-SIZE MMIC PAs IN GaAs pHEMT TECHNOLOGY
Fig. 2. (a) Stabilization network, (b) stability factor, and (c) input–output large-
signal characteristic (at 10 GHz) of an 8 150- m transistor.
improve the amplifier stability [15]. To improve the device sta-
bility, a parallel RC network is inserted in series with the gate
of transistors [Fig. 2(a)]. Since the compensation network is
inserted in the input of the device, it has an insignificant ef-
fect on the device maximum output power. The series resis-
tance reduces the small-signal gain in low frequencies to im-
prove the stability. Its value is selected to achieve a -factor
greater than unity at frequencies above 1 GHz . stage transistors. Since the width of transistors is set based on
The paralleled capacitance is aimed to decrease the equivalent
impedance of the compensation network in higher frequencies,
thereby avoiding unnecessary degradation of the small-signal
gain in the high frequencies where the device is inherently stable
2 pF . The compensated device is unconditionally stable
in frequencies above 1 GHz [Fig. 2(b)]. The potential instability
below 1 GHz is not a major concern in this design, as the op-
eration frequency of HPA is much higher than 1 GHz, thus the
impedance matching circuits highly suppress the amplifier gain
below 1 GHz. As shown in Fig. 2(c), the stability factor is im-
proved in the expense of 2 dB degradation of the small-signal
gain. However, the maximum output power of the device re-
mains intact. A similar parallel RC network (with , D. Thermal Simulations
2.9 pF) is used to improve the stability of the 8 290- m
device which is used in the second HPA design.
3
C. Design of Input Stage
The input stage transistors should provide the power required
for driving the output stage transistors. For the HPA architecture
in Fig. 1, it can be shown that
(3)
where and are the number of transistors in the input
stage and the output power of each transistor, respectively,
is the loss of the ISMN, and denotes power gain of the
output stage transistors in saturation. As will be discussed in
Section III-E, ISMN is the most complicated part of the HPA
that commonly incurs substantial loss, especially in wideband
designs. The value of is typically in the range of 2–4 dB.
For 5-W HPA, using (3) with , 29 dBm (0.79
W), 9 dB (7.94), and 3 dB (2), the total output
power of the input stage is derived as
(4)
Therefore, the input stage can be designed to include four
transistors each with 0.4-W output power ( ,
0.4W) or two transistors each with 0.8-W output power (
, 0.8 W). In the first option, the width of transistors
is smaller and power gain of the input stage is slightly higher.
However, the output impedance of the input stage transistors is
also higher, thus, the bandwidth of the circuit is reduced. In this
design, the second option is chosen to achieve wider bandwidth.
Thus, the width of input stage transistors becomes the same as
that of the output stage devices. The same argument applies to
the 8-W HPA, where the input stage includes two transistors
with the same width as the output stage devices.
The input power required for drive of HPA, using Fig. 1, is
derived as
(5)
where is the loss of IMN and is the power gain of
the input stage transistors. The power gain of the input stage
transistors can have considerable effect on the gain compres-
sion point of the HPA. It should be selected to avoid saturation
of the input stage transistors before the output stage devices.
can be controlled by width and bias condition of the input
their output power , can be controlled by the gate bias
voltage. In current HPA designs, the above conditions are sat-
isfied by biasing the input stage transistors at 0.8 V
and 8 V, which maximize their transconductance. It
should be noted that the optimum load and source impedances
of the input stage transistors can be determined by load pull
and source pull simulations to maximize power gain rather than
output power or efficiency. Thus, input stage transistors can pro-
vide higher power gain compared to output stage devices. Using
(5) with 12 dB and assuming 1 dB, the required
input power is derived as 21 dBm.
The reliability of transistors in HPA is highly dependent
on the device channel temperature. The maximum channel
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4 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 3. Thermal simulation result for an 8 150- m device in the 5-W HPA.
temperature for reliable operation of transistors is typically
around 150 C [14]. Thermal simulations performed in CST
Microwave Studio environment1 are used to estimate the
channel temperature. Thermal properties of the substrate,
comprising layers of transistors, and backside epoxy are im-
ported into the thermal simulator. The backside temperature is
considered as 70 C. A CW heat source, the power of which is
determined based on the device dissipated power and number
of fingers, is applied to each gate finger of transistors. The
power of each heat source can be estimated as
(6)
where is supply voltage, is bias current of the tran-
sistor, and is the number of fingers. In 5-W HPA,
8 V, mA, and , thus heat sources with
0.13-W power are used in this simulation. Thermal
simulation results for an output stage transistor in the 5-W HPA
are shown in Fig. 3. Thermal simulations for complete output
stage structure indicate that the maximum channel temperature
is 100 C, which is well below the maximum tolerable tempera-
ture. In the 8-W HPA, using heat sources with 0.25-W
power, the maximum channel temperature is derived as 110 C,
which is slightly higher than that of the 5-W HPA. Although the
dissipated power is twice in the 8 290- m devices, the larger
size of back-vias helps to lower the channel temperature. There-
fore, it is expected that the two HPAs have similar reliability.
1[Online]. Available: www.cst.com
E. Design of Matching Networks
As shown in Fig. 1, the HPAs include three impedance-
matching networks. In the following, the design issues of each
matching network are addressed in detail. Also, a harmonic
termination technique is introduced that can be used to improve
PAE of HPA.
1) Output-Matching Network (OMN): The OMN should
transform the 50- load impedance to the optimum load
impedance of each output stage transistor, while performing
the task of combining output powers of transistors. The output
stage transistors should be terminated in their optimum load
and source impedances to provide the maximum output power
and PAE. These optimum impedances are determined using
load-pull and source-pull simulations. In wideband design,
the optimum load impedance of the output stage transistors
should be determined based on tradeoffs among output power,
PAE, and bandwidth. This impedance is not necessarily corre-
sponding to the maximum output power or maximum PAE. To
broaden the bandwidth, the load impedance should be located
inside the low- circles within the Smith chart. In the 5-W
HPA, the optimum load impedance is selected inside
circle [Fig. 4(a)]. The optimum source impedance is also deter-
mined in a similar manner using source-pull simulations. The
input impedance of transistors is capacitive with a small resis-
tive part due to feedback effect of the gate–drain capacitance.
Thus, the optimum source impedance is located inside higher
circles. For design of a broadband impedance-matching
network, the optimum load and source impedances are de-
termined at several frequencies in the band of interest. These
impedances for an 8 150- m transistor with 20-dBm input
power are shown in Table I. A lumped-element network is
synthesized using Agilent ADS impedance-matching tool2 (or
other circuit synthesis tool). Then, inductors are replaced by
microstrip lines, and the circuit is optimized to provide desired
impedance-matching characteristics. If the circuit cannot pro-
vide required bandwidth, the above process should be repeated
with the load and source impedances chosen in lower circles.
In the 8-W HPA, a different approach is adopted that results
in a compact layout for OMN. Two transistors are connected
using short-length lines. Then, load-pull simulations are per-
formed on this composite device to determine its optimum load
impedance [Fig. 4(b)]. Although there is the possibility that each
transistor is not terminated by its optimum load and source im-
pedances, this design method helps to considerably reduce the
area of the OMN. It is also possible to combine more devices.
A limitation of this method is that each device may not be ter-
minated by its optimum load and source impedances. Thus, the
output power and efficiency of the HPA are degraded. More-
over, by combining more devices, large parasitic capacitances
are formed at the input and output of the composite device. The
impedance-matching networks may need more elements to pro-
vide impedance matching in the expected frequency band. This
can even increase the chip area.
There are several power-combiner structures that can be used
for combining output power of transistors [15]. In the 5-W HPA,
a tree-structure power combiner is used for power combining
2[Online]. Available: www.home.agilent.com
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NIKANDISH AND MEDI: DESIGN PROCEDURE FOR HIGH-EFFICIENCY AND COMPACT-SIZE MMIC PAs IN GaAs pHEMT TECHNOLOGY
Fig. 4. Output power and PAE contours at 10 GHz. Top: for an 8 150- m
transistor with 20 dBm and in the 5-W HPA.
Bottom: for a composite power cell including two 8 290- m transistors with
26 dBm and in the 8-W HPA.
TABLE I
OPTIMUM LOAD AND SOURCE IMPEDANCES OF A TRANSISTOR IN 5-W HPA
as well as impedance transformation. Shown in Fig. 5(a), the
drain bias line is also embedded in the OMN, and its ef-
fects are considered in simulations. In standard microwave cir-
cuit designs, the drain bias is provided through large inductors
or quarter-wavelength lines that exhibit high impedance at the
frequency of operation. However, these methods occupy large
chip area in the targeted frequency band. In the current design,
the drain bias line has shorter length and exhibits a finite induc-
tance. The OMN is designed with this line as an element that
its length is optimized by simulator. The width of the drain bias
line is determined based on current density limit specified by the
process. The loss of the OMN should be minimized as it directly
degrades the output power delivered to the load. Double-metal
microstrip lines are used to minimize ohmic losses. Moreover, a
dummy bias line is included to make the output power
combiner characteristics more symmetric and reduce losses due
to imperfect power combining. Length and width of other lines
5
Fig. 5. Schematic of OMN. (a) 5-W HPA. (b) 8-W HPA. Half of the circuits
are shown.
and size of capacitors are optimized in Agilent ADS environ-
ment to achieve desired power combining and impedance trans-
formation characteristics.
In the 8-W HPA, a bus bar line is used to provide the drain
bias current and also combine the output power of the tran-
sistors. As shown in Fig. 5(b), the OMN transforms the 50-
load impedance into the optimum load impedance
of the composite power cell discussed above. Only length of
lines and the size of the capacitors are optimized to
achieve the desired impedance transformation. As discussed in
Section IV, this approach leads to a more compact layout at the
cost of slightly lower PAE due to suboptimal load impedance
for the output stage transistors.
2) Inter-Stage Matching Network (ISMN): The ISMN
should be designed to provide the optimum source impedance
for the output stage transistors and the optimum load
impedance for the input stage transistors . It also
divides output power of the input stage transistors between the
output stage devices. The large size of the output stage tran-
sistors makes their input impedance very small, while
is quite larger. Thus, the impedance transformation
ratio (TR) [1] is very high for the ISMN. For example, in the
5-W HPA at 10 GHz, we have
(7)
Realization of wideband impedance transformers with high
TR values requires complicated networks. Therefore, ISMN
in HPA introduces significant loss, limits the overall ampli-
fier bandwidth, and occupies a large chip area. Loss of the
ISMN degrades the HPA power gain. However, as the input
power is chosen to saturate the output stage devices, this loss
has insignificant effect on the output power and efficiency.
Schematics of ISMN of HPAs are shown in Fig. 6. The gate
bias line of the output stage transistors and the drain
bias line of the input stage transistors are also included
in the ISMN. In the 5-W HPA, the dummy gate bias lines [
in Fig. 6(a)] are used to make the inter-stage power divider
more symmetric and reduce losses. In the 8-W HPA, the gate
bias line of the output stage transistors is placed farther from
the transistors [Fig. 6(b)]. Therefore, the dummy lines can be
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6 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 6. Schematic of ISMN. (a) 5-W HPA. (b) 8-W HP. Half of the circuits are
shown.
Fig. 7 Schematic of IMN. (a) 5-W HPA. (b) 8-W HPA. Half of the circuits are
shown.
removed and chip area occupied by the ISMN is considerably
reduced.
To protect the gate of transistors against thermal runaway and
limit the gate current, integrated resistors are inserted in series
with the gate bias lines ( in Fig. 6). These resistors can also
improve the HPA’s overall stability [16]. However, it should be
noted that, as the input signal power increases, the gate current
of the transistors also increases, which causes higher voltage
drops on the gate resistor and the device gate bias voltage is
changed. Thus, the HPA compression point in high input power
levels is degraded [1]. In current HPA designs, these resistors
are optimized considering these tradeoffs.
3) Input-Matching Network (IMN): The IMN transforms the
input impedance of the input stage transistors to the 50- source
impedance. It also divides the input power between the input
stage devices. Similar to the ISMN, impedance transformation
ratio is high for the IMN. However, losses in the IMN only af-
fect the amplifier gain and have negligible effect on the output
power and PAE. Thus, resistive elements can be used in the
IMN to improve the bandwidth and input impedance matching.
Schematics of IMN of the HPAs are shown in Fig. 7. The gate
bias lines of the input stage transistors are also em-
bedded in this network. The resistor is inserted in series
with the gate bias lines for protection of the gate of transistors.
4) Harmonic Termination: The efficiency of power ampli-
fiers can be improved by performing appropriate harmonic ter-
minations [17]. There are several challenges in adopting the
harmonic termination in HPAs. Among these are the increased
Fig. 8. Harmonic termination network used at output of the input stage tran-
sistors in the 5-W HPA.
layout complexity, higher losses caused by harmonic termina-
tion circuit, and difficulties in performing the harmonic termi-
nation in the entire operation frequency band. In the design of
the 5-W HPA, a harmonic-termination network is inserted at
the output of the input stage transistors instead of the output
stage devices. This enables performing harmonic termination
with lower loss and chip area penalties. The harmonic termina-
tion network and its equivalent impedance are shown in Fig. 8.
This network is designed such that it provides high impedance
(greater than 80 ) in the entire frequency band, while ma-
nipulating the second and third harmonics at the drain of the
input stage transistors to improve PAE by about 5%. If this har-
monic termination network is placed at the output of HPA, it
even degrades the PAE at some frequencies. This circuit is not
employed in the 8-W HPA as this design is primarily targeted
for compact layout, however similar technique could have been
used there as well.
As the transistors are not unilateral, the IMNs affect each
other and cannot be designed independently. Thus, after de-
signing the IMNs based on the optimum load and source im-
pedances of each stage, the overall amplifier is optimized again
to account for such effects. The effects of EM coupling and
line discontinuities are accounted for using EM simulations. All
IMNs are designed and optimized using EM simulations per-
formed in Agilent ADS Momentum environment . As the thick-
ness of the amplifier structure is much smaller than the substrate
thickness, 2.5-D EM simulations of ADS Momentum provide
accurate results. Final schematics of HPAs are shown in Fig. 9.
F. Large-Signal Stability
The small-signal stability of the HPA is verified using
the -factor stability criterion. However, as the input power
increases, the HPA may exhibit unstable behavior in certain
intervals of the input power and frequency. As explained in
[16], [18], and [19], instability in HPAs has several origins. The
nonlinear input capacitance of transistors can result in negative
resistance in high input power levels, increasing the risk of
parametric oscillations. In addition, the conventional presence
of power dividers and combiners in HPAs with multiple transis-
tors can lead to odd- and even-mode oscillations in the circuit
internal loops. Thus, large-signal simulations are required to
identify the existence of such instabilities.
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NIKANDISH AND MEDI: DESIGN PROCEDURE FOR HIGH-EFFICIENCY AND COMPACT-SIZE MMIC PAs IN GaAs pHEMT TECHNOLOGY 7

Fig. 9. Schematic of (a) 5-W HPA and (b) 8-W HPA. Half of the circuits are shown.

For stability simulation, a small-signal auxiliary power to derive reflection coefficient [20]. To ensure stability,
source at frequency is applied to the drain terminal the condition should be satisfied at all auxiliary
of a transistor, while the RF power at frequency (pump frequencies in the range and RF frequencies in
signal) is applied to the HPA input [Fig. 10(a)]. The reflected the operation band of the HPA. In addition, the stability should
power to the auxiliary power source at is then calculated be checked in several input power levels to ensure stability in
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8 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 10. Setup for large-signal stability simulations. (a) Parametric oscillation
detection. (b) Odd/even mode instability detection.
Fig. 11. Odd-mode stability simulation results. (a) Without
With resistors.
back-off, where the HPA gain is higher. Out of the frequency
band of operation, the gain of HPA rapidly falls due to high
order of IMNs. Thus, the HPA is commonly stable at these
frequencies.
This method can also be used for odd- and even-mode insta-
bility simulations [Fig. 10(b)]. For odd-mode instability simula-
tion, two out-of-phase signals with the same power
level and frequency are applied to drain terminals of two transis-
tors in the HPA in the presence of the input signal. Similarly, for
even-mode instability simulation, two in-phase signals
are applied to the HPA. All permutations of two drain terminals
should be checked for possible instabilities.
Extensive harmonic-balance (HB) simulations should be per-
formed to identify possible large-signal instabilities. The insta-
bilities are more likely observed in odd-mode stability simula-
tions. In the even-mode stability simulations, transistors are ex-
cited with in-phase signals, thus the device stability behavior is
similar to its normal operation which is stable at the frequency
band of operation. A sample of the odd-mode instability simu-
lation results for the 5-W HPA, shown in Fig. 11, indicates that
Fig. 12. Die photograph of the 5-W HPA (dimensions: 5.68 3.00 mm ).
the amplifier is potentially unstable. The RF frequency
is varied in the range 8–13 GHz with a step size of 0.25 GHz,
while the auxiliary source frequency is varied in the
range 0.1 GHz to with a step size of 0.1 GHz.
To eliminate the instabilities, several resistors are inserted
between the drain terminals of the output stage transistors and
some symmetric points in the ISMN (denoted by in Fig. 9).
The resistance value is 100 in the 5-W HPA and 25 in the
8-W HPA. These resistors reduce the gain of internal loops in
the odd-mode of operation, thus suppressing the odd-mode os-
cillations [Fig. 8(b)]. In theory, the parallel amplification paths
are symmetric, and these resistors have no effect on the HPA
normal operation. In practice, these resistors reduce asymme-
tries between the parallel amplification paths, thereby improve
the output power. The current flowing through these resistors
can be high depending on mismatch between drain currents of
transistors, thus current density limitations should be considered
in their layout.
IV. MEASUREMENT RESULTS
resistors. (b)
The HPAs are implemented in a 0.25- m gate-length Al-
GaAs–InGaAs pHEMT process. The chip die is directly
attached to the backside heat-sink using a conductive epoxy
with good thermal conduction. The chip is connected to the
external board using 18- m-diameter gold bond wires. The test
board provides adjustable bias voltages and RF input and output
access through 50- microstrip lines. The chip is attached to a
heat-sink to limit the chip temperature. Several samples of each
HPA have been tested to ensure repeatability of the measured
results.
A. 5-W HPA Measurements
The 5-W HPA chip photograph is shown in Fig. 12. The
HPA is biased with 8 V, 0.8 V, leading
to 1360 mA of total quiescent bias current, including 1100 mA
in the output stage and 260 mA in the input stage. When the
input power level is increased to drive the HPA into satura-
tion, the total dc bias current is increased to approximately
1400–1800 mA. The measured and simulated -parameters
of the HPA are depicted in Fig. 13. In the frequency band of
8.5–12.5 GHz, the small-signal gain is 19.8 1.2 dB, and the
input and output reflection coefficients are smaller than 9.9
and 8.7 dB, respectively.
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NIKANDISH AND MEDI: DESIGN PROCEDURE FOR HIGH-EFFICIENCY AND COMPACT-SIZE MMIC PAs IN GaAs pHEMT TECHNOLOGY 9

Fig. 13. Measured and simulated -parameters of the 5-W HPA.

Fig. 14 shows the measurement and simulation results of

the saturated output power, PAE and input-referred third-order
intercept point (IIP3). The large-signal measurements are per-
formed in the CW-mode operation with 20-dBm input power.
The output power ranges from 36.5 to 37.8 dBm over the
frequency band 8.7–12.5 GHz. The maximum output power
37.8 dBm (6 W) is achieved at 10.5 GHz. Over this frequency
band, the PAE varies between 37% and 48%, reaching the
peak of 48% at 9 GHz. The discrepancy between the measured Fig. 14. Measured and simulated (a) output power, (b) PAE, and (c) IIP3 of the
5-W HPA.
and simulated PAE is mainly due to the inaccuracies in the
transistors large-signal models. The IIP3 is obtained using the
two-tone test with 0-dBm input power and 10-MHz frequency
spacing. The maximum measured IIP3 is 27.8 dBm obtained at
10.5 GHz.
Fig. 15 depicts the output power, gain, and PAE in terms of
the input power measured at 10.5 GHz (where the maximum
output power is achieved). The measured output-referred 1-dB
compression point of the HPA is 37.4 dBm with 41%
associated PAE.

B. 8-W HPA Measurements

The 8-W HPA, shown in Fig. 16, is biased with 8 V,
0.8 V. Its total quiescent bias current is 2450 mA,
including 1970 mA in the output stage and 480 mA in the
input stage. The total dc bias current increases to about
2700–3270 mA when the HPA is driven into saturation. The
measured and simulated -parameters of the HPA are depicted
in Fig. 17. In the frequency band of 7–11 GHz, the small-signal
gain is 17.9 1.8 dB, and the input and output reflection
coefficients are smaller than 7.8 and 8 dB, respectively.
Fig. 18 shows the measurement and simulation results of
the saturated output power, PAE and IIP3. The large-signal
measurements are performed in the CW-mode operation with
Fig. 15. Measured (solid lines) and simulated (dashed/dotted lines) output
power, gain, and PAE at 10.5 GHz for a 5-W HPA.
27-dBm input power. The output power varies in the range
38.8–40 dBm in the frequency band of 7.5–12 GHz. The
maximum output power 40 dBm (10 W) is achieved at 8 GHz.
In this frequency band, the PAE varies between 30% and 40%,
with the maximum value of 40% at 9 GHz. The IIP3 is derived
from the two-tone test with 10-dBm input power and 10-MHz
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10 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 16. Die photograph of the 8-W HPA (dimensions: 2.97 2.95 mm ).

Fig. 18. Measured and simulated (a) output power, (b) PAE, and (c) IIP3 of the
8-W HPA.

Fig. 17. Measured and simulated -parameters of the 8-W HPA.

frequency spacing. Its maximum is 33.2 dBm, measured at

12 GHz. In Fig. 19, the output power, gain, and PAE are shown
in terms of the input power measured at 8 GHz. The measured Fig. 19. Measured (solid lines) and simulated (dashed/dotted lines) output
of the HPA is 38.2 dBm with 30% associated PAE. power, gain, and PAE at 8 GHz for 8-W HPA.

C. Comparison and Discussion

In Table II, the performance of several state-of-the-art GaAs PAE ( ) as well as the bandwidth and output power
pHEMT and HBT -band HPAs are summarized. For quali- are calculated as figure-of-merits (FOMs) for
tative comparison of HPAs, the products of the bandwidth and broadband operation of HPA. Moreover, the output power per
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
NIKANDISH AND MEDI: DESIGN PROCEDURE FOR HIGH-EFFICIENCY AND COMPACT-SIZE MMIC PAs IN GaAs pHEMT TECHNOLOGY
TABLE II
COMPARISON OF DESIGNED HPAS WITH STATE-OF-THE-ART
chip area is calculated as a measure of effective
usage of the chip area to produce output power.
The 5-W HPA presented in this paper achieves one of the
highest PAE values over a broad bandwidth. Among HPAs with
at least 5-W (37 dBm) output power, only the PAE of HPAs re-
ported in [3] and [11] exceeds that of the current design. How-
ever, both are obtained over narrower bandwidths (and mea-
sured in the pulse mode). It should be noted that when an HPA
is designed for narrow bandwidth, better matching to the op-
timum termination impedances can be achieved, thus it is ex-
pected to achieve higher PAE compared to the case that is de-
signed for wider bandwidth. Moreover, the output power and
PAE of an HPA measured in the pulse-mode operation are com-
monly higher than that measured in the CW-mode operation [1]
(see pulse- and CW-mode performances of HPAs in [3] and [10]
given in Table II). Comparison of the BW.PAE and
values for HPAs in Table II indicates that both of the designed
HPAs provide superior broadband performance.
The 8-W HPA achieves the lowest chip area reported for
GaAs pHEMT and HBT HPAs. The chip area is 20% lower than
the most compact size pHEMT HPA reported in [2]. This results
in the maximum value of 1.14 W/mm in the CW
mode, while the highest reported values are 0.97 W/mm in the
pulse mode [2], [13] and 0.74 W/mm in the CW mode [3].
V. CONCLUSIONS
The design procedure and measurement results of a high-ef-
ficiency 5-W HPA and as well as a compact size 8-W HPA fab-
ricated in an AlGaAs–InGaAs pHEMT technology were pre-
sented. The 5-W HPA features 40% average PAE, 20 dB average
11
-BAND MMIC HPAS
small-signal gain, and 9.9 dB/8.7 dB minimum input/output re-
turn loss in the frequency band of 8.5–12.5 GHz. The peak per-
formance of the HPA is 37.8 dBm (6 W) output power and 48%
PAE. Compared to available -band HPAs, the designed 5-W
HPA exhibits one of the highest efficiencies over a wide band-
width. The 8-W HPA provides 35% average PAE, 17.5-dB av-
erage small-signal gain, and 7.8-dB/8 dB minimum input/output
return loss in the frequency band of 7.5–12 GHz. The HPA max-
imum output power and PAE are 40 dBm (10 W) and 40%, re-
spectively. The 8-W HPA occupies 8.8 mm chip area, which is
the smallest chip area and corresponds to the highest
reported for GaAs HBT and pHEMT HPAs in the same fre-
quency band.
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Gholamreza Nikandish (S’11) received the B.Sc.
degree (with honors) form the Shahid Chamran
University, Ahvaz, Iran, in 2004, and the M.Sc.
degree from the Sharif University of Technology,
Tehran, Iran, in 2006, both in electrical engineering.
He is currently working toward his Ph.D. degree at
the Sharif University of Technology.
His research interests include RF and microwave
integrated circuits.
Ali Medi (S’98–M’08–SM’13) received the B.Sc.
degree from the Sharif University of Technology,
Tehran, Iran, in 2001, and the M.Sc. and Ph.D.
degrees in electrical engineering from the University
of Southern California, Los Angeles, in 2003 and
2007, respectively.
He is currently an Assistant Professor with the
Electrical Engineering Department, Sharif Univer-
sity of Technology, Tehran, Iran. He was a Research
Assistant with the UltRaLab, where he worked
in the field of analog and RF circuit design for
ultra-wideband systems. He was with Broadcom Corporation, developing RF
blocks for GSM cellular phone transceivers. His research interests are RF and
microwave integrated circuits as well as wideband analog circuit design.