1867-7 Cwiklinski EPrint

Science for Systems
Design of Millimeter-Wave Power

$PSOLğHUVLQ*DOOLXP1LWULGH+LJK
Electron-Mobility Transistor Technology
Maciej Ćwikliński
Fraunhofer Verlag
Fraunhofer Institute for
Applied Solid State Physics IAF
Science for Systems

No. 59
Maciej Ćwikliński
Design of Millimeter-Wave Power
Amplifiers in Gallium Nitride High-
Electron-Mobility Transistor Technology
Fraunhofer Verlag
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Applied Solid State Physics IAF
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ISBN (print edition): 978-3-8396-1867-7

DOI (free PDF version): https://doi.org/10.24406/publica-330
D 25
Zugl.: Freiburg, Univ., Diss. 2022
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Albert-Ludwigs-Universität Freiburg
Design of Millimeter-Wave
Power Amplifiers in Gallium Nitride
High-Electron-Mobility Transistor
Technology
Dissertation
submitted in partial fulfillment of the
requirements for the degree of
Doktor-Ingenieur (Dr.-Ing.)
by
Maciej Ćwikliński
Freiburg im Breisgau, Germany

Dean
Prof. Dr. Rolf Backofen
Referees
Prof. Dr. Rüdiger Quay
Prof. Dr.-Ing. habil. Dietmar Kissinger
Date of the Examination

January 31, 2022
To Ania & Leon
„We choose to go to the Moon and do the other things,
not because they are easy, but because they are hard.“
John F. Kennedy
Rice University, September 12, 1962
vii
Abstract
Gallium nitride (GaN) high-electron-mobility transistor (HEMT) technology appears as an
appealing candidate for supporting a variety of millimeter-wave (mm-wave) applications
with its unique combination of simultaneous high-voltage and high-frequency operation.
However, despite the rapid advance in GaN HEMT technology, the reported available gain
of the devices is still limited at higher mm-wave frequencies in comparison to the com-
peting high-speed semiconductor processes. This work investigates several approaches
to enhance the performance of GaN-based circuits operating within the millimeter-wave
spectrum. The main aim of this work is to provide a set of design approaches and
techniques to enable broadband operation of mm-wave GaN power amplifier monolithic
microwave integrated circuits (MMICs), with a particular focus on frequencies close to
and beyond the 100-GHz mark. In order to fulfill this goal, these approaches need to
simultaneously target distinct design levels. Furthermore, implementing the concepts
investigated in this work on circuit-level resulted in several MMICs providing state-of-
the-art performance among GaN-based power amplifiers.
One of the investigated approaches for optimizing the bandwidth performance of power
amplifiers is related to the two key passive parts of any active MMIC, namely the matching
and biasing networks. Matching network design has, besides the capabilities of the
active devices, a decisive impact on the overall performance of the circuit. The optimal
matching network design by incorporating low-impedance transmission lines can push the
circuit’s bandwidth performance closer towards the theoretical limits set, for instance,
by the Bode-Fano criterion and the often-necessary transformation of the real part of
the impedance, which can be achieved by using low-impedance microstrip lines. The
amplifier’s bandwidth can be also enhanced by improving the performance of the bias
networks. The radial stub has been identified as a key element of such networks for mm-
wave MMIC applications. In this work, a novel topology approach to the radial stub with
a superior bandwidth performance is introduced. By using two slightly separated half-
stubs, a second in-band resonance is created. As a result, this radial stub can provide a
nearly two-fold improvement over the conventional radial stub in the rejection fractional
bandwidth. Combining these two passive network concepts resulted in power amplifiers
that can deliver on average 27 dBm or 0.5 W of output power over a 70–110-GHz band.
This is the first demonstration of a full W-band (75–110 GHz) power amplifier based on
GaN HEMT technology.
Alternatively to the passive networks design considerations, the high-frequency perfor-
mance of GaN-based amplifiers can be improved also due to topology-based enhance-
ments. The improved reverse isolation of the cascode results in a significantly higher
maximum gain of this topology when compared with the common-source configuration.
Therefore, the cascode topology appears as an appealing alternative for applications in
GaN power amplifiers operating at the higher mm-wave bands, where the available gain of
GaN HEMTs is limited. This topology variant allows for designing a power amplifier that
viii Abstract
can cover the 107–148-GHz band with more than 25-dB of small-signal gain with peak
output power and power-added efficiency values of 26.4 dBm and 16.5 %, respectively.
A wideband performance can be achieved also by employing an fT -doubler configuration,
which enhances the current gain of transistors in the utilized semiconductor process.
However, applying this topology at mm-wave frequencies is a challenging task due to the
layout-induced parasitic effects that degrade the high-frequency performance. This work
introduces a novel integrated layout based on GaN HEMTs. The compact approach
described in this thesis allows for minimizing the layout-induced parasitic effects, which
enables operation at high frequencies. The potential of the fT -doubler topology using the
novel integrated layout approach for broadband MMIC applications is demonstrated with
two amplifiers able to cover several mm-wave waveguide bands. These circuits can pro-
vide a small-signal gain better than 10 dB and output power ranging between 14.5 dBm to
20.6 dBm from about 28 GHz up to 90 GHz. This corresponds to a fractional operating
bandwidth of 105 % or 1.68 octaves.
Another method for improving the gain of GaN circuits operating beyond 100 GHz is
related to modifying the geometry of a single transistor. One example of such a modi-
fication of a GaN HEMT with a pronounced effect on its high-frequency performance is
optimizing the gate-drain and gate-source contact spacings. This geometry-based modi-
fication impacts the key effective parameters of the transistor, which significantly influ-
ence the high-frequency gain. In addition, the performance of high-frequency GaN circuits
can be further improved with proper dimensioning of the transistors. An increased oper-
ating voltage of GaN HEMTs with respect to other high-speed semiconductor technolo-
gies induces specific output impedance levels, which requires considering several design
tradeoffs when selecting an optimal GaN HEMT geometry for G-band (140–220 GHz)
applications. Although implementing the aforesaid geometry-based methods can sig-
nificantly enhance the high-frequency gain of GaN devices on transistor level, many of
such HEMT stages need to be cascaded in order to obtain a practical circuit-level gain.
Therefore, scaling the passive networks is a crucial effort to support GaN circuits oper-
ating at higher mm-wave bands. Moreover, in amplifiers incorporating many gain stages,
the interstage matching network is the critical passive network, which often defines the
overall MMIC performance and size. This work proposes a novel compact interstage
layout, which allows to advance the performance of GaN-based circuits above 200 GHz.
Combining the transistor-level design techniques with passive network scaling resulted
in broadband G-band amplifiers, which offer the highest gain and output power among
the reported GaN-based MMICs to date. It is also the first-ever demonstration of GaN
circuits able to operate beyond the 200-GHz mark.
ix
Zusammenfassung
Die Galliumnitrid (GaN) Transistoren mit hoher Elektronenbeweglichkeit (HEMTs) er-
scheinen als attraktive Technologie-Kandidaten für die Unterstützung einer Vielzahl von
Millimeterwellenanwendungen mit einer einzigartigen Kombination aus gleichzeitigem
Hochspannungs- und Hochfrequenzbetrieb. Trotz des rasanten Fortschritts in der GaN
HEMT-Technologie ist die bisher verfügbare Verstärkung dieser Bauelemente bei höheren
Millimeterwellenfrequenzen im Vergleich zu den konkurrierenden Hochgeschwindigkeits-
Halbleiterprozessen jedoch noch begrenzt. Diese Arbeit untersucht mehrere Ansätze zur
Leistungssteigerung von GaN-basierten Schaltungen, die innerhalb des Millimeterwellen-
spektrums arbeiten. Das Hauptziel dieser Arbeit ist, eine Reihe von Entwurfsansätzen
und Entwurfstechniken bereitzustellen, um den Breitbandbetrieb von Millimeterwellen-
GaN-Leistungsverstärkern basierend auf monolithisch integrierten Mikrowellenschaltun-
gen (MMICs) zu ermöglichen, mit einem besonderen Fokus auf Frequenzen in der Nähe
und oberhalb der 100-GHz-Marke. Um dieses Ziel zu erreichen, müssen diese Ansätze
gleichzeitig unterschiedliche Designebenen adressieren. Darüber hinaus führte die Um-
setzung der in dieser Arbeit auf Schaltungsebene untersuchten Konzepte zu mehreren
MMICs, die unter GaN Leistungsverstärkern herausragende Performance zeigen.
Einer der untersuchten Ansätze zur Optimierung der Bandbreite von Leistungverstärkern
bezieht sich auf die beiden wichtigsten passiven Teile jedes aktiven MMICs, nämlich die
Anpassung und die Bias-Versorgungs-Netzwerke. Das Design des Anpassungsnetzwerks
hat neben den Fähigkeiten der Transistoren einen entscheidenden Einfluss auf die Ge-
samtperformance der Schaltung. Das optimale Design des Anpassungsnetzwerks durch
die Integration von Leitungen mit niedriger Impedanz kann die Bandbreitenfähigkeit der
Schaltung näher an die theoretischen Grenzen des Bode-Fano-Kriteriums und die oft
notwendige Transformation des Realteils der Impedanz bringen, die durch den Einsatz
von Mikrostreifenleitungen mit niedriger Impedanz erreicht werden kann. Die Bandbreite
des Verstärkers kann auch durch die Bias-Netzwerke verbessert werden. Der Radial-Stub
wurde als Schlüsselelement solcher Netzwerke für Millimeterwellen-MMIC-Anwendungen
identifiziert. In dieser Arbeit wird ein neuartiger Topologieansatz für den Radial-Stub
mit einer überlegenen Bandbreite eingeführt. Durch die Verwendung von zwei leicht ge-
trennten Halb-Radial-Stubs entsteht eine zweite In-Band-Resonanz. Dadurch kann dieser
neuartige Radial-Stub eine fast zweifache Verbesserung gegenüber dem herkömmlichen
Radial-Stub in der relative Bandbreite des Stopbandes ermöglichen. Die Kombination die-
ser beiden passiven Netzwerkkonzepte führte zu Leistungsverstärkern, die durchschnitt-
lich 27 dBm oder 0,5 W Ausgangsleistung über das 70–110-GHz-Band liefern können.
Dies ist die weltweit erste Demonstration eines Leistungsverstärkers auf Basis der GaN
HEMT-Technologie, der das gesamte W-band (75–110 GHz) abdeckt.
Alternativ zu den Überlegungen zur Konstruktion von passiven Netzwerken kann die
Hochfrequenz-Performance von GaN-basierten Verstärkern auch durch topologiebasierte
Weiterentwicklungen verbessert werden. Die verbesserte Rückwärts-Isolation der Cascode-
x Zusammenfassung
HEMTs führt im Vergleich zur Common-Source-Konfiguration zu einer deutlich höheren

maximalen Verstärkung dieser Topologie. Daher erscheint die Cascode-Topologie als at-
traktive Alternative für Anwendungen in GaN-Leistungsverstärkern, die in den höheren
Millimeterwellen-Bändern arbeiten, wo die verfügbare Verstärkung von GaN HEMTs be-
grenzt ist. Diese Topologievariante ermöglichte die Entwicklung eines Leistungsverstärkers,
der das 107–148-GHz-Band mit mehr als 25 dB Kleinsignalverstärkung abdecken kann,
mit Ausgangsleistung bis 26,4 dBm und Leistungswirkungsgrad bis 16,5 %. Eine hohe
Breitband-Performance kann auch durch den Einsatz einer fT -Doubler-Konfiguration er-
reicht werden, die die Stromverstärkung der Transistoren im eingesetzten Halbleiterpro-
zess verbessert. Die Anwendung dieser Topologie bei mm-Wellenfrequenzen ist jedoch
aufgrund der Layout-induzierten parasitären Effekte, die die Hochfrequenz-Performance
beeinträchtigen, eine schwierige Aufgabe. Diese Arbeit führt ein neuartiges integriertes
Layout ein, das auf GaN HEMTs basiert ist. Der in dieser Dissertation beschriebene kom-
pakte Ansatz ermöglicht die Minimierung der Layout-induzierten parasitären Effekte, die
den Betrieb bei hohen Frequenzen ermöglichen. Das Potenzial der fT -Doubler Topologie
mit dem neuartigen integrierten Layout-Ansatz für Breitband-MMIC-Anwendungen wird
mit zwei Verstärkern demonstriert, die mehrere Millimeterwellen-Hohlleiterbänder abde-
cken können. Diese Schaltungen können eine Kleinsignalverstärkung von besser als 10 dB
und eine Ausgangsleistung zwischen 14,5 und 20,6 dBm von etwa 28 GHz bis 90 GHz
bieten. Dies entspricht einer relativen Bandbreite von 105 % oder 1,68 Oktaven.
Eine andere Methode zur Verbesserung der Verstärkung von GaN-Schaltungen, die über
100 GHz hinaus arbeiten, ist die Optimierung der Geometrie eines einzelnen Transis-
tors. Ein Beispiel für eine solche Modifikation eines GaN HEMT mit einer ausgepräg-
ten Wirkung auf seine Hochfrequenz-Performance ist die Optimierung der Gate-Drain-
und Gate-Source-Abstände. Diese geometriebasierte Modifikation wirkt sich auf die ef-
fektiven Parameter des Transistors aus, die die Hochfrequenzverstärkung maßgeblich
beeinflussen. Darüber hinaus kann die Leistung von hochfrequenten GaN-Schaltungen
durch die richtige Dimensionierung der Transistoren weiter verbessert werden. Eine erhöh-
te Betriebsspannung von GaN HEMTs im Vergleich zu anderen Hochgeschwindigkeits-
Halbleitertechnologien bedingt spezifisch-hohe Ausgangsimpedanzniveaus, was die Be-
rücksichtigung mehrerer Design-Kompromisse bei der Auswahl einer optimalen GaN HEMT
Geometrie für G-band (140–220 GHz) Anwendungen erfordert. Obwohl die Implemen-
tierung der oben genannten geometriebasierten Methoden die Hochfrequenzverstärkung
von GaN-Schaltungen auf Transistorebene erheblich verbessern kann, müssen viele dieser
HEMT-Stufen kaskadiert werden, um ein praktisch nutzbare Verstärkung auf Schaltungs-
ebene zu erzielen. Daher ist die Skalierung der passiven Netzwerke ein entscheidender An-
satz, GaN-Schaltungen zu entwickeln, die auf höheren mm-Wellenbändern betrieben wer-
den können. Darüber hinaus ist das Interstage-Anpassung-Netzwerk bei Verstärkern mit
vielen Stufen das kritische passive Netzwerk, das oft die Gesamtperformance und die Grö-
ße von MMICs definiert. Diese Arbeit schlägt ein neuartiges kompaktes Interstage-Layout
vor, das es ermöglicht, den Betrieb von GaN-basierten Schaltungen über 200 GHz voran-
zubringen. Die Kombination der Design-Techniken auf Transistorebene mit der Skalierung
der passiven Netzwerke führte zu Breitband G-band Verstärkern, die die höchste Verstär-
kung und Ausgangsleistung unter den bisher publizierten GaN-basierten MMICs bieten. Es
ist auch die erste Demonstration von GaN-Schaltungen, die jenseits der 200-GHz-Grenze
arbeiten.
xi
Contents
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Zusammenfassung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
List of Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Objectives and Organization of the Thesis . . . . . . . . . . . . . . . . 2
2 Fundamentals of Gallium Nitride Millimeter-Wave Power Amplifiers . . . . . 7

2.1 Millimeter-Wave Frequencies . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Gallium Nitride for High-Frequency Applications . . . . . . . . . . . . . 11
2.3 Overview of State-of-the-Art Millimeter-Wave Power Amplifiers . . . . 13
2.4 Millimeter-Wave GaN HEMT Technology . . . . . . . . . . . . . . . . 15
2.5 Experimental Verification of the HEMT Model at the W-Band . . . . . 17
2.6 Conclusions on Chapter 2 . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Passive Network Considerations for Broadband GaN Power Amplifiers . . 21

3.1 Broadband and Low-Loss Matching Networks . . . . . . . . . . . . . . 21
3.1.1 The Broadband Impedance Matching Problem . . . . . . . . . 22
3.1.2 Importance of Using Low-Impedance Transmission Lines . . . . 26
3.1.3 Low-Loss Matching Networks . . . . . . . . . . . . . . . . . . 27
3.1.4 Low-Impedance and Low-Loss Microstrip Lines . . . . . . . . . 28
3.1.5 Experimental Verification of Low-Impedance Matching Networks 32
3.1.6 Microstrip-to-Coplanar Mode Transition . . . . . . . . . . . . . 35
3.2 Broadband DC-Biasing Networks Using Novel Radial Stubs . . . . . . . 37
3.2.1 Modeling of the Conventional Radial Stub . . . . . . . . . . . . 38
3.2.2 Existing Solutions to Bandwidth Enhancement of the Radial
Stub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.3 A Novel Type of Radial Stub . . . . . . . . . . . . . . . . . . . 40
3.2.4 Model Development for the Novel Separated Radial Stub . . . . 40
3.2.5 Experimental Verification of the Novel Radial Stub . . . . . . . 44
3.2.6 Mathematical Formulation for the Novel Stub . . . . . . . . . . 47
3.2.7 Optimization of the Input Reflection of the Novel Radial Stub . 49
3.3 Application of the Passive Network Concepts on Circuit Level . . . . . 54
3.3.1 Design of Full W-Band GaN Power Amplifiers . . . . . . . . . . 54
xii Contents
3.3.2 Impact of the Radial Stub Configuration on the MMIC

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3.3 Measurement Results of the Power Amplifiers . . . . . . . . . . 56
3.3.4 Comparison with the State of the Art . . . . . . . . . . . . . . 59
4 Topology-Based Performance Enhancements of GaN Power Amplifiers . . 63

4.1 D-Band GaN Power Amplifier Using a Cascode Topology . . . . . . . . 64
4.1.1 The Cascode Topology . . . . . . . . . . . . . . . . . . . . . . 64
4.1.2 Experimental Evaluation of a GaN HEMT Cascode Cell . . . . 65
4.1.3 Design of a Cascode-Based D-Band Power Amplifier . . . . . . 67
4.1.4 Measured Performance of the D-Band Power Amplifier . . . . . 69
4.1.5 Comparison with the State of the Art . . . . . . . . . . . . . . 72
4.2 Millimeter-Wave Integrated fT -Doubler Topology . . . . . . . . . . . . 74
4.2.1 The Darlington Topology . . . . . . . . . . . . . . . . . . . . . 74
4.2.2 The fT -Doubler Topology . . . . . . . . . . . . . . . . . . . . 75
4.2.3 Millimeter-Wave fT -Doubler: A Novel Integrated Layout
Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.2.4 Experimental Evaluation of the Integrated AC-Coupled
fT -Doubler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.2.5 Broadband Amplifiers Employing the Integrated fT -Doubler . . 92
5 Layout Considerations for G-Band GaN Amplifiers . . . . . . . . . . . . . . 97

5.1 Geometry-Based High-Frequency Gain Enhancement of GaN HEMTs . 97
5.1.1 Transistor Layout Considerations for G-Band GaN Amplifiers . . 98
5.1.2 Experimental Comparison of Two GaN HEMT Layouts . . . . . 104
5.1.3 Dimensioning GaN HEMTs for High-Frequency Applications . . 113
5.1.4 Application of the Transistor Layout Concepts in Broadband
G-Band GaN Amplifiers . . . . . . . . . . . . . . . . . . . . . . 117
5.2 Advancing GaN Amplifiers Beyond 200 GHz . . . . . . . . . . . . . . . 120
5.2.1 Scaling the Coplanar Waveguide Passive Networks . . . . . . . 120
5.2.2 Modeling of Coplanar Waveguide Networks Based on
Electromagnetic Simulations . . . . . . . . . . . . . . . . . . . 125
5.2.3 Novel Compact Interstage Matching Network for Multi-Stage
High-Frequency GaN Amplifiers . . . . . . . . . . . . . . . . . 132
5.2.4 Examples of GaN Amplifiers Operating Beyond 200 GHz . . . . 134
6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.1 Summary and Conclusions of the Thesis . . . . . . . . . . . . . . . . . 145
6.2 Impact of the Work on the State of the Art . . . . . . . . . . . . . . . 148
A General Two-Port Formulation of the fT -Doubler Configuration . . . . . 153
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
List of Personal Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Contents xiii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
xv
List of Abbreviations
2DEG Two-dimensional electron gas

5G Fifth generation technology standard for cellular networks
6G Sixth generation technology standard for cellular networks
ABCD-Parameters Transmission parameters
AC Alternating current
AlGaN Aluminium gallium nitride
AlN Aluminium nitride
Au Gold
BEOL Back end of line
BW Bandwidth
CAD Computer-aided design
CB Common base
CE Common emitter
CG Common gate
CMOS Complementary metal-oxide semiconductor
CPW Coplanar waveguide
CS Common source
CW Continuous wave
D-Band Electromagnetic spectrum band from 110 GHz to 170 GHz
DC Direct current
DE Drain efficiency
DIBL Drain-induced barrier lowering
DL Dissipative loss
DUT Device under test
E-Band Electromagnetic spectrum band from 60 GHz to 90 GHz
E-Beam Electron beam
E-Field Electric field
EM Electromagnetic
EW Electronic warfare
F-Band Electromagnetic spectrum band from 90 GHz to 140 GHz
xvi List of Abbreviations
FBW Fractional bandwidth

Fe Iron
FET Field-effect transistor
FMCW Frequency modulated continuous wave
FoM Figure of merit
Fraunhofer IAF Fraunhofer Institute for Applied Solid State Physics
FSPL Free-space path loss
G-Band Electromagnetic spectrum band from 140 GHz to 220 GHz
GaAs Gallium arsenide
GaN Gallium nitride
H-Band Electromagnetic spectrum band from 220 GHz to 325 GHz
H-Field Magnetic field
HBT Heterojunction bipolar transistor
HEMT High-electron-mobility transistor
IMN Input matching network
InGaAs Indium gallium arsenide
InP Indium phosphide
ISMN Interstage matching network
JPL NASA Jet Propulsion Laboratory
k-factor Rollett’s stability factor
Ka-Band Electromagnetic spectrum band from 26.5 GHz to 40 GHz
KCL Kirchhoff’s current law
KVL Kirchhoff’s voltage law
LNA Low-noise amplifier
LRRM Line-reflect-reflect-match
MAG Maximum available gain
MESFET Metal-semiconductor field-effect transistor
MET1 First metal layer
METG Galvanic metal layer
mHEMT Metamorphic high-electron-mobility transistor
MIM Metal-insulator-metal
ML Mismatch loss
mm-Wave Millimeter-wave frequencies (30 GHz–300 GHz)
MMIC Monolithic microwave integrated circuit
MN Matching network
MOCVD Metal-organic chemical vapour deposition
MSG Maximum stable gain
List of Abbreviations xvii
MSL Microstrip line

NiCr Nickel chromium
nid Not-intentionally doped
NR New radio
OMN Output matching network
PA Power amplifier
PAE Power-added efficiency
PDK Process design kit
pHEMT Pseudomorphic high-electron-mobility transistor
PtAu Platinum gold
Q-Band Electromagnetic spectrum band from 33 GHz to 50 GHz
RF Radio frequency
RL Return loss
Rx Receiver
S-Parameters Scattering parameters
SAR Synthetic aperture radar
Si Silicon
SiC Silicon carbide
SiGe Silicon germanium
SiN Silicon nitride
SWOT Strengths, weaknesses, opportunities, and threats
TE Transverse electric
TEM Transverse electromagnetic
TGW Total gate width
TL Transmission line
TM Transverse magnetic
Tx Transmitter
U-Band Electromagnetic spectrum band from 40 GHz to 60 GHz
UGW Unit gate width
V-Band Electromagnetic spectrum band from 50 GHz to 75 GHz
VNA Vector network analyzer
W-Band Electromagnetic spectrum band from 75 GHz to 110 GHz
WLAN Wireless local area network
Y-Parameters Admittance parameters
xix
List of Symbols
Attenuation constant
Current gain
Reflection coefficient
Skin depth
" Electromagnetic permittivity
Damping factor
Wavelength
=4 Quarter-wavelength
Electromagnetic permeability
Electrical conductivity
Time delay
! Angular frequency
AV Voltage gain
Aeff Effective aperture
c Wave propagation velocity
Cds Drain-source capacitance
Cgd Gate-drain capacitance
Cgs Gate-source capacitance
EC Conduction band energy
EF Fermi level
Ecrit Critical electric field
fmax Maximum frequency of oscillation
fT Current-gain cutoff frequency
GG Spacing between the topside ground planes of a coplanar waveguide
GA Available gain
GP Power gain
GT Transducer gain
Gant Antenna gain
gds Small-signal drain-source conductance
gm Small-signal transconductance
xx List of Symbols
h Substrate thickness
h21 Short-circuit current gain
ID Drain current
Ji Bessel function of the i th order
LGD Gate-drain spacing
LGS Gate-source spacing
LG Gate length
N i Neumann function of the i th order
ns Sheet charge density
Pin Input power
Pout Output power
Q Quality factor
q Elementary charge
R S Surface resistivity
Rc Contact resistance
Ron On-state resistance
Rsh Sheet resistance
rds Small-signal drain-source resistance
rgd Small-signal gate-drain resistance
rgs Small-signal gate-source resistance
Sx
p
Relative sensitivity of the parameter p to element x
S11 Input reflection coefficient
S12 Reverse transmission coefficient
S21 Forward transmission coefficient
S22 Output reflection coefficient
t Conductor thickness
U Unilateral power gain (Mason’s invariant)
VV Via spacing
VDS Drain-source voltage
VD Drain voltage
VGS Gate-source voltage
veff Effective carrier velocity
Z0 Characteristic impedance
1
1 Introduction
1.1 Motivation
The ever-growing demand of the modern society for wireless connectivity systems with
higher data rates and radar imaging systems of finer resolution drives the steady ascent of
the frequencies at which these microwave systems operate. For instance, it is predicted
that the W-band (75–110 GHz) will become the main radar frequency operation region
within the next years, which is driven by automotive and defense market segments [1, 2].
Furthermore, emerging wireless communication network standards, such as 5G and 6G,
as well as communication link applications based on satellite constellations induce a
substantial propelling force towards developing millimeter-wave systems [2–4].
This poses an increasing need on the semiconductor industry for providing components
able to deliver high output powers at high frequencies. Power amplifiers, which operate
within the millimeter-wave part (30–300 GHz) of the electromagnetic spectrum and are
able to provide a combination of high output power levels over broad bandwidths are a
vital driving force of emerging wireless communication and imaging systems.
The power amplifier (PA) is an essential component of many microwave systems. It is
usually located in the last stage of a transmitter chain and drives directly the load, such
as the antenna. Hence, the quality of the power amplifier has often a decisive influence
on the overall system’s performance in the terms of output power, efficiency, bandwidth,
and linearity.
It is also not unusual for the power amplifier to be the most expensive component of the
system [5]. Moreover, it has oftentimes also the leading impact on the size, weight, and
the DC power consumption of the subsystem. The high power dissipation during the
operation of the PA significantly increases the device’s temperature. Hence, the power
amplifier is likely the most important contributor to the thermal budget of the system
and thus dominates the overall system’s long-term reliability [5].
Early microwave amplifiers were based exclusively on vacuum tubes [6, 7]. However,
nowadays the field is dominated by power amplifiers developed using solid-state transis-
tors, and are often realized as single-chip monolithic microwave integrated circuit (MMIC)
solutions [6]. Some of the major benefits of amplifiers based on transistors over vacuum
tubes are smaller size, lighter weight, higher reliability, high level of multi-functional
integration, high-volume and high-yield production capability, lower bias voltages, and
reduced maintenance effort [6].
As the operating frequency of power amplifiers increases into the millimeter-wave region,
the size of the devices and their power handling capability have to be down-scaled [8].
Both commercial and defense millimeter-wave applications continue to push the power
and bandwidth limitations of power transistors. Upper frequency performance boundaries
2 1 Introduction
are inversely proportional to the parasitic effects of the device. The parasitic capacitances
become the limiting factor, and these capacitances accumulate as multiple devices are
added in parallel to achieve higher powers [9]. At some point, it is no longer possible to
continue to add more gate periphery without impacting the operational bandwidth [10].
Moreover, increasing the gate periphery is further restricted by aforementioned thermal
management considerations [5] and the current-handling capacity of the on-chip inter-
connections [6].
The aforementioned application segments will benefit from power amplifier components
that combine high output power, broad operation bandwidth, and a compact form factor.
As explained in the following chapter, the gallium nitride (GaN) high-electron-mobility
transistor (HEMT) technology appears as an appealing candidate for supporting these
applications with its unique combination of simultaneous high-voltage and high-frequency
operation. Thanks to these properties, power amplifiers based on GaN transistors have
demonstrated so far superior output power levels up to about 100 GHz.
However, despite the rapid advance in GaN HEMT technology [11–14], the reported
available gain of the devices is still limited at higher millimeter-wave (mm-wave) frequen-
cies in comparison to the competing high-speed semiconductor processes, such as indium
gallium arsenide (InGaAs) metamorphic HEMT (mHEMT) [15], indium phosphide (InP)
HEMT [16], InP heterojunction bipolar transistor (HBT) [17], silicon germanium (SiGe)
HBT [18, 19], or silicon (Si) complementary metal-oxide semiconductor (CMOS) [20].
This is one of the main reasons why only few GaN amplifiers operating above 100 GHz
have been reported so far [21–26].
1.2 Objectives and Organization of the Thesis

This thesis investigates several approaches to enhance the performance of GaN-based
circuits operating within the millimeter-wave spectrum. The main aim of this work is
to provide a set of design approaches and techniques to enable broadband operation of
mm-wave GaN power amplifier MMICs, with a particular focus on frequencies close to
and beyond the 100-GHz mark.
In order to evaluate the attainability of the above-stated goal of this work, one can
investigate the subject matter using business strategy tools, such as the SWOT analy-
sis [27], where the relevant strengths, weaknesses, opportunities, and threats of the
particular problem are identified. From a fundamental point of view, applying this
method to the objective tackled in this work leads to decomposing into individual SWOT-
elements the essential question set behind this thesis, that is, Can GaN HEMT tech-
nology be a well-suited candidate for high-performance power amplifiers operating at
upper millimeter-wave frequency bands? How can this be achieved? The individual key
SWOT-components helpful in addressing the above question can be identified as follows.
Strength: Output power density. As already mentioned above and as will be discussed
in Section 2.2, the unique combination of physical properties of GaN-based
material systems makes transistors employing this semiconductor technol-
ogy attractive for high-power mm-wave amplifiers due to the high power
densities offered by the devices. As a result, power amplifiers based on
1.2 Objectives and Organization of the Thesis 3
GaN transistors have demonstrated so far output power levels up to about

100 GHz superior to any other semiconductor technology.
Weakness: High-frequency gain of the transistors. When approaching operation at
100 GHz and beyond, the gain available from GaN HEMTs is lacking when
compared with some other high-speed semiconductor processes, such us
the ones based on InP or SiGe material systems. On the one hand, this
lack of gain is can be currently attributed to the relatively low maturity of
the mm-wave GaN technologies [11–14]. On the other hand, the compara-
tively high output impedance levels presented by GaN HEMTs increase the
influence of the parasitic feedback capacitance [28], which has a negative
impact on the available gain from the device. This results in operating near
or beyond the transistor’s transit frequency with a significantly reduced gain
margin, which implies several constrains on the designer in terms of the
feasible power combining complexity as well as balancing the impedance
matching targets between the small- and large-signal performance.
Opportunity: Circuit gain enhancement on individual design levels. In order to transfer
the primary strength of GaN HEMTs (i.e., high output power density)
towards operation at higher mm-wave bands, one has to overcome the
predominant weakness, that is, the relatively low gain of the transistors at
frequencies near and beyond the 100-GHz mark. Therefore, this thesis is
oriented around developing techniques and approaches for enhancing the
high-frequency circuit gain of GaN MMICs on distinct design levels, which
is identified as the primary opportunity of achieving the aforesaid goal. The
particular approaches employed in this work are summarized and presented
in more detail in the following part of this section, where the outline of the
thesis is described.
Threat: Technology scaling limitations. Even the most promising circuit design
cannot operate beyond the limits set by the technology. For an amplifier
design, the most relevant figure of merit is the maximum frequency of os-
cillation (fmax ), which is theoretically the absolute frequency limit at which
the transistor is able to provide any power gain. In practical circuits, this
frequency boundary cannot be achieved due to the incorporated mismatch
and dissipative losses. Moreover, mm-wave power amplifiers require a cer-
tain level of circuit complexity to fulfill the given specifications, including
combining and cascading several transistor stages. Therefore, in order to
accomplish the objectives of this thesis, one has to have an access to a
GaN HEMT technology that offers sufficiently high fmax values in combi-
nation with an adequate yield and homogeneity of the single devices to
realize complex amplifier circuits. However, it has to be noted that the
technology development activities are beyond the scope of this thesis.
As has been already mentioned, this thesis is oriented around exploiting the above-
identified opportunity, that is, developing techniques and approaches for enhancing the
high-frequency circuit gain of GaN MMICs on distinct design levels. Here, this objective
is followed with a three-fold design level segmentation:
4 1 Introduction
• Circuit level: Designing matching and biasing passive network allowing for broad-
band amplifiers and with reduced dissipative loss as well as developing scaled passive
networks supporting operation at frequencies beyond 200 GHz.
• Topology level: Implementing mm-wave power amplifier circuits employing ad-
vanced transistor topologies beyond the conventionally utilized common-source.
• Transistor layout level: Investigating the influence of the transistor’s layout and
dimensioning on its high frequency gain.
The above concepts are studied in detail in Chapters 3 to 5. Moreover, these concepts
are also implemented on circuit level resulting in MMICs providing state-of-the-art per-
formance among GaN-based power amplifiers. The body of this thesis is organized as
follows.
Chapter 2 highlights the necessity of developing power amplifiers operating within the
millimeter-wave spectrum and discusses whether GaN can be the technology of choice
for supporting these efforts. Furthermore, this chapter provides an overview of the state
of the art millimeter-wave power amplifiers and presents in detail the Fraunhofer IAF
100-nm GaN HEMT process utilized in the experimental part of this work.
In Chapter 3, several aspects regarding the design of passive networks in application for
mm-wave GaN power amplifiers are discussed. In particular, the main focus is put on
optimizing the bandwidth performance of two key passive parts of any active MMIC,
namely the matching and DC-biasing networks. Matching network design has, besides
the capabilities of the active devices, a decisive impact on the overall performance of the
circuit. The optimal matching network design by incorporating low-impedance transmis-
sion lines can push the circuit’s bandwidth performance closer towards the theoretical
limits set by the Bode-Fano criterion and the often-necessary transformation of the real
part of the impedance. Furthermore, the amplifier’s bandwidth can also be enhanced by
improving the performance of the DC-bias networks. The radial stub has been identified
as a key element of such networks for mm-wave MMIC applications. In Section 3.2,
a novel topology approach to the radial stub with a superior bandwidth performance is
introduced.
Chapter 4 covers enhancing the performance of mm-wave GaN power amplifiers by em-
ploying different transistor topologies. In particular, the main focus is oriented here
around increasing the high-frequency gain of the amplifier with cascode configuration
and optimizing the bandwidth performance with an fT -doubler pair. The improved re-
verse isolation of the cascode results in a significantly higher maximum gain of this to-
pology when compared with the common-source configuration. Therefore, the cascode
topology appears as an appealing alternative for applications in GaN power amplifiers
operating at the higher mm-wave bands, where the available gain of GaN HEMTs is lim-
ited. Alternatively to the passive networks design considerations provided in Chapter 3,
a wideband performance can be achieved also by employing more advanced transistor
topologies, such as the fT -doubler, which enhances the current gain of transistors in the
utilized semiconductor process. However, applying this topology at mm-wave frequen-
cies is a challenging task due to the layout-induced parasitic effects that degrade the
high-frequency performance. In Section 4.2.3, an fT -doubler topology employing a novel
integrated layout based on GaN HEMTs is introduced. The compact approach described
1.2 Objectives and Organization of the Thesis 5
in this part of the thesis allows for minimizing the layout-induced parasitic effects, which
enables operation at high frequencies.
Chapter 5 analyzes several design approaches for enabling operation of GaN-based am-
plifiers at the G-band (140–220 GHz) and beyond. In particular, enhancing the high-
frequency gain on transistor level by optimizing the geometrical properties of an HEMT
device, as well as coplanar network scaling for enabling multi-stage amplifiers operating
beyond 200 GHz are investigated. One of the possible layout-based modifications of a
GaN HEMT with a pronounced effect on its high-frequency performance is optimizing the
gate-drain and gate-source spacings. Such modification impacts the effective parame-
ters of the transistor, which significantly influence the high-frequency gain, as analyzed in
Section 5.1.1 and experimentally verified in Section 5.1.2. Another attainable alternative
for improving the performance of high-frequency GaN circuits is proper dimensioning of
the transistors. Section 5.1.3 discusses GaN-specific output impedance aspects arising
from an increased operating voltage when compared to other high-speed semiconductor
technologies. Although implementing the design methods investigated in Section 5.1
can considerably enhance the high-frequency gain of GaN devices on transistor level,
many of such HEMT stages need to be cascaded in oder to obtain a practical circuit-
level gain. This brings scaling of the passive networks with the substrate thickness as a
crucial effort to support GaN circuits operating at higher mm-wave bands, as discussed
in Section 5.2.1. In amplifiers incorporating many gain stages, the interstage matching
network is the critical passive network, which often defines the overall performance of a
multi-stage MMIC in terms of its bandwidth, gain, and size. A novel compact interstage
network layout is proposed in Section 5.2.3, which allowed to advance the performance
of GaN-based circuits towards the terahertz frontier.
Finally, the thesis is concluded in Chapter 6. This chapter provides an overview of the
concepts discussed in the preceding chapters with highlighting the essential takeaways
emerging from this work from a millimeter-wave GaN power amplifier designer’s perspec-
tive. Furthermore, a summary of the results achieved within the scope of this dissertation
is presented, alongside with their impact on the state of the art.
7
2 Fundamentals of Gallium Nitride

Millimeter-Wave Power Amplifiers
2.1 Millimeter-Wave Frequencies

The millimeter-wave (mm-wave) spectrum is located between 30 GHz and 300 GHz,
where the free-space wavelength () spans from 10 mm to 1 mm, respectively. The spe-
cific atmospheric attenuation within this frequency range at an air pressure of 1013 hPa,
a temperature of 15 C, and a water vapor density of 7.5 g/m3 is plotted in Fig. 2.1
[29–31]. As can be seen, the atmospheric attenuation is steadily increasing with the
increasing operation frequency. Moreover, the mm-wave spectrum contains resonance
frequencies of water and oxygen molecules, at which a high attenuation of electromag-
netic wave propagation is observed. In between these resonance frequencies, there exist
so-called atmospheric windows with reduced propagation loss, which can be utilized by
a number of attractive applications.
The mm-wave part of the electromagnetic spectrum is allocated into several bands
[32, 33]. This allocation scheme is based on the frequency range at which electromag-
netic wave propagation can be supported by a particular dimension of a standard-type
rectangular waveguide [32]. The letter designation nomenclature has its origin in World
War II secret radar band classification [33]. The mm-wave waveguide band allocation is
summarized in Table 2.1 and marked in Fig. 2.2. Since the bands often overlap with each
100
H2O
H2O
Attenuation (dB/km)
O2
10
O2
1
H2O
0.1
20 30 50 75 100 150 200 300

Frequency (GHz)
Fig. 2.1. Specific atmospheric attenuation within the millimeter-wave spectrum at an air pressure of
1013 hPa, a temperature of 15 C, and a water vapor density of 7.5 g/m3 [29–31].
8 2 Fundamentals of Gallium Nitride Millimeter-Wave Power Amplifiers
Table 2.1. Millimeter-wave waveguide frequency bands [32, 33] with references to amplifiers designed in
this work that operate within the specified band.
Band designation Frequency range Amplifier examples in this work

Ka-band 26.5 GHz to 40 GHz Section 4.2.5
Q-band 33 GHz to 50 GHz Section 4.2.5
U-band 40 GHz to 60 GHz Section 4.2.5
V-band 50 GHz to 75 GHz Section 4.2.5
E-band 60 GHz to 90 GHz Sections 3.3 and 4.2.5
W-band 75 GHz to 110 GHz Section 3.3
F-band 90 GHz to 140 GHz Section 4.1.3
D-band 110 GHz to 170 GHz Section 4.1.3
G-band 140 GHz to 220 GHz Sections 5.1.4 and 5.2.4
H-band 220 GHz to 325 GHz Section 5.2.4
other, the graph is split into two parts for better clarity. Furthermore, Table 2.1 provides
references to amplifiers operating at the specified bands that were designed throughout
this thesis.
One of the primary applications of mm-wave frequencies are radar imaging systems. The
availability of high instantaneous bandwidths combined with the ability of the signals
at these frequencies to penetrate through smoke, fog, dust, and some non-metallic
objects enables all-weather and through-clothing high-resolution frequency modulated
continuous wave (FMCW) radars for demanding surveillance, security, material analysis,
and medical imaging applications [34–44]. An example result of an airborne synthetic
aperture radar (SAR) system operating near 94 GHz is shown in Fig. 2.3 [39]. Comparing
the images produced using a visible-spectrum camera and the SAR sensor, shown in
Ka U E F G H Q V W D
Attenuation (dB/km)
Attenuation (dB/km)
Frequency Frequency
(a) (b)
Fig. 2.2. Visual representation of the millimeter-wave waveguide bands. Due to an overlap between the
bands, the graph is split into two parts for better clarity. Letter designations after [32, 33].
2.1 Millimeter-Wave Frequencies 9
(a) (b) (c)
Fig. 2.3. Example of a W-band airborne imaging system [39]. (a) Aircraft platform. Images produced
using (b) a visible-spectrum camera and (c) a W-band SAR system. © Fraunhofer FHR.
Fig. 2.3(b) and Fig. 2.3(c), respectively, one can note that the SAR image provides an
adequate resolution for many applications, with the additional advantage that the image
quality does not profoundly depend on the weather and daytime (ambient illumination)
conditions.
Another important application field facilitated by mm-wave components are high-data-
rate wireless communication links [45–49]. Besides point-to-point radio links, the mm-
wave propagation is increasing its impact on modern cellular networks. For instance, the
24-30-GHz and 37-40-GHz frequency bands play a key role in supporting the introduction
of the 5G communication standard [50–52]. Moreover, frequencies from 43 GHz to
50 GHz and around 60 GHz are often utilized for satellite communication links [53, 54].
In addition, the increased propagation loss around 60 GHz due to resonance of oxygen
molecules offers a possibility of establishing intrinsically secure wireless links (“whisper
radio”) with high data throughputs, mainly for indoor applications [55]. This feature is
utilized by short-range high-speed wireless local area network (WLAN) systems [55].
Furthermore, the next-generation mobile communication standards (6G and beyond)
are projected to profoundly rely on components operating above 100 GHz [52, 56–63].
Intuitively, one can assume that increasing the carrier frequency of the wireless link will
lead inevitably to a significant increase of the channel loss. However, this is true only
in a scenario where both the transmitter (Tx) and receiver (Rx) ends of the link are
omnidirectional [57].
The equation for evaluating the free-space path loss (FSPL) of a wireless link was de-
veloped by Harald Friis [64] and has the following form:

FSPL (2.1)
ant Rx ant Tx
where is the distance between the Tx and Rx link ends, is the operating wavelength,
whereas antTx and antRx are the antenna gains of the transmitter and receiver ends,
respectively. As can be seen from examining (2.1), the FSPL value is increasing quadrat-
ically with the increasing frequency of operation, given that the distance between the Tx
and Rx as well as their antenna gains are fixed. This relation is illustrated in in Fig. 2.4(a),
where the FSPL is plotted as a function of the distance between the link ends for three
carrier frequency cases (35 GHz, 70 GHz, and 140 GHz) in a scenario where both link
ends are omnidirectional ( antTx antRx ) [57, 58].
140 100
130 90
Free-space path loss (dB)
Free-space path loss (dB)

120 80
110 70
100 60
90 35 GHz 50 35 GHz
70 GHz 70 GHz
80 40
140 GHz 140 GHz
70 30
60 20
1 10 100 1000 1 10 100 1000
Distance (m) Distance (m)
(a) (b)
Fig. 2.4. Theoretical Friis’ free-space path loss for mm-wave wireless links [57, 58]. (a) Scenario where
both Tx and Rx are omnidirectional. (b) Scenario where both Tx and Rx have directional
antennas with an fixed effective aperture size of 1 cm2 .
The antenna gain (Gant ) depends on the effective aperture (Aeff ) of the antenna, which
is directly proportional to its physical size, as well as on the operating wavelength and is
given as [65]
Gant =
4Aeff : (2.2)
2
For instance, a directional antenna with an fixed effective aperture of 1 cm2 shows the-
oretically an antenna gain of 12.3 dBi, 18.4 dBi, and 24.4 dBi when operated at 35 GHz,
70 GHz, and 140 GHz, respectively. Provided that the physical dimensions of the an-
tenna are kept constant, the antenna gain is increasing in a quadratic manner with the
increasing carrier frequency of the link.
Therefore, after inserting (2.2) into (2.1) it can be concluded that by utilizing a di-
rectional antenna with a fixed effective aperture at one of the ends of the link, the
theoretical FSPL value given by (2.1) can be made insensitive to the carrier frequency of
the link [57]. What is more, by implementing two such antennas at both ends of the link,
the path loss decreases quadratically with the increasing frequency of operation [57].
Hence, employing highly directional and steerable antennas should enable wireless com-
munication links operating at higher frequencies, which should provide wider channel
bandwidth (and thus higher data throughput) without the penalty of an significantly
deteriorated signal-to-noise ratio due to atmosphere-induced attenuation (see Fig. 2.1)
when compared with systems utilizing lower carrier frequencies [57].
Another application of power amplifiers operating above 100 GHz is driving diode-based
multiplier chains in order to establish terahertz power sources [66]. Using high-frequency
driving amplifiers with enough output power allows for reducing the number of multiplying
stages necessary to achieve the target frequency, and thus improves the size, DC power
budget, and efficiency of the complete system.
Moreover, the G-band includes a water vapor line which has its peak absorption at
183 GHz, as indicated in Fig. 2.1. This characteristic is exploited in Earth and planetary
scientific instrumentation, such as remote humidity sensing [67].
2.2 Gallium Nitride for High-Frequency Applications 11
2.2 Gallium Nitride for High-Frequency Applications
Since the early 1990s, when the first gallium nitride (GaN) high-electron-mobility tran-
sistor (HEMT) was demonstrated [68, 69], GaN is considered as an excellent candidate
for the next-generation semiconductor material for high-power and high-frequency tran-
sistors [9]. This is based on the unique combination of the material properties that is
offered by GaN. These properties are collected and compared to other high-speed semi-
conductor technologies in Table 2.2 and are also summarized visually in form of a radar
plot in Fig. 2.5 [70].
On the one hand, GaN offers a relatively high electron mobility and saturated electron
velocity, with values inferior only to the ones achievable with advanced material sys-
tems based on indium phosphide (InP), gallium arsenide (GaAs), and silicon germanium
(SiGe) [71–73]. Therefore, one can expect that the high-frequency figures of merit,
such as current-gain cutoff frequency (fT ) or maximum frequency of oscillation (fmax ),
of GaN-based transistors will enable amplifiers operating within the mm-wave spectrum.
On the other hand, GaN provides some very favorable material features for high-power
applications, namely a high energy gap, a high breakdown field strength, and relatively
good thermal conductivity. These properties allow GaN transistors to operate under high
bias voltages and thus deliver remarkable output power densities [74, 75].
Furthermore, the lack of a mature bulk GaN source material led to the need for growing
the GaN heterostructures on mismatched carrier substrates, such as sapphire, silicon
carbide (SiC), or silicon (Si) [9]. Among these, SiC is the primary substrate material
choice for high-power and high-frequency applications due to its excellent thermal con-
ductivity (Table 2.2), a relatively low lattice mismatch to GaN, and its semi-insulating
properties [76].
However, the material parameter combination offered by GaN is highly attractive not
only for power amplifier MMICs, but also for other transceiver building blocks, such as
switches [77–79], phase shifters [79, 80], mixers [23], and low-noise amplifiers (LNAs)
[26, 81–83]. Even though it may be difficult to develop, for instance, a GaN-based
LNA with a noise-figure performance matching its InP or GaAs counterparts due to
their superb noise properties, the high-voltage-handling capability of GaN HEMTs allows
for realizing mm-wave circuits that can tolerate high input power levels, even beyond
1 W [26, 77, 79]. As a result of its superior robustness, the limiter or circulator could
Table 2.2. Selected material properties of semiconductors used in mm-wave applications [71–73].
Material parameter GaN GaAs InP Si SiGe SiC

Energy gap (eV) 3.4 1.4 1.3 1.1 0.9 3.3
Electron mobility*(cm2 =V s) 2 000 8 500 12 000 1 350 7 700 900
Saturation velocity (107 cm=s) 2.5 1 3.3 1 1.3 2
Breakdown field (MV=cm) 3.3 0.4 0.5 0.3 0.25 3
Thermal conductivity (W=cm K) 2 0.5 0.7 1.3 0.11 4.9
Dielectric constant 9.5 13 12.5 12 13.5 9.8
* Measured on respective transistor structures [71]
Breakdown field (MV/cm)

4 GaN GaAs
Hig Si SiGe
3 hv
olta InP
ge
2
Saturation 4 4
3 3 Energy gap
velocity 2 1 2
( 107 cm/s)
freque 1 1 (eV)
rature
Highncy
tempHe igh
3 0.5
6 1.0
9 1.5
Electron Thermal
mobility 12 2.0 conductivity
( 10 cm2/V×s)
3
(W/cm ×K)
Fig. 2.5. Comparison of selected material properties of semiconductors used in mm-wave

applications [70].
be potentially removed from the receiver chain, driving down the overall cost, volume
and weight of the system [26]. Moreover, due the high power density enabled by the
technology, gallium nitride mm-wave MMICs can provide good linearity, having the 1-dB
compression point well above 10 dBm [23, 26, 79, 82].
However, despite the rapid advance in GaN HEMT technology [11–14], the reported
available gain of the devices is still limited at higher mm-wave frequencies in comparison
to the competing high-speed semiconductor processes, such as indium gallium arsenide
(InGaAs) mHEMT [15], InP HEMT [16], InP HBT [17], SiGe HBT [18, 19], or Si
CMOS [20]. For instance, the 250-nm InP HBT process from Teledyne [17], which is the
foundation technology for state-of-the-art power amplifiers operating beyond 100 GHz
(see Fig. 2.7 in Section 2.3), provides an fT > 400 GHz and an fmax > 650 GHz. Thanks
to the high gain offered by the process within the mm-wave spectrum, a large number
of transistors could be combined on-chip in the output stage, and thus high absolute
output power levels can be achieved.
The amplifiers developed throughout this thesis employ the Fraunhofer IAF 100-nm GaN
HEMT process, which is described in more detail in Section 2.4. This process can provide
transistors with an fT above 100 GHz and an fmax of approximately 300 GHz. Thus,
employing this technology for power amplifiers targeting frequencies beyond 100 GHz
leads to operating already above the fT of the process.
Operating near or beyond the transistor’s fT leads to significantly lower gain margin in
the design budget, which implies several constrains on the designer. For instance, instead
of following the classical power amplifier design flow, that is, matching the device for
optimum large-signal swing of the voltage and current waveforms at the transistor’s
reference plane [84], one has to re-focus the design goals more towards gain optimization.
This is a necessary measure in order to take advantage of the exceptional power densities
offered by GaN HEMTs at mm-wave frequencies. Several design considerations for
increasing the high-frequency gain of GaN-based circuits are described in the following
chapters.
2.3 Overview of State-of-the-Art Millimeter-Wave Power Amplifiers 13
45
GaN SiGe GaAs
40
InP CMOS
Output Power (dBm)

35
30
25
20
15
10
5
0
30 50 75 100 150 200 300
Frequency (GHz)
Fig. 2.6. State-of-the-art overview of mm-wave power amplifiers as of September 2016. Based on the
data collected in [85]. InGaAs mHEMT amplifiers are categorized under GaAs.
2.3 Overview of State-of-the-Art Millimeter-Wave

Power Amplifiers
An overview of the state-of-the-art mm-wave power amplifiers based on the data col-
lected in [85] is depicted in Fig. 2.6 and Fig. 2.7. The data points shown in Fig. 2.6
include only works published up to September 2016, which is the starting date of this
thesis, whereas the chart from Fig. 2.7 provides an up-to-date overview and also includes
the results presented in this work.
One can note that the data points are to some extent congested around particular
frequencies rather than distributed evenly over the mm-wave spectrum. This is of course
caused by the specific frequency allocation for various applications that drive the research
efforts of the mm-wave power amplifier designer community.
For instance, a large group of results was published around 30 GHz. In this case, the
main driver can be related to the development need of circuits for handsets and the
infrastructure (e.g., base stations) supporting the introduction of the mm-wave 5G stan-
dard [50, 51]. In particular, the assigned 5G new radio (NR) bands are exploited, i.e.,
the n258 (24–28 GHz), n257 (26–30 GHz), and n260 (37–40 GHz) bands [50–52].
Another group of published works is concentrated from about 43 GHz to 50 GHz and
around 60 GHz. These frequencies can be associated with the Q/V-band satellite com-
munication links [53, 54]. Furthermore, the frequencies around 60 GHz are being also
used for short-range high-speed WLAN applications [55], where a plethora of CMOS-
based circuits has been reported.
The last “congested" frequency region seen in Fig. 2.6 lies between approximately 70 and
95 GHz, which contains a variety of possible applications. The frequencies around 77 GHz
45
GaN SiGe GaAs
40
InP CMOS This work
Output Power (dBm)

35
30
25
20
15
10
5
0
30 50 75 100 150 200 300
Frequency (GHz)
Fig. 2.7. State-of-the-art overview of mm-wave power amplifiers as of August 2021. Based on the data
collected in [85]. InGaAs mHEMT amplifiers are categorized under GaAs.
are utilized for automotive radar [86–88], whereas many imaging radar systems operate
near 94 GHz [36, 37, 41, 42]. The discussed frequency region includes also the licensed
E-band downlink (71–76 GHz) and uplink (81–86 GHz) frequency windows, which serve
for backhaul and point-to-point high-data-rate communication links [49, 89]. Finally,
frequencies around 94 GHz are also commonly used in electronic warfare (EW) sys-
tems [90, 91].
It can be further noticed that only a handful of results above 100 GHz were published
as of 2016 (Fig. 2.6). However, as can be seen from analyzing Fig. 2.7, a tremendous
progress was made in the last four years at the upper mm-wave bands, which is mainly
owed to the designs based on InP and, to less extent, on SiGe and InGaAs mHEMT.
The main drivers of this progress are the emerging next-generation 6G communication
systems [56–60] and scientific instruments [67]. Penetrating this frequency region also
with GaN-based amplifiers is one of the primary goals of this work.
Considering the output power levels gathered in Fig. 2.7, it can be concluded that GaN
power amplifiers are capable of delivering more than 10 W at the lower edge of the mm-
wave spectrum and more than 1 W at frequencies approaching to 100 GHz. This clearly
documents the advantage of utilizing GaN HEMT technology over other semiconduc-
tor processes in high-power mm-wave applications, such as base stations, point-to-point
radios, and electronic warfare systems. However, it has to be acknowledged that the
output power levels required by applications such as mobile handset radios and auto-
motive radars can be covered with lower-cost Si-based (CMOS, SiGe) or GaAs-based
technologies.
Direct and more detailed benchmarks of the particular results achieved in this thesis
against the state-of-the-art outcomes are provided in respective sections of this work,
where the measured performance of the developed amplifiers is discussed.
2.4 Millimeter-Wave GaN HEMT Technology 15
2.4 Millimeter-Wave GaN HEMT Technology
All of the circuits described within this thesis were developed and fabricated using the
Fraunhofer IAF deep submicron GaN HEMT technology targeting the higher mm-wave
bands [14].
A cross-section overview of the GaN HEMT structure with its calculated energy band
diagram is shown in Fig. 2.8. All of the active epitaxial layers are grown in-house by
metal-organic chemical vapour deposition (MOCVD) on 100-mm (4-inch) semi-insulating
4H-SiC substrates. The epitaxial stack of this technology comprises an aluminium gallium
nitride (AlGaN) barrier alloy with a thin aluminium nitride (AlN) interlayer to reduce the
alloy scattering and increase the two-dimensional electron gas (2DEG) mobility [92, 93].
The 2DEG is established near the interface of the AlN interlayer and the buffer layer,
where the conduction band energy ( ) lays below the Fermi level ( ), as plotted in
Fig. 2.8(b). The source and drain contact regions are implanted with Si in order to
create n-type ohmic layers and reduce the transistor’s contact resistance [94, 95].
Looking from top to bottom, the buffer structure contains a not-intentionally doped
(nid) GaN region followed by a GaN region doped with iron (Fe) [96]. The Fe-dopant
acts as a deep acceptor, which compensates the n-type background doping arising from
the impurities present during the MOCVD-growth of the nid-GaN layer [96], and thus
lead to an improved performance of the transistors in terms of their breakdown voltage,
leakage current, and short-channel effects [96–98].
The AlGaN/GaN-heterostructure is covered with a thin GaN-cap layer, which introduces
a polarization-induced enhancement of the effective Schottky barrier height that, in
effect, improves the electrical properties of the heterostructure [93, 99]. The epitaxial
stack is passivated with a silicon nitride (SiN) dielectric layer. In order to improve the
high-frequency performance of the HEMTs, the nitride deposition is optimized to reduce
the parasitic capacitances [100].
Most of the MMICs developed within the scope of this work is based on the above-
discussed AlGaN barrier alloy. Alternatively, also an AlN barrier can be applied. A
SiN
MET1 MET1
Gate
Ohm Metal Stack Ohm Metal Stack
GaN Cap
n+ Si-implantation AlGaN Barrier n+ Si-implantation
AlN Interlayer
2DEG
GaN Buer
AlN Nucleation
SiC Substrate
(a) (b)
Fig. 2.8. Fraunhofer IAF 100-nm AlGaN/GaN HEMT structure. (a) Technology cross-section (not to
scale). (b) Calculated energy band and electron density diagram.
MIM Capacitor
Airbridge
METG HEMT NiCr Resistor

MET1 MET1 MET1
SiN
Via Active HEMT layers
Substrate
Backside metalization
Fig. 2.9. Technology cross-section of the Fraunhofer IAF 100-nm GaN-on-SiC process (not to scale).
high aluminum content in the barrier alloy amplifies the spontaneous polarization and
piezoelectric effects in the GaN HEMT heterostructure, which results in a higher sheet
carrier density of the 2DEG [71, 101–103]. Therefore, lower sheet resistances of the
HEMT structure and thus greater output power densities on transistor level can be ex-
pected [71, 103]. However, growing sharp and well-behaved AlN/GaN interfaces using
MOCVD is a challenging task [104, 105]. Examples of high-frequency amplifiers incor-
porating an AlN barrier are provided in Section 5.2.4.
On top of the GaN cap layer, a platinum-gold (PtAu) T-shaped gate is defined by means
of electron-beam (e-beam) lithography and forms the Schottky junction. The PtAu
T-gate shows a good compromise between the high-frequency performance, threshold
voltage homogeneity, leakage characteristics, and long-term reliability of the resulting
HEMTs [106, 107]. The baseline gate length of the described process is 100 nm and this
variant has been applied in the majority of the circuits discussed in this work. However,
defining the gate structure with an e-beam lithography process offers some degree of
flexibility regarding the gate length. This feature was used in the 200-GHz amplifiers
discussed in Section 5.2.4, where scaled variants of the gate process with gate lengths
of 70 nm and 50 nm were utilized.
The resulting active devices demonstrate an extrinsic fT value of above 100 GHz and an
fmax beyond 300 GHz with good homogeneity over the wafer and over a broad range of
bias conditions, as shown in Fig. 5.14 and Fig. 5.15 in Section 5.1.2, respectively.
A cross-sectional overview (not to scale) of the complete MMIC process is sketched in
Fig. 2.9. The process provides metal-insulator-metal (MIM) capacitors with a capaci-
tance per area of about 0.25 fF/μm2 , 50-Ω/sq nickel-chromium (NiCr) thin-film resistors,
and two metal layers. The first metal layer (MET1) is deposited by means of evaporat-
ing an approximately 0.5-μm thick layer of gold (Au). The second metal layer (METG)
is realized with a galvanic deposition of Au, and serves for implementing the top-plate
metalization of the MIM capacitors and airbridge connections. It can be also directly
deposited on top of MET1 in order to develop the full-metal stack with a total thickness
of about 3 μm. As a final step, the SiC substrate is thinned to 75 μm and viaholes with
a size of 30 30-μm2 are produced.
2.5 Experimental Verification of the HEMT Model at the W-Band 17
1.0j
0.5j 2.0j
Nominal Circuit ZL (Ω) at 94 GHz
RL-Low Nominal 9:8 + j 19:9
0.2j RL-High 5.0j RL-Low 7:3 + j 20:1
XL-Low RL-High 16 + j 19:7
XL-High XL-Low 9:9 + j 15:8
0.2 0.5 1.0 2.0 5.0 XL-High 10 + j 21:7
Fig. 2.10. Location of the simulated load impedances presented to the single-stage test amplifiers’ tran-
sistors on a 50-Ω Smith chart with their corresponding values at 94 GHz.
2.5 Experimental Verification of the HEMT Model at

the W-Band
Most of the designs presented in this thesis were carried out using a small- and large-signal
GaN HEMT model developed in-house [108]. The bias-dependent intrinsic transistor is
described by means of a state-space approach, including the low-frequency dispersion
phenomena [109, 110]. The intrinsic HEMT is embedded in a fully-scalable parasitic
shell. The bias-dependent intrinsic parameters as well as the bias-independent extrinsic
parameters are extracted for a specific technology and epitaxy variant [111].
At W-band frequencies there is a limited access to commercial microwave characteriza-
tion tools, such as loadpull systems, which provide a significant aid to designing nonlinear
circuits [6, 84]. This aspect makes the modeling task more challenging. Therefore, reg-
ular monitoring of the active device behavior is critical for delivering a satisfying MMIC
performance already from the first design iterations.
In order to verify the used HEMT model, a set of five prematched single-stage test
amplifiers was designed. The main purpose of this experiment is to validate the large-
15 8 32
S11 S12 Meas. Pout Meas.
10 7 28
S21 S22 Sim. Gain Sim.
Pout (dBm), DE (%)
S-parameters (dB)
5 6 24
DE
0 5 20
Gain (dB)
-5 4 16
-10 3 12
-15 2 8
-20 1 4
-25 0 0
50 60 70 80 90 100 110 0 2 4 6 8 10 12 14 16 18 20
Frequency (GHz) Pin (dBm)
(a) (b) (c)
Fig. 2.11. Prematched test amplifier with the nominal ZL . (a) Chip photograph (1 0.75 mm2 ). (b) Mea-
sured (solid) and simulated (dashed) small-signal response. (c) Measured (solid) and simulated
(dashed) large-signal response at 94 GHz. VDS = 10 V and ID = 200 mA/mm.
15 8 32
10 7 28
Pout (dBm), DE (%)

S-parameters (dB)
5 6 24
DE
0 5 20
Gain (dB)
-5 4 16
-10 3 12
-15 2 8
-20 1 4
-25 0 0
50 60 70 80 90 100 110 0 2 4 6 8 10 12 14 16 18 20
(a) (b) (c)
Fig. 2.12. Prematched RL -Low test amplifier with a decreased real part (RL ) of the nominal ZL . (a) Chip
photograph (10.75 mm2 ). (b) Measured (solid) and simulated (dashed) small-signal response.
(c) Measured (solid) and simulated (dashed) large-signal response at 94 GHz. VDS = 10 V and
ID = 200 mA/mm.
signal load target prediction of the model around 94 GHz, which is approximately the
center frequency of the W-band.
The output matching network (OMN) of one amplifier was intended to provide a nominal
load impedance (ZL = RL + jXL ) predicted by the loadpull simulations, while OMNs of
the other four amplifiers were designed to provide ZL with varied real (RL ) and imaginary
(XL ) parts of the nominal load impedance. The values of the ZL for each amplifier
variant are gathered in a table and illustrated with a 50-Ω Smith chart in Fig. 2.10. The
above mentioned experiment could be thought of as an approach to mimic a mm-wave
frequency on-chip loadpull measurement. The HEMT in each prematched circuit is a
4 32:5-μm common-source (CS) device. The choice of the transistor size is based on
its simulated performance, where a good compromise between the small-signal gain and
the gain compression levels with the input power levels available from the measurement
setup was observed. The input matching network (IMN) is the same in case of all circuits.
The matching networks were designed using grounded coplanar waveguides (CPWs).
15 8 32
10 7 28
S-parameters (dB)
5 6 24
Pout (dBm), DE (%)
DE
0 5 20
Gain (dB)
-5 4 16
-10 3 12
-15 2 8
-20 1 4
-25 0 0
50 60 70 80 90 100 110 0 2 4 6 8 10 12 14 16 18 20
(a) (b) (c)
Fig. 2.13. Prematched RL -High test amplifier with an increased real part (RL ) of the nominal ZL . (a) Chip
photograph (10.75 mm2 ). (b) Measured (solid) and simulated (dashed) small-signal response.
(c) Measured (solid) and simulated (dashed) large-signal response at 94 GHz. VDS = 10 V and
ID = 200 mA/mm.
2.5 Experimental Verification of the HEMT Model at the W-Band 19
15 8 32
10 7 28
Pout (dBm), DE (%)

S-parameters (dB)
5 6 24
DE
0 5 20
Gain (dB)
-5 4 16
-10 3 12
-15 2 8
-20 1 4
-25 0 0
50 60 70 80 90 100 110 0 2 4 6 8 10 12 14 16 18 20
(a) (b) (c)
Fig. 2.14. Prematched XL -Low test amplifier with a decreased imaginary part (XL ) of the nominal ZL .
(a) Chip photograph (1 0.75 mm2 ). (b) Measured (solid) and simulated (dashed) small-
signal response. (c) Measured (solid) and simulated (dashed) large-signal response at 94 GHz.
VDS = 10 V and ID = 200 mA/mm.
Figure 2.11 shows, starting from the left, the photograph and the small- and large-signal
responses of the single-stage test amplifier with the nominal ZL . The corresponding
illustrations for the varied real (RL ) and imaginary (XL ) parts of the load impedance
are presented starting from Fig. 2.12 to Fig. 2.15. The S -parameters were measured
up to 110 GHz, while the power measurements were performed at 94 GHz. Due to the
relatively low gain of the single-stage amplifiers (about 5 dB), drain efficiency (DE) is
chosen to characterize the circuits instead of the power-added efficiency (PAE), as the
latter parameter is gain-dependent [6]. The quiescent bias conditions for each measure-
ment are VDS = 10 V and ID = 200 mA/mm. As can be seen, the measurement results
are in good agreement with the simulations. In general, the measured amplifiers enter
the compression later than predicted by the model. The measured large-signal results are
gathered in Table 2.3. Circuits with decreased real part (RL -Low) and increased imagi-
nary part (XL -High) of ZL perform better than the one with the nominal load impedance.
The RL -High and XL -Low amplifiers show an inferior performance. This could indicate
that the transistor’s loadline resistance is slightly overestimated, while the large-signal
15 8 32
10 7 28
Pout (dBm), DE (%)
S-parameters (dB)
5 6 DE 24
0 5 20
Gain (dB)
-5 4 16
-10 3 12
-15 2 8
-20 1 4
-25 0 0
50 60 70 80 90 100 110 0 2 4 6 8 10 12 14 16 18 20
(a) (b) (c)
Fig. 2.15. Prematched XL -High test amplifier with an increased imaginary part (XL ) of the nominal ZL .
(a) Chip photograph (1 0.75 mm2 ). (b) Measured (solid) and simulated (dashed) small-
signal response. (c) Measured (solid) and simulated (dashed) large-signal response at 94 GHz.
VDS = 10 V and ID = 200 mA/mm.
Table 2.3. Large-signal measurement results of the single-stage test amplifiers at 94 GHz.
Circuit Gain at Pin = 0 dBm Pout, max DEmax

Nominal 4.6 dB 22.1 dBm 27.5 %
RL -Low 5.0 dB 22.3 dBm 29.5 %
RL -High 4.5 dB 21.8 dBm 23.8 %
XL -Low 4.5 dB 21.5 dBm 22.3 %
XL -High 5.4 dB 22.3 dBm 29.5 %
output capacitance is underestimated by the model. This effect was considered during
the design of the power amplifiers described in the following chapters.
2.6 Conclusions on Chapter 2

This chapter highlighted the necessity of developing power amplifiers operating within the
millimeter-wave spectrum and discussed whether GaN can be the technology of choice
for supporting these efforts.
The operation frequency of power amplifiers is constantly increasing, which is driven by
the emerging radar, communication, and scientific applications described in Section 2.1.
The increasing frequency of operation is also accelerating the progress of high-speed
semiconductor MMIC technologies. The desired technology vehicle for mm-wave power
amplifiers must not only be able to operate at the frequencies of interest with a mean-
ingful gain, but also must be able to deliver significant output power therein.
Due to its unique combination of high breakdown voltage and high electron velocity,
amplifiers based on GaN HEMTs have dominated the state-of-the-art tables up to ap-
proximately 100 GHz (see Section 2.3), where there are able to offer more than a twofold
output power advantage over the competing semiconductor technologies. In the circuits
developed within this thesis, the Fraunhofer IAF submicron AlGaN/GaN HEMT technol-
ogy was employed with its features being described in detail in Section 2.4.
However, despite the continued improvement of GaN HEMT technology, the high-
frequency gain of the transistors still appears as the restraining factor in closing the
performance gap to other semiconductor processes above 100 GHz. Hence, employing
GaN technology for power amplifiers targeting higher mm-wave frequency bands leads
to operating near or already above the fT values provided by the transistors.
Moreover, at frequencies approaching 100 GHz there is a limited access to commercial
microwave characterization tools, such as loadpull systems, which provide a significant aid
to designing nonlinear circuits. This aspect makes matching the amplifiers design goals
a very challenging task due to modeling uncertainties. Therefore, regular monitoring of
the active device behavior is critical for delivering a satisfying MMIC performance already
from early design iterations. For instance, this can be achieved by means of developing
prematched test structures, as discussed in Section 2.5.
21
3 Passive Network Considerations for

Broadband GaN Power Amplifiers
In this chapter, several aspects regarding the design of passive networks used in PAs are
investigated. In particular, the main focus is placed on optimization of the bandwidth
performance of the two key types of passive sub-networks of any MMIC amplifier, i.e.,
the matching networks (MNs) and the networks responsible for providing the DC-bias to
the active devices.
The concepts provided in this chapter are found to be the crucial circuit-level improve-
ment factors that allow for development of millimeter-wave (mm-wave) PAs using GaN
HEMT technology with state-of-art performance. As an example, a design description
of the first-ever GaN-based PA that is able to cover the full W-band is included in the
conclusion of this chapter. This amplifier incorporates the key passive concepts discussed
here.
3.1 Broadband and Low-Loss Matching Networks

Matching networks are an essential part of any MMIC. Besides the characteristics of the
active devices, the matching network design plays usually a decisive role for the overall
circuit’s performance, especially in terms of the resulting bandwidth (BW) and consumed
chip area [6].
The primary function of a matching network is to transform the system impedance Z0
(usually 50 Ω) to a target impedance at the interface of the active device in order to
optimize one or more of its performance indicators, such as gain, output power, PAE, or
noise figure, over a specified frequency range [6]. Besides, the MN should also provide a
number of secondary but still essential functions, such as [6]
• incorporating power combing/dividing of multiple cells with an amplitude and phase
equalization between the parallelized cells;
• embodying a stabilization network for suppressing even-mode and odd-mode oscil-
lations;
• providing (an) injection point(s) for the DC-bias for the active devices (DC-bias
networks are discussed in Section 3.2) and simultaneously isolating different
DC-potentials;
• providing adequate filtering properties in order to shape the resulting gain response
and to hinder any out-of-band artifacts;
On top of supporting the aforementioned functions, several requirements have to be met
during the MN design, including realizability, low loss, and compactness [33].
22 3 Passive Network Considerations for Broadband GaN Power Amplifiers
3.1.1 The Broadband Impedance Matching Problem
Complex impedance matching, which is the usual case in mm-wave amplifier design, can
be seen from a two-way perspective. On the one hand, the real parts of the impedance
levels on both ends of the MN have to be matched using a proper transformation ratio
of the network. On the other hand, the reactance at each end of the MN has to be
compensated and/or absorbed by the network. Whilst the resistive transformation is
theoretically not a bandwidth-limiting factor [112], the maximum frequency range where
a reactance can be matched with a given reflection coefficient is limited by the so-called
Bode-Fano criterion [113, 114].
The Bode-Fano criterion specifies a theoretical benchmark of an achievable coefficient
magnitude for a certain impedance matching scenario over a given bandwidth. When
designing a power amplifier the usual matching scenarios shown in Fig. 3.1 occur [115].
It is important to note that, strictly speaking, the large-signal HEMT model presented
in Fig. 3.1 is not an exact physical representation of the transistor in large-signal ope-
ration regime, but rather a complex-conjugate of the desired impedances that should
be presented at the input and output terminals of the HEMT in order to maximize its
large-signal performance [6]. These impedances are equivalent to the voltage/current
ratios that are found to provide an optimum large-signal performance from a load-pull
experiment or simulation [6]. For the case of a HEMT device, the transistor’s input can
be represented as a series RC circuit (denoted later with Zin ), whereas the output port
can be described as a parallel RC connection (denoted later with Zout ) [6].
In reality, the network parameters representing the transistor in Fig. 3.1 are non-linear
and strongly dependent on the bias conditions as well as on the gain compression level [6].
However, this simplified and abstract representation of the HEMT should be still capable
of delivering an adequate level of depth in terms of illustration of the Bode-Fano limits.
Rsource
Input Output
Matching Matching Rload
Cin Rin Rout Cout
Fig. 3.1. Matching scenario for a single-stage power amplifier with a unilateral large-signal model of the
input and output impedances of a HEMT in a common-source configuration [115].
3.1 Broadband and Low-Loss Matching Networks 23
Bode-Fano Limit for Output Matching
As can be seen from the unilateral large-signal model of a HEMT in a CS configuration

provided in Fig. 3.1 and its aforementioned interpretation, the transistor’s input can be
described as series RC circuit, whereas the output port can be modeled as a parallel RC
connection. Starting with the output side, the Bode-Fano limit for matching a parallel
RC circuit is given as [6]
1
ln
1
j
d! < :
( ! )j RC (3.1)
0
By assuming that has a constant magnitude of j j = j max j within a desired band (from
! to ! ) and is unity elsewhere, (3.1) takes the following form [6]:
l h
h
:
!
ln
1
d! < RC (3.2)
max
! l
After solving (3.2) and substituting ! = 2f , the theoretically obtainable bandwidth for
the output matching scenario shown in Fig. 3.1 can be expressed as
BWmax,out = f< RoutCout

2
1
ln
: (3.3)
max,out
Alternatively, using the quality factor Q of the output load,

QL,out !0RoutCout;
= (3.4)
where
!0 =
p
!! h l (3.5)
is the center operating frequency, (3.3) can be rewritten as
BWmax,out = f < Q f0 : ln

(3.6)
L,out max,out
The experimental verification of the GaN HEMT model at the W-band, described in
Section 2.5, revealed that the output target impedance of a 4 32:5-μm HEMT in a
CS configuration resulting in a reasonable large-signal performance at 94 GHz is given
as Zout = 7:3 j 20:1 Ω. Converting this impedance into a parallel RC connection (see
Fig. 3.1) yields Rout = 62.6 Ω and Cout = 74.4 fF. Alternatively, Rout and Cout can be
expressed with respect to the device periphery (scalable form) as Rout = 8.14 Ω mm and
Cout = 0.57 pF/mm. These values can be substituted in (3.3) to evaluate the maximum
theoretical matching bandwidth for a given return loss. The return loss (RL) is related
to the reflection coefficient as [33]
RL = 20 logj j: (3.7)
For a reasonable return loss value of 10 dB, the maximum bandwidth over which this
transistor can be theoretically matched at its output is BWmax,out 93 GHz. The plot
of the theoretical maximum achievable output matching bandwidth for the aforesaid
4 32:5-μm HEMT versus the targeted return loss is provided in Fig. 3.2(a).
Bode-Fano Limit for Input Matching
The Bode-Fano limit for the input matching case of the HEMT from Fig. 3.1, that is, a
series RC connection, is described as [6]
1
! d! < !0 RC:

1
2
ln (3.8)
j ( )j
0
By following a similar procedure as for the output matching case, the maximum obtain-
able bandwidth with respect to the Bode-Fano criterion at the input side can be rewritten
as
BWmax,in = f< 2 2f02RinCin : (3.9)
ln max,in
Again, (3.9) can be rearranged using the quality factor Q of the input load to
BWmax,in = f < Q f0 ;ln
(3.10)
L,in max,in
where
QL,in =
f0RinCin :
2
1
(3.11)
Based on the numerical example given above for the output matching, a similar analysis
of the Bode-Fano input matching limit is performed. When the complex-conjugate of
the aforementioned target impedance Zout
(Section 2.5) is presented to the output port
of the HEMT, simulations show that the impedance that must be presented to the input
of the transistor in order to maximize the power transfer (complex-conjugate matching)
at 94 GHz is given as Zin = 3:0 + j 10:0 Ω. Therefore, the values of the series RC circuit
used for modeling the input of a HEMT in Fig. 3.1, for the case of a 4 32:5-μm device,
are Rin = 3 Ω and Cin = 169 fF.
It is important to note that, unlike for the Rout case, Rin is not inversely proportional to
the total gate width (TGW) [116]. Instead, it is a function of the device geometry, that
is, the width of the single gate finger and the number of parallelized fingers. Hence, the
Bode-Fano input matching limit depends on the chosen HEMT geometry, which is not
the case for the output port since Rout / 1 Cout [116]. The input capacitance Cin is
however proportional to the TGW, similarly as the Cout [116].
Substituting the experimentally extracted values of Rin and Cin to (3.9), the Bode-Fano
input matching limit can be evaluated numerically. Again, for a reasonable return loss
value of 10 dB around f0 = 94 GHz, the maximum bandwidth over which this transis-
tor can be theoretically matched at its input port is BWmax,in 77 GHz. Comparing
this result with the obtained BWmax,out , one can note that input matching is a more
bandwidth-limiting factor than the output matching, which is the usual case when de-
signing power amplifiers comprising GaN HEMTs [116].
300 120
275 110 Ka-band
250 100
Bode-Fano Limit (GHz)

Q-band
225 90
V-band
200 80
175 70 E-band
150 60 W-band
125 50
100 40
75 30
50 20
25 10
0 0
0 2 4 6 8 10 12 14 16 18 20 22 24 0 2 4 6 8 10 12 14 16 18 20 22 24
Output Return Loss (dB) Input Return Loss (dB)
(a) (b)
Fig. 3.2. Calculated Bode-Fano (a) output and (b) input matching limit for a 4 32:5-μm GaN HEMT
as a function of the targeted return loss. In case of the input matching limit (b), the f0 is chosen
as the center frequency of the five lower mm-wave waveguide bands. The symbols mark the
absolute bandwidth that is necessary for a complete coverage of the respective waveguide band.
Bode-Fano Criterion and a Full-Waveguide-Band Power Amplifier Design Case
Contrary to the output matching case [see Equation (3.3)], the Bode-Fano bandwidth
limit for the input matching [see Equation (3.9)] depends on the center operating fre-
quency, such that BWmax, in / f02 . This partially marks the necessity of pushing the circuit
development towards operating at higher frequencies, in particular at the mm-waves and
beyond, for applications where high instantaneous bandwidths are of great importance.
In order to illustrate the aforesaid demand for increasing the operating frequency of
broadband systems, a specific design case of a full-waveguide-band PA at the mm-wave
frequencies is discussed. A full-waveguide-band amplifier is a desired component in several
applications, for instance, in high-frequency measurement setups. In this example, the
five lower mm-wave waveguide bands are taken into consideration, namely: the Ka-band
(26.5–40 GHz), Q-band (33–50 GHz), V-band (50–75 GHz), E-band (60–90 GHz), and
the W-band (75–110 GHz). The 4 32:5-μm GaN HEMT mentioned above is used as
the device under test (DUT).
Figure 3.2(b) shows the Bode-Fano input matching limit calculated using (3.9), where
f0 is chosen as the center frequency of the respective waveguide bands listed above. The
symbol on each curve marks the instantaneous bandwidth that is necessary to completely
cover the given waveguide band. One can notice that the ideal-case input return loss
for matching this DUT over the complete Ka-band is 6.4 dB, whereas for the W-band
matching case the return loss is already 20.5 dB. In other words, for a given transistor,
the theoretical input matching quality is improved for full-band matching realized at
higher frequencies. In a practical sense, this means that the matching quality can be
traded for other performance indicators, such as lower loss or less-complex topology,
while still meeting the input return loss design specifications. This conclusion assumes
that the given transistor is able to provide sufficient gain also within the higher frequency
bands.
3.1.2 Importance of Using Low-Impedance Transmission Lines

As can be seen from the numerical examples provided in Section 3.1.1, the real part
of the input impedance (Rin ) of the GaN HEMTs intended to operate at mm-wave
frequencies is usually significantly lower than 50 Ω, which is a commonly used value for
the system impedance. Therefore, an up-transformation of the HEMT’s input impedance
is necessary.
In MMIC design at mm-wave frequencies, employing on-chip quarter-wavelength (=4)
transmission lines is a convenient and practical way of implementing the transformation
of the real part of an impedance [33]. However, the =4-transformation is limited in
terms of its bandwidth performance [33]. For the case of an up-transformation of the
impedance of a series RC circuit, the Q-factor is inevitably increased with regards to the
Q-factor of the input load QL,in [115], which has been already defined in (3.11). The
resulting QT of the transformation realized with a =4 transmission line is given as [115]

QT = QL,in + 4 r r ; 1
(3.12)

where r = Z0 Rin for Z0 > Rin is the ratio of the characteristic impedance Z0 of the
=4 transmission line to the real part of HEMT’s input impedance (see Fig. 3.1).
Evaluating (3.11) with the numerical values of Rin = 3 Ω and Cin = 169 fF provided in
Section 3.1.1 for a 4 32:5-μm GaN HEMT, results in QL,in = 3:45 at the center of the
W-band. The calculated Q-factor resulting from the =4-transformation from (3.12) is
plotted in Fig. 3.3(a) as function of the Z0 of the employed =4 line. As can be noticed,
using a transmission line with a Z0 of 20 Ω results already in a more than two-fold increase
of the Q-factor with respect to using an ideal transformer (i.e., not bandwidth-limited).
The impact of the Z0 of the =4 transformer on the Bode-Fano limit is evaluated by
substituting (3.12) into (3.10) [115]. The resulting input matching limit is shown in
Fig. 3.3(b) as function of the input return loss for several values of Z0 . It can be seen
that the achievable matching bandwidth is severely limited by the increasing Z0 .
The above analysis marks the importance of using low-impedance transmission lines for
matching the input of the mm-wave GaN HEMTs. By looking at (3.12) and Fig. 3.3, one
can conclude that the Z0 should be kept low, as close to Rin as possible [115]. However,
as will be discussed in Section 3.1.4, practical realization of very low-impedance microstrip
lines in modern MMIC processes is challenging and comes along with introducing several
undesired effects.
In case that employing low-impedance lines is impractical, an alternative solution to
minimize the QT is to lower the Z0 Rin ratio by increasing the Rin of the HEMT. It can
be done by modifying the geometry of the used transistor, for instance, by reducing the
number of parallel gate fingers. Changing the HEMT’s layout from a four-finger to a
two-finger geometry will result in an approximately two-fold increase of the Rin and an
approximately two-fold decrease of the Cin , which will keep the QL,in constant. However,
making the transistor smaller will result in less available Pout , which can be necessary to
drive the following stage in large-signal operation. Moreover, very small HEMTs realized
in high-voltage technologies (such as GaN) can also be very challenging to match at
their output side, which will be addressed in more detail in Section 5.1.3. It can be also
noted that matching the input of the HEMTs localized in the last stage of the PA is
20 120
18 110 Characteristic Impedance

Quality Factor QT (-)
16 100 3W 20 W
90 5W 30 W
14
80 10 W 50 W
12 70
10 60
8 50
6 40
30
4
20
2 10
0 0
0 5 10 15 20 25 30 35 40 45 50 0 2 4 6 8 10 12 14 16 18 20 22 24
Characteristic Impedance ( W) Input Return Loss (dB)
(a) (b)
Fig. 3.3. Impact of the characteristic impedance of the =4-transformer on the Q-factor and Bode-
Fano limit of input matching of a 4 32:5-μm GaN HEMT. (a) Calculated Q-factor of the
resulting =4-transformation as a function of the characteristic impedance of the transformer.
(b) Calculated Bode-Fano input matching limit as a function of the targeted return loss for
different values of the characteristic impedance of the =4-transformer. f0 is chosen as the
center frequency of the W-band.
usually the key bandwidth-limiting factor [115], since the TGW of the output stage is
usually the largest in order to provide the required amount of Pout .
Another possible choice to raise the Rin without decreasing the Pout is to increase the
unit gate width of the finger. However, this will have a negative effect on the gain of
the HEMT, which tends to be limited at high-frequencies, due to an increased gate-line
resistance and can result in a necessity of using more stages in the amplifier. Additionally,
increasing the unit gate width can deteriorate the high-frequency performance of the
transistor due to some distributed effects, such as gate propagation delay [115], when
the effective electrical length of the gate width approaches a significant fraction of the
operating wavelength (). Alternatively, other topologies beyond the common source
can be used to raise the Rin as, for instance, the fT -doubler discussed in Section 4.2.
3.1.3 Low-Loss Matching Networks

Low-loss matching network design is one of the key measures taken to utilize the full
potential of the transistors used as power generators. It is especially crucial for the OMN,
however too lossy IMNs and interstage matching networks (ISMNs) are also not desirable
in a power amplifier design, as they deteriorate the gain which could prevent driving the
following stage(s) into saturation.
The total loss of a MN can be expressed as the sum of its mismatch loss (ML) and
dissipative loss (DL) [6]. The mismatch loss (in dB) is given by [6]
1
; ML = 10 log
1 j j2
(3.13)
where is the reflection coefficient arising from the mismatch between the impedance
ZHEMT that should be presented to the input or output terminal of the HEMT for opti-
Rsource
Input Output
Matching Matching Rload
S21i S21o
S22i S11o
Fig. 3.4. Matching scenario representation for evaluation of the dissipative loss of the input and output
matching networks [6].
mum performance and the impedance ZMN that is seen looking towards the respective
input or output matching network [6]. This reflection coefficient is then calculated as [6]
= ZZMN + ZZHEMT : (3.14)

MN HEMT
The dissipative losses can be evaluated by considering a modified view of the matching
scenario shown in Fig. 3.4 and examining the S -parameters of the input and output MNs.
The DL of the input matching network is given as [6]
= 10 log 1 j j21 j j2
S
2
i
DLIMN ; (3.15)
22S i
whereas the DL of the output matching network can be expressed in an analogous form
as [6]
= 10 log 1 j j21 j j2
S
2
o
DLOMN : (3.16)
11S o
Despite the rapid advance of the GaN HEMT technology, the gain of the transistors
at the higher mm-wave bands is still rather limited. Therefore, preserving the gain on
circuit level by reducing the loss of the MNs is one of the very few enablers to fully utilize
one of the greatest potentials of GaN, that is, very high Pout densities.
3.1.4 Low-Impedance and Low-Loss Microstrip Lines

In the preceding sections (3.1.2 and 3.1.3), the necessity of employing low-impedance
and low-loss matching networks in to order to develop high-performance mm-wave power
amplifiers has been discussed. However, one aspect that needs to be still addressed is
how to practically implement such networks on MMIC level.
In the mm-wave MMIC design community, microstrip is, besides the CPW, one of the
common technology choices for realizing planar passive networks. Cross-sectional views
of both of the transmission line realizations are shown in Fig. 3.5. The electric field
(E-field) and the magnetic field (H-field) lines in Fig. 3.5 are shown for the quasi-static
transverse electromagnetic (TEM) propagation mode, which is the dominant case when
the substrate is much thinner than the operating wavelength [33]. The microstrip line
(MSL) technology is a popular choice among MMIC designers since it provides a pos-
sibility of very compact routing, and there exists a vast range of reliable closed-form
simulation models in commercial computer-aided design (CAD) software packages [117].
E-Field E-Field
H-Field H-Field
S
S G S G
Via Via
Backside Ground Backside Ground

(a) (b)
Fig. 3.5. Cross-sectional view of the (a) microstrip and (b) grounded coplanar waveguide transmission
lines with an illustrative distribution of the electric and magnetic fields of the respective quasi-
TEM modes [118].
Characteristic Impedance of a Microstrip Line
The characteristic impedance of an MSL can be calculated based on the line width w
and substrate thickness h as [119, 120]
⎧
60 8h w
⎪ p
⎨ " ln w + 4h ;
⎪ w h
Z0 =⎪ e 120
(3.17)
⎪
⎩ p
"e w=h + 1:393 + 0:667 ln(w=h + 1:444)
; w >h
where the effective dielectric constant "e is related to the dielectric constant of the
substrate material "r by [119, 120]
"r + 1 "r 1 1
"e = + : (3.18)
2 2 1 + 12h=w
This model assumes, however, that the substrate material is non-dispersive, that is, the
relative dielectric constant does not depend on the operation frequency. The character-
istic impedance is plotted in Fig. 3.6(a) as a function of the line width for the substrate
parameters of the MMIC technology used in this work, i.e., h = 75 μm and "r = 9:7.
One can note that realizing low-impedance MSLs in the used technology requires very
wide line widths. For instance, implementing a microstrip line of Z0 20 Ω requires
a line width above 300 μm, which can be considered already as approximately =4 at
100 GHz in a SiC substrate.
Loss Evaluation of a Microstrip Line
The attenuation of an RF signal propagating in a microstrip line occurs inevitably and

can be expressed as a sum of two dominant effects [6]:
• the conduction loss ( c ) due to the finite resistance of the metal strip and backside
ground metalization, and
• the dielectric loss ( d) due to the loss tangent in the substrate material.
120 0.50
110
Characteristic Impedance ( W)
0.45 30 GHz
Loss per Wavelength (dB)

100 50 GHz
0.40
90
0.35 70 GHz
80
70 0.30 90 GHz
60 0.25 110 GHz
50 0.20 130 GHz
40
0.15
30
20 0.10
10 0.05
0 0.00
0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500
Line Width (µm) Line Width (µm)
(a) (b)
Fig. 3.6. Calculated impact of the microstrip line width on its (a) characteristic impedance and (b) con-
duction loss. The conduction loss is normalized per the operating guided wavelength inside the
microstrip 75-μm SiC substrate ("r = 9:7).
In the case of using semi-insulating substrate materials, such as SiC in this work, the
dielectric loss d is usually much smaller than the conductor loss c , and thus it can be
usually neglected [33].
The conduction attenuation constant per unit length can be approximated by the follow-
ing equation [33]:
1
c = ; (3.19)
2Z0 w
where Z0 is given by (3.17), w is the metal strip width, is the electrical conductivity
of the strip material, and is the skin depth arising from the frequency-dependent skin
effect, that is given by [121, 122]
1
= f : (3.20)
The thickness of the full gold metal stack in the used MMIC technology is t = 3 μm,
which is at least six times the skin depth at mm-wave frequencies, i.e., above 30 GHz.
Therefore, it should be safe to neglect the impact of the conductor thickness on the
overall loss [121, 122].
From (3.19) and (3.20) it can be concluded that the conduction loss per unit length
is proportional to the operating frequency and inversely proportional to the line width.
However, with increasing frequency of operation, the absolute length of the transmis-
sion lines used for impedance matching is usually decreasing, since it is dependent on
the operating wavelength (the =4-transformer is a clear example). Hence, from a de-
signer’s perspective it is reasonable to express the attenuation constant normalized to
the operating guided wavelength inside the microstrip substrate rather than per absolute
length. This quantity is plotted in Fig. 3.6(b) for several operating frequencies. It can
be noticed that the normalized conduction loss per wavelength is decreasing with the
increasing operation frequency, which may seem counter-intuitive at first. This effect
p per unit length is pro-

has its origin in the fact that the conduction attenuation constant
portional to the square root of the operating frequency ( c / f ) due to the skin effect,
which can be seen after inserting (3.20) into (3.19). On the other hand,
the wavelength
is inversely proportional to the operating frequency, that is, / 1 f . Therefore, the
p per unit length and the operating wavelength,
resulting product of the conduction losses
plotted in Fig. 3.6(b), follows a / 1 f functional relationship.
What is truly independent of the operating frequency, is that the conduction loss is
reduced with increasing line width. This, besides the low-impedance properties discussed
before, is the second argument for utilizing wide microstrip lines in the matching networks
of broadband amplifiers.
Limitations of Low-Impedance and Low-Loss Microstrip Lines
From the aforementioned evaluation of impedance and loss of the microstrip line and
given the passive requirements laid out in Sections 3.1.2 and 3.1.3, one can conclude that
using lines with extreme widths should provide the best-case gain-bandwidth performance.
However, there are limitations in dimensioning microstrip lines. On the one hand, very
wide MSLs consume a significant chip area which increases the MMIC cost, especially
when a high-speed compound semiconductor process is employed. On the other hand,
line widths approaching a significant fraction of the operating wavelength could allow for
propagation of higher-order modes within the band of interest, and thus deteriorate the
overall circuit performance [6].
The maximum operating frequency of a microstrip line is limited by the cutoff frequencies
of the two dominant parasitic effects, namely the surface wave mode and the transverse
resonance. The cutoff frequency of the lowest order TM1 surface mode is commonly
approximated by [33]
c0 2
fT 1 u 2h "r 1 tan 1 "r ; (3.21)
where c 0 is the speed of light in free space. For the case of the used GaN-on-SiC
MMIC technology with a substrate thickness of h= 75 μm, (3.21) can be evaluated
as fT 1 448 GHz. However, in case of the presence of transverse discontinuities in a
microstrip circuit (such as bends or junctions), which is usually the case in a useful
microwave circuit, the transverse currents may allow for propagation of the transverse
electric (TE) surface modes [33]. The cutoff frequency of the TE1 mode can be approx-
imated as [33]
pc0
fT 2 u ; (3.22)
2h " r 1
which in the case of the used MMIC technology is fT 2 339 GHz.
Additionally to the surface modes, which are affected by the substrate thickness, another
effect that can occur when employing wide MSLs is excitation of a resonance along the
transverse axis of the conductor strip, i.e., along the line width axis [33]. The threshold
frequency for a transverse resonance is often approximated in literature by [6, 33]
c
fT 3 u p" (2w0 + h) : (3.23)
r
500
(GHz)
450
400
fT3
350
Transverse Resonance
300
250
200
150
100
50
0
0 50 100 150 200 250 300 350 400 450 500
Line Width (µm)
Fig. 3.7. Calculated threshold frequency for the transverse resonance in a microstrip line in the used
GaN-on-SiC MMIC technology.
This threshold frequency for the transverse resonance in the used GaN-on-SiC MMIC
process is plotted as function of the MSL width in Fig. 3.7. When considering a W-band
amplifier design and analyzing Fig. 3.7, one can note that the line width within the
matching networks should not exceed 400 μm in any case, for which fT 3 110 GHz. After
comparing these findings with the results provided in Fig. 3.6(a), it can be concluded that
the theoretical lower limit of the characteristic impedance of a microstrip line realized in
this technology is around 18 Ω for assuring a safe operation at the W-band.
3.1.5 Experimental Verification of Low-Impedance Matching

Networks
Given the hazards of using wide microstrip lines discussed in Section 3.1.4, an experi-
mental validation of the microstrip process design kit (PDK) at the W-band frequencies
has been conducted. Its main purpose was
• to determine whether the passive library correctly predicts the high-frequency be-
havior of extremely wide structures with non-typical length-to-width aspect ratios,
and
• to check if the propagation of higher-order modes of significant contribution is the
case for these designs.
The test structures displayed in Fig. 3.8 are realized as MMIC-breakouts from the match-
ing networks of the power amplifiers presented in Section 3.3. The processed structures
are the input and output matching networks with the input and output HEMT pairs,
respectively, in addition to the input matching network without any active devices. The
difference between these breakouts and the actual matching networks in the design is
the lack of bias networks due to layout compactness. Therefore, the input and output
DC-blocking capacitors were removed to provide a bias path, which should not affect
the W-band performance significantly. All structures have CPW feeders that combine
both branches to enable two-port on-wafer measurements. They are intended to be
de-embedded afterwards.
(a) (b) (c)
Fig. 3.8. Micrographs of the processed breakout structures for the W-band input and output match-
ing networks evaluation. (a) IMN without HEMTs. (b) IMN with the input stage HEMTs
(2 2 35 μm). (c) OMN with the output stage HEMTs (2 4 35 μm).
Loss Evaluation of the Matching Networks
The dissipative loss (DL) of the IMN is evaluated by de-embedding the measured
S -parameters of the structure shown in Fig. 3.8(a) and calculating the dissipative loss
from (3.15). A comparison of the measured DLIMN with a simulation using the passive
PDK elements is given in Fig. 3.9(a). The measured loss is better than 0.5 dB within
the W-band. Given the best-case uncertainty of the calibrated measurement setup of
0.1 dB, the results are in good agreement with the simulation shown with dashed lines.
This indicates a good prediction of the wide microstrip line behavior by the passive PDK
models. For reference, a simulated performance of the complete IMN with the bias
network is presented with a dotted line. A peak occurring around 70 GHz is caused by
the good input matching of the applied novel radial stubs, which is discussed later in
Section 3.2. Due to the lack of an on-wafer structure for measuring the sole OMN
performance, only simulation results are provided. However, as seen in the above com-
parison, the passive PDK models can be considered trustworthy. The dissipative loss of
1.4 1.4
1.3 IMN breakout meas. 1.3
OMN test breakout sim.
1.2 IMN breakout sim. 1.2
Dissipative Loss (dB)
Dissipative Loss (dB)
1.1 1.1 OMN with bias network sim.

1.0 IMN with bias network sim. 1.0
0.9 0.9
0.8 0.8
0.7 0.7
0.6 0.6
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0.0 0.0
60 65 70 75 80 85 90 95 100 105 110 60 65 70 75 80 85 90 95 100 105 110
Frequency (GHz) Frequency (GHz)
(a) (b)
Fig. 3.9. Loss evaluation of the W-band microstrip breakout structures. (a) Measured (solid) and simu-
lated (dashed) dissipative loss of the passive IMN test structure simulated DL of the IMN with
bias network (dotted). (b) Simulated dissipative loss of the passive OMN test structure (dashed)
and complete OMN with bias network (solid).
5 S11 S21 5
S21 S22
0 0
S-parameters (dB)
S-parameters (dB)
-5 -5
-10 -10
-15 -15 Meas.

Meas.
-20 Sim. -20 Sim.
Hybrid Hybrid
-25 -25
60 65 70 75 80 85 90 95 100 105 110 60 65 70 75 80 85 90 95 100 105 110
(a) (b)
Fig. 3.10. Evaluation of the matching bandwidth performance of the W-band microstrip breakout struc-
tures. S -parameter measurement (solid) and simulation (dotted) of the (b) IMN and (b) OMN
breakout structure with the respective HEMT pairs. A hybrid result of the simulated passives
combined with measured HEMTs is given with dashed lines. VDS = 15 V and ID = 400 mA/mm
in both cases.
the OMN is evaluated by means of (3.16). The results are shown in Fig. 3.9(b). The
simulated DL of the OMN breakout is on a comparable level as in case of the IMN,
which is expected due to the structure similarity. A simulation of the complete OMN
containing the bias network and utilized in the PA design is plotted with a solid line.
The DLOMN, PA is expected to be better than 0.55 dB across the frequencies of interest,
except for a slight peak around 80 GHz. As for the IMN case, it is created by the novel
type of radial stub (Section 3.2).
Bandwidth Performance of the Matching Structures
The matching bandwidth of the input and output matching networks is analyzed with
the breakout structures shown in Figs. 3.8(b) and 3.8(c), respectively. These breakouts
were laid out with the corresponding HEMT pair and a CPW-feeder, which is to be
de-embedded afterwards. The measured and simulated S11 and S21 of the IMN breakout
are depicted in Fig. 3.10(a). As can be noticed, the measured input matching response
is shifted by about 25 GHz towards lower frequencies with regard to the simulation. To
assess whether the origin of this discrepancy results from modeling of the passive or
active devices, a hybrid approach combining the simulated passive elements from the
PDK with the measured HEMT cells is presented with dashed lines. This result is in
much better agreement with the measured ones, indicating that the input capacitance
of the HEMTs in this process run has increased compared with the run from which the
model was extracted. The input matching is better than −3 dB across the W-band,
with the minimum located in the middle of the band, contrary to the upper edge of the
W-band, which was aimed in the design as shown by the simulation curve.
An analogous analysis for the OMN case is provided in Fig. 3.10(b). Again, the S22 is
shifted by about 20 GHz towards lower frequencies with regard to the simulation. The
hybrid analysis of the PDK-based passives simulation with measured HEMT cells indicates
0.20
Transition Loss (dB)

0.15
0.10
0.05
0.00
60 70 80 90 100 110 120
Frequency (GHz)
Fig. 3.11. EM-simulated loss of the MSL-to-CPW transition. The transition is marked in the inset.
that the output capacitance of the transistors is increased in comparison with the PDK,
which is the main reason for this shift. Together with an increase of the small-signal
transconductance (gm ) of the processed HEMTs compared with the active PDK models,
as discussed in Section 3.3, these capacitance discrepancies are most likely responsible
for the differences in the S21 response in both cases.
3.1.6 Microstrip-to-Coplanar Mode Transition

In the circuits shown in Section 3.1.5, two dominating propagation modes are expected,
that is, an MSL mode in the matching networks and a CPW mode within the HEMTs.
Hence, some loss has to be expected at the transition point due to the mode conversion.
The extension of ground planes around the HEMTs (see inset of Fig. 3.11) should allow
for an optimum transition between these modes. The EM-simulated loss in this transition
is better than approximately 0.15 dB over the W-band, as depicted in Fig. 3.11.
Apart from assessing the loss of the transition, another important concern is to localize
the point from which, after passing the transition, the propagation modes can be con-
sidered as almost-purely of CPW or MSL type. The in-house GaN HEMT model used in
this work [108] (see Section 2.5) was extracted using measurements of CPW-based test
structures. Therefore, when using this model in circuit designs employing MSL environ-
ment, special care has to be taken of the propagation modes that will be presented at the
reference plane of the transistors. Assuring that the modes seen by the HEMTs within
the circuit are compatible with the modes present in the model-extraction structures
should increase the probability of a first-pass design success of the complete MMIC.
The above concern is addressed by performing full-wave EM simulation of the matching
structures and monitoring the field distributions at the particular points of interest. In
Fig. 3.12, simulation results at 94 GHz of a structure including the discussed MSL-to-
CPW transition are shown. The field monitor is located at the plane where the input of
the HEMTs is expected. As can be seen from the distribution of the electric and magnetic
fields, the propagation mode at this plane can be considered as nearly pure CPW mode
[see Fig. 3.5(b)], which should closely match the conditions during the HEMT model
extraction.
(a)
(b)
(c)
Fig. 3.12. EM-simulation of the field distribution at the MSL-to-CPW transition. (a) Simulation structure
modeled in CST Microwave Studio® with the HEMT’s reference plane marked. (b) E-field and
(c) H-field distribution at the reference plane simulated at 94 GHz.
3.2 Broadband DC-Biasing Networks Using Novel Radial Stubs 37
3.2 Broadband DC-Biasing Networks Using Novel

Radial Stubs
Besides the matching networks, another important passive-element-based part of a

broadband MMIC is the biasing network. Its main purpose is to provide a path for
the DC-bias to the transistors, and at the same time to prevent the in-band RF-signal
from leaking into the DC-path. At lower microwave frequencies, this function can be
achieved by incorporating an RF-choke in the design. However, at mm-wave frequencies
implementing this element on-chip is very challenging due to profound parasitic coupling
effects.
An alternative solution is a shunt =4 open-circuit stub from Fig. 3.13(a). This element
transforms the open circuit to a short circuit at a frequency where the stub length is equal
to =4 [123] which, as a result, leads to rejecting the RF-signal around this frequency.
The dependency of the operating frequency on the physical dimensions implies that the
=4 stub is a bandwidth-limited solution. The bandwidth performance can be enhanced
by using a stub of a lower characteristic impedance (Z0 ) from Fig. 3.13(b), as evaluated
for an ideal MSL case in Fig. 3.14. It can be noticed that decreasing the Z0 from 50 Ω to
25 Ω results in a nearly two-fold -15-dB rejection bandwidth improvement. Regrettably,
realizing a very low-impedance stub in most of the modern MMIC-technologies requires
employing very wide MSLs. Besides occupying a relatively large chip area, stubs realized
with wide MSLs have additionally a disadvantage of a poorly-defined point of excitation,
as the physical width of the line can approach a notable fraction of the wavelength as
depicted Fig. 3.13(b). This can result in exciting higher-order propagation modes of a
significant contribution [124]. These concerns regarding employing low-impedance MSLs
are addressed in Section 3.1.4.
The radial stub drawn in Fig. 3.13(c) is a compact way to realize a low-impedance
microstrip stub. This element is very often found in bias networks of active microwave
circuits [125]. Contrary to the low-impedance stub of a uniform width from Fig. 3.13(b),
the radial stub has a well-defined point of excitation, which allows for operating at an
extended frequency range due the higher launching frequency of parasitic propagation
modes of higher order [125].
Z0,2
Z0,1
/4 /4 /4
(a) (b) (c)
Fig. 3.13. Microstrip realizations of a shunt open-circuit quarter-wavelength stub. (a) High-impedance
stub. (b) Low-impedance stub. (c) Radial stub.
-5
Z0 = 50 W
Z0 = 25 W
-10
S21 (dB)
-15
-20
-25
-30
80 85 90 95 100 105 110 115 120
Frequency (GHz)
Fig. 3.14. Simulated S21 response of ideal shunt open-circuit quarter-wavelength stubs for two different
characteristic impedances.
3.2.1 Modeling of the Conventional Radial Stub

Before proceeding to more advanced structures, a mathematical description of the con-
ventional radial stub will be provided. It will later serve as a foundation for modeling of the
novel stub described in Section 3.2.4. The geometry of a shunt connected conventional
radial stub shown in Fig. 3.15 was analyzed in [126], where a closed-form formula for its
input impedance was derived. Assuming only the presence of the dominant quasi-TEM
radial mode, the input impedance of a radial stub can be described as [126]
2 2='
Zin,stub = j Z0 cot(k r ie ; k ro e ) j !h
2
P0
2
+
h
2 2 ; (3.24)
' k00 k " eff;1 j !"eff;0 roe
r
ie
with
( ) ( )
N0 k r i e J1 k r o e ( ) ( )
J0 k r i e N 1 k r o e
cot(k r ie ; k ro e )= ; (3.25)
J 1 (k r )N 1 ( k r
ie )
oe N 1 (k r )J 1 (k r
ie ) oe

w ge r oe
wg
w we
r ie
Fig. 3.15. Geometry of a conventional radial stub [126]. The suffix e indicates effective dimensions.
h 1 p
Z0 = r120p
' "
; (3.26) P0 =
r2 r 2; (3.27) and k = ! "; (3.28)
ie r oe ie
where J and N are the Bessel and Neumann functions of the i th order, respectively, h
i i
is the substrate thickness, and "eff is the effective permittivity of the resonant modes.
;n
The effective geometrical parameters illustrated in Fig. 3.15 are obtained in terms of the
actual geometric parameters using the following formulas provided in [127] and [128]:

t 2h t 2h
w = w + ln + 1 ; (3.29) w = w + ln +1 ; (3.30)
ge
t g e
t
w
r = ge
; (3.31)
ie
2 sin('=2)
⎧
⎨ 1
r =r 1+
2h
r
ln
r
2h
o
+1:7726 +
w ge
2
w g
⎩ sin('=2) ; '<
(3.32)
' < 3=2
oe o
o
1;
with t being the conductor thickness.
3.2.2 Existing Solutions to Bandwidth Enhancement of the Radial

Stub
Although being more compact and broadband than a low-impedance =4 open stub
of uniform width, the bandwidth of the radial stub can be still insufficient for some
applications, such as wideband amplifiers. The bandwidth can be enhanced by placing a
/4
(a) (b) (c)
Fig. 3.16. Existing solutions to bandwidth enhancement of the radial stub. (a) Butterfly stub. (b) Cas-
caded stubs. (c) Connected half-stubs.
second shunt-stub in parallel, which creates the so-called butterfly configuration shown in
Fig. 3.16(a). Another possibility for even further bandwidth improvement is to cascade
a second radial stub with a =4 line in between [125], as illustrated in Fig. 3.16(b).
However, these solutions come at a cost of an increased circuit area.
In [129], Dehbashi et al. proposed a compact concept comprising inclined half-stubs
connected at their vertices, illustrated in Fig. 3.16(c). The performance in terms of
bandwidth is similar to the one provided by the cascaded stubs from Fig. 3.16(b), but
the chip area consumed by the structure is reduced almost by half [129].
3.2.3 A Novel Type of Radial Stub

The radial stub concept introduced here is a modification of the layout from [129]. It is
composed of two inclined half-stubs and a transmission line (TL) in between, as depicted
in Fig. 3.17. The half-stubs are slightly separated at their vertices, rather than connected
as in [129]. The parasitic capacitance created by this separation allows for establishing
a second in-band resonance, which results in a significant BW improvement without any
substantial area penalty.
3.2.4 Model Development for the Novel Separated Radial Stub

The novel type of stub is analyzed by partitioning the structure into two vertex-coupled
stubs with a transmission line in parallel. In order to do so, one can characterize every
element of the structure with its transmission matrices (ABCD , here denoted shortly
by A ) and cascade them for calculating the final response [33]. However, in (3.24)
the radial stub is treated as a one-port network. Such an assumption will lead to loss of
information about the capacitive coupling between the stubs, most pronouncedly near the
closely separated vertices. This coupling plays a vital role in the broadband performance
of the stub by introducing a second resonance. In order to overcome this issue, the
novel radial stub was modeled as a tapered MSL with an additional shunt-connected
smaller stub to account for the fringing capacitance to ground. This approach creates
an opportunity to insert the coupling element between the inclined stubs, e.g., by using
l sep
ro
w line
l line wg
Fig. 3.17. Geometry of the novel separated radial stub.
[A L ]
[A T ] [A T ]
[A S ] [A S]
[A C ]
Fig. 3.18. Modeling approach to the novel separated radial stub.
a lumped capacitor. The described concept is illustrated with a schematic in Fig. 3.18.
The ABCD -parameters of the elements are [33]:

cosh l Z0 sinh l
AL = Y0 sinh l ; cosh l (3.33)
N
cosh n dl Z0;n sinh n dl ;
AT =
Y sinh n dl cosh n dl
(3.34)
n=1 0;n
⎡ ⎤ ⎡ ⎤
1 0 1
AS =⎣ ⎦; 1
(3.35) and AC =⎣ j!CC ⎦ : (3.36)
Yin,stub 1 0 1
The tapered line is described as a cascade of multiple microstrip line segments of an

infinitesimal length dl and a gradually changing width wn , each with an individual complex
propagation constant n and a characteristic impedance Z0;n , calculated analogously as
in Section 3.1.4 with [119, 120]
⎧
8h w
1
⎪ 60
p
⎨ " ln w + 4h ;
⎪
e;n n
n
wn h
Z0;n = Y = ⎪ 120
(3.37)
0;n ⎪ ⎩ p
"e;n wn =h + 1:393 + 0:667 ln(wn =h + 1:444)
; wn > h
n=
Rs p
+ j! 0 "0 "e;n ; (3.38)
Z0;n wn
where RS is the surface resistivity of the conductor [33]. The effective dielectric constant
"e ;n of each segment is given as [119, 120]
"r + 1 "r 1 1
"e;n = + : (3.39)
2 2 1 + 12h=wn
The Yin,stub in (3.35) is the input admittance of the “remaining” radial stub and is cal-
culated as the reciprocal of (3.24). In (3.36), CC is the value of the lumped capacitor
used to model the coupling between the stubs. The final result is obtained by solving
0
-5
S-parameters (dB)
-10
-15
-20
-25 S11
-30 S21
-35 Calc.
Sim.
-40
0 20 40 60 80 100 120 140 160 180 200
Frequency (GHz)
Fig. 3.19. Model verification of the novel radial stub: calculated (solid) and EM-simulated (dashed)
S -parameters.
the parallel connection of transmission line AL with the cascade of elements in the
remaining branch,
AT1 AS1 AC AS2 AT2 : (3.40)
This can be done by transforming both branches to admittance Y -matrices and adding
them together [33]. The resulting Y -matrix can be easily converted to the S -matrix [33]
in order to investigate the scattering parameters of the circuit.
To verify the described approach, in Fig. 3.19 the S -parameters calculated numerically
using the proposed method are compared to a 3D EM-simulation of the novel stub. The
results match each other well. The slight differences could be due to neglected coupling
between the inclined stubs and the feeding transmission line as well as due to inaccurate
modeling of the losses in the structure.
Determination of the Vertex-Coupling Capacitance Value
Most of the parameters used in equations (3.33)–(3.36), that are necessary to de-
velop the mathematical description of the model from Fig. 3.18, can be determined
solely from the physical dimensions and material properties of the respective structures.
Nonetheless, the question remains as to how the capacitance value CC describing the
vertex-coupling between the stubs in (3.36) can be derived. In order to achieve a value
of physical relevance rather than just a fitting parameter, the approach followed here
was to EM-simulate the region near the vertices and extract the series capacitance as
CC = jY12j=2f . The result was cross-checked using microstrip gap model simulations
using microwave CAD software as well as calculated using formulas available in litera-
ture [130]. The obtained capacitance values using the aforementioned methods ranged
from 0.32 fF to 0.5 fF, which can be considered as trustworthy. Figure 3.20 provides a
comparison of the calculated S -parameters using both capacitance values with the EM-
simulation result serving as the reference. It can be noticed that the matching between
the theoretical calculations and EM-simulation is relatively accurate in both cases.
0 0
-5 C = 0.32 fF -5 C = 0.50 fF
S-parameters (dB)
S-parameters (dB)
-10 -10
-15 -15
-20 -20
-25 S11 -25 S11
-30 S21 -30 S21
-35 Calc. -35 Calc.

Sim. Sim.
-40 -40
0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200
(a) (b)
Fig. 3.20. Comparison of the calculated (solid) S -parameters of the novel radial stub for two
vertex-coupling capacitance values: (a) 0.32 fF and (b) 0.5 fF. The EM-simulation (dashed)
of the actual structure serves as the reference in both cases.
Impact of the Vertex-Coupling Capacitance on the Performance of the Stub
After determining the value of the vertex-coupling capacitance using the aforesaid ap-
proach, it is also of great interest how the value of this capacitance is impacting the
performance of the novel stub. This impact is investigated with the aid of Fig. 3.21.
In Fig. 3.21(a), the S21 response of the novel stub is calculated for different values of
the vertex-coupling capacitance using the model shown in Fig. 3.18. It can be seen that
the rejection bandwidth of the stub is increasing with the increasing value of the vertex-
coupling capacitance, which indicates a tighter coupling between the two half-stubs.
However, the rejection bandwidth is traded for the rejection region depth, that is, the
0 0
Vertex capacitance (fF) Vertex spacing (µm)
-10 0.01 0.1 0.5 -10 2 6 10
0.05 0.3 1.0 4 8 12
-20 -20
S21 (dB)
S21 (dB)
-30 -30
-40 -40
-50 -50
-60 -60
90 95 100 105 110 115 120 125 90 95 100 105 110 115 120 125
(a) (b)
Fig. 3.21. Impact of the vertex-coupling capacitance value on the performance of the stub. (a) Calculated
S21 of the novel stub for different values of the vertex-coupling capacitance. (b) EM-simulated
S21 of the novel stub for different values of the vertex spacing.
increasing separation between the resonances, which increases the rejection bandwidth,
comes with an increasing magnitude of the response between these resonances.
Similar observations can be also made after analyzing Fig. 3.21(b), where an
EM-simulation of the S21 response of the novel stub is plotted for different vertex spac-
ings between the two half-stubs. Increasing the spacing, which is in turn decreasing the
vertex-coupling capacitance, leads to narrower rejection bandwidths. It can be also no-
ticed that at some point the spacing between the half-stubs is big enough that the stubs
cannot be longer considered as vertex-coupled. As a result, the two resonances converge
into a single one. This transition effect can be observed in Fig. 3.21(b) between the
vertex-spacing values of 8 μm and 10 μm.
3.2.5 Experimental Verification of the Novel Radial Stub

Design of Test Structures of Different Stubs
In order to experimentally evaluate and compare the performance of different types of

radial stubs, the test structures presented in Fig. 3.22(a) were designed. As can be
seen, three types of radial stubs were included, separated half-stubs introduced here (left
column), connected half-stubs reported in [129] (middle column), and conventional radial
stubs (right column). All three types of stubs were designed in singled-sided (upper row)
and double-sided or butterfly (lower row) configurations.
The stubs are intended to be used in the bias paths of a broadband GaN W-band power
amplifier MMIC, thus they were dimensioned to provide good rejection from 75 GHz to
110 GHz. The conventional radial stubs have an ro = 235 μm, wg = 40 μm, and ' = 60
(see Fig. 3.15). The wg and ' dimensions of each of the half-stubs are halved with
respect to the conventional ones, whereas ro is in this case 210 μm. This slight change
was due to the final layout performance of the amplifier presented in Section 3.3 in order
to achieve a flatter gain response. The separation between the vertices of the half-stubs,
lsep in Fig. 3.17, is 2 μm, the minimal value allowed by the design rules. The connected
Separated Connected Conventional
(a) (b)
Fig. 3.22. Micrographs of the fabricated radial stub test structures. (a) Complete test field including the
separated half-stubs (left column), connected half-stubs (middle column), and conventional
radial stubs (right column) in single-sided (upper row) and double-sided (lower row) configu-
rations. (b) Magnified comparison of the fabricated stubs of each type (to scale).
half-stubs were dimensioned in the same way as the separated ones, however for this case
lsep was set to −2 μm, again to comply with the design rules. Keeping the dimensions of
the different types of stubs similar makes an area-equivalent comparison possible. The
Z0 of the transmission lines in all test structures is 50 Ω.
The structures were fabricated with the in-house GaN-on-SiC MMIC process described
in Section 2.4. The radial stubs were realized using only the first metal layer (MET1),
whereas the feeding lines and pads were realized using the full metal stack.
Measurement Results of the Test Structures of Different Stubs
The on-wafer S -parameter measurements up to 150 GHz were performed with an Anritsu
VectorStar ME7838D vector network analyzer (VNA) with a coaxial broadband test set
with 0.8 mm connectors.
The measured and EM-simulated S21 of the three types of radial stubs are presented in
Fig. 3.23(a). Their performance is benchmarked for a fractional bandwidth (FBW) with
a rejection magnitude better than −15 dB, which can be consider as practical value for
broadband MMIC applications. As can be seen, due to establishing a second in-band
resonance, the separated half-stubs provide the broadest FBW, nearly twice as for the
conventional stub. The rejection region of the connected half-stubs from [129] is shifted
towards higher frequencies with a lower rejection magnitude. These results indicate that
for the given region of operating frequency, the separated half-stubs reported here provide
the best combination of bandwidth and area efficiency. The corresponding S11 of the
single-sided stubs are plotted in Fig. 3.23(b). In case of the novel separated stubs, a
resonance appears near the lower edge of the operation band. This resonance could
affect the stability of active circuits when this type of stub is used in the DC-bias path.
Thus, special care has to be taken during the design.
The measured and simulated S21 and S11 parameters for the compared stubs in double-
sided or butterfly configuration are shown in Fig. 3.24(a) and 3.24(b), respectively.
0 0
-5 -5
-10 -10
-15 -15
S11 (dB)
S21 (dB)
-20 -20
-25 -25
-30 Separated -30 Separated
Meas. Meas. Connected
-35 Connected -35
Sim. Sim. Conventional
Conventional
-40 -40
20 40 60 80 100 120 140 160 180 200 20 40 60 80 100 120 140 160 180 200
(a) (b)
Fig. 3.23. Measured (solid) and simulated (dashed) S -parameters of the three types of radial stubs in
single-sided configuration: (a) S21 and (b) S11 .
0 0
-5 -5
-10 -10
-15 -15
S11 (dB)
S21 (dB)
-20 -20 Meas.

-25 -25 Sim.
-30 Separated -30 Separated
Connected Meas. Connected
-35 -35
Conventional Sim. Conventional
-40 -40
20 40 60 80 100 120 140 160 180 200 20 40 60 80 100 120 140 160 180 200
(a) (b)
Fig. 3.24. Measured (solid) and simulated (dashed) S -parameters of the three types of radial stubs in
double-sided (butterfly) configuration: (a) S21 and (b) S11 .
Again, the separated half-stubs provide superior performance in terms of broadband

operation, with a factor of two advantage over the conventional solution. However, as
the in the single-sided configuration, the dip in S11 of the novel stub is still present.
The connected half-stubs in butterfly configuration seem to be non-operational, at least
below 200 GHz.
The measured and simulated absolute BW and −15 dB FBW of all investigated stubs
are collected in Table 3.1. The measured and simulated results are in good agreement.
Table 3.1. Comparison of simulated and measured absolute and fractional −15 dB rejection bandwidths
of three types of stubs in single- and double-sided (butterfly) configurations.
Stub Type flow (GHz) fhigh (GHz) BW (GHz) FBW (%)

Single-sided configuration
Separated Sim. 93.5 122.5 29 27.1
half-stubs Meas. 90.5 120.5 30 28.7
Connected Sim. 127, 178 135, 186 8, 8 10.5
half-stubs Meas. 126, 143 131, 153* 5, 10 10.7
Conventional Sim. 88 101 13 13.8
radial stub Meas. 84.5 98.5 14 15.4
Double-sided (butterfly) configuration
Separated Sim. 90.5 163 72.5 59.7
half-stubs Meas. 87.5 160 * 72.5 61.3
Connected Sim. – – – –
half-stubs Meas. – – – –
Conventional Sim. 108 137.5 29.5 24.2
radial stub Meas. 103, 139 126, 152* 23, 13 29
* extrapolated value
3.2.6 Mathematical Formulation for the Novel Stub

As can be seen from Fig. 3.23, the S21 response of the novel stub contains two closely-
spaced resonances, which is the main source for the bandwidth enhancement over existing
solutions. At the same time, a dip is present in the S11 response at the lower end of the
operation band.
In order to gain more insight about this behavior, the stub model is analyzed with regards
to its zeros and poles location. To maintain the analysis at a straightforward level, the
novel stub model can be significantly simplified to an LC circuit provided in Fig. 3.25(a).
The feed line and the tapered lines are modeled with single inductors, LL and LT , re-
spectively, whereas the “remaining” radial stub is described with shunt capacitance CS .
Despite the high degree of introduced simplification regarding the approach followed in
Section 3.2.4, the LC -model is still able to capture the most important features of the
novel stub behavior up to approximately 120 GHz, as displayed in Fig. 3.25(b). The
component values were chosen to obtain a good fit with the model from Section 3.2.4,
which is achieved by setting LL = 66 pH, LT = 46 pH, CS = 47 fF, and CC = 0.5 fF.
The S -parameters of the circuit from Fig. 3.25(a) can be calculated by following the
same approach as in Section 3.2.4. The resulting S21 response can be expressed in the
s -domain as

2Y0 (s 2 LT CS +1)2 +s 2 CC 2LT (s 2 LT CS +1)+LL
S21 (s ) = : (3.41)
sCS (sY0 LT +1)+Y0 s 3 Y0 LL LT (2CC +CS )+s 2 (2LT +LL )(2CC +CS )+sY0 LL +2
The location of the resonances in the S21 response can be found by determining the
dominant zeros (i.e., below 200 GHz) of the function from (3.41), which are located at
1
fz1 2 =
; : (3.42)
2CC LL + 4LT (CC + CS ) 4CC 4CS LL LT + CC (2LT + LL )2
0
LL -5
-10
S-parameters (dB)
-15
LT LT -20
CC -25
S11
-30
S21
-35
CS CS LC
-40
Calc.
-45
0 20 40 60 80 100 120 140 160 180 200
Frequency (GHz)
(a) (b)
Fig. 3.25. Simplified lumped LC -model of the novel stub for analytical calculations. (a) Circuit schematic.
(b) Comparison of the S -parameters response of the LC -model for fitted component values
(solid) and the calculated model discussed in Section 3.2.4 (dashed).
When solving (3.42) numerically using the aforementioned component values, the ob-
tained zeros are located at fz1 = 101.2 GHz and fz2 = 114.5 GHz. The expression under
the inner square root in (3.42) determines the spacing between the zeros, and thus
the overall bandwidth of the structure. If the vertex-coupling is neglected, so that
CC 0, (3.42) is reduced to a form describing the resonance frequency of a simple
series LC -resonator, that is,
1
fz =
2 LT CS
: p (3.43)
Evaluating (3.43) numerically using the provided component values results in

fz = 108.2 GHz. Similar behavior can be observed by analyzing the simulation results
presented in Fig. 3.21, where the double-zero S21 response is converging to a single-zero
response with decreasing the value of the vertex-coupling capacitance value (or with
increasing the vertex spacing between the half-stubs).
To complete the analysis of the S21 response, also the poles of (3.41) will be determined.
A complex-conjugate pair of poles is found and its location can be expressed as
4Y02 LT CS CS2 jCs

fp1 2 = ; (3.44)
;
4Y0 LT CS
which numerical value of the modulus is equal to 108.2 GHz. Moreover, there exist a
second complex-conjugate pair of poles. However, the analytical expression describing
this pair is rather extensive and thus, for the sake of clarity, it will not be provided here.
Nevertheless, after numerical evaluation, the location of this pole pair is found to be at
82.9 GHz.
The S11 response of the circuit from Fig. 3.25(a) can be solved in an analogical manner
as before. Its analytical expression in the s -domain is given with the following formula:

s Y02 LL s 2 LT (2CC +CS )+1 s 2 L T C S +1 CS s 2 (2LT +LL )(2CC +CS )+2
S11 (s ) = : (3.45)
s CS (s Y0 LT +1)+Y0 s 3 Y0 LL LT (2CC +CS )+s 2 (2LT +LL )(2CC +CS )+s Y0 LL +2
Again, in order to locate the resonances of the S11 response, the zeros of (3.45) have
to be determined. As can be clearly seen from analyzing the numerator of (3.45), the
first zero is at fz1 = 0 Hz. Furthermore, an imaginary zero pair is located at

2Y02 LL LT (CC + CS ) CS (2CC + CS )(2LT + LL ) +
p a1
fz2 = ; (3.46)
8 2 Y02 L2T LL CS (2CC + CS )
where
2 2 2 2 2

a1 =4Y0 LL LT CC 4Y0 LL LT CS 2CC + CS L L (C C + C S ) + 2 C C L T
2
2 2 (3.47)
+ CS 2CC + CS 2LT + LL :
Solving (3.46) numerically results in fz2 = 79.3 GHz. Both zeros are apparently visible in
the plotted S11 response in Fig. 3.25(b). Regarding the location of the poles of the S11
response, it can be noticed that the denominators in (3.41) and (3.45) are of the same
form since the network from Fig. 3.25(a) is lossless, and thus the S11 2 + S21 2 = 1 j j j j
140 140
Pole Zero 120 Pole Zero 120

100 100
80 80
Imaginary (GHz)
Imaginary (GHz)
60 60
40 40
20 20
0 0
-20 -20
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
-140 -140
-140 -120 -100 -80 -60 -40 -20 0 -140 -120 -100 -80 -60 -40 -20 0
Real (GHz) Real (GHz)
(a) (b)
Fig. 3.26. Pole-zero map of the calculated S -parameters of the simplified LC -model of the novel radial
stub. (a) S21 response and (b) S11 response.
condition must hold [33]. Therefore, the poles of the S11 response are the same as for
the S21 case.
A graphical mapping on the complex frequency plane of the resulting poles and zeros of
the S21 and S11 responses is provided in Fig. 3.26. As can be noticed from the pole-zero
map of the S11 in Fig. 3.26(b), the zero pair at 79.3 GHz is purely imaginary, thus the
damping factor = 0. Therefore, it dominates over the complex-conjugate pair of poles
located at 82.9 GHz ( = 0:07) and, as a result, creates the dip in the S11 response at
the lower end of the operating band.
3.2.7 Optimization of the Input Reflection of the Novel Radial Stub
As discussed in the previous section and seen in Figs. 3.23(b) and 3.24(b), a resonance
occurs in the S11 response at lower-end of the operating band. This effect could po-
tentially pose a danger to obtaining a favorable amplifier performance without investing
special care to the design.
In an effort to reduce the dip in the S11 response of the novel radial stub while preserving
the favorable broadband and small-footprint properties of the novel stub, a layout modi-
fication illustrated in Fig. 3.27(a) is proposed. In this approach, one of the half-stubs is
connected to the feed line through a MIM capacitor, rather than directly as in Fig. 3.18.
This results in a significant reduction of the dip in the S11 response of Fig. 3.23(b). The
development of the novel radial stub with an optimized S11 response concept described
in this section is subject to a German patent application filing [P11].
This improved layout can be described mathematically by expanding the previous ap-
proach from Fig. 3.18 in a way demonstrated in Fig. 3.27(b). A lumped capacitor ACM
with a value of 75 fF is used to model the MIM capacitor. The structure representing
the optimized stub can be solved in a similar manner as followed before in Section 3.2.4.
[A C ] M
[A L ]
MIM
Cap. [A T ] [A T ]
[A S ] [A C ] [A S]
(a) (b)
Fig. 3.27. Layout-based optimization of the input reflection performance of the novel radial stub.
(a) Layout drawing. (b) Corresponding model.
Figure 3.28 shows a comparison of the resulting S -parameter responses based on an

EM-simulation (dashed lines) and by solving numerically the circuit from Fig. 3.27 (solid
lines). As can be seen, the dip occurring previously at lower-end of the operating band
in the S11 response is now altered to a plateau with a magnitude of around −8 dB.
Therefore, this undesired effect has been reduced by almost 30 dB when compared to
the structure without a capacitor.
The agreement between the developed model and the EM-simulation is again on a very
good level. The discrepancy at the higher-end of the operation band can have its source
in neglecting the parasitic inductance introduced by the airbridge connection between
the top plate of the MIM-capacitor and the feed line.
0
-5
S-parameters (dB)
-10
-15
-20
-25 S11
-30 S21
-35 Calc.
Sim.
-40
0 20 40 60 80 100 120 140 160 180 200
Frequency (GHz)
Fig. 3.28. Model verification of the novel radial stub with an optimized input reflection response: calcu-
lated (solid) and EM-simulated (dashed) S -parameters.
0
LL
-5
S-parameters (dB)
-10
CM
LT -15
-20
LT CC
-25 S11
-30 S21
CS CS -35 LC
Calc.
-40
0 20 40 60 80 100 120 140 160 180 200
Frequency (GHz)
(a) (b)
Fig. 3.29. Simplified lumped LC -model of the optimized novel stub for analytical calculations. (a) Cir-
cuit schematic. (b) Comparison of the S -parameters response of the LC -model for fitted
component values (solid) and the calculated model shown in Fig. 3.27 (dashed).
Mathematical Formulation for the Improvement of the Input Reflection
Building on the analysis developed in Section 3.2.6, the stub with an improved S11
response can examined accordingly in order to gain more insight about the optimized
performance. As before, the analysis is maintained on a straightforward level. Therefore,
the stub is again simplified to an LC circuit provided in Fig. 3.29(a). In comparison to
Fig. 3.25(a), the model of the optimized stub comprises an additional capacitance CM ,
representing the MIM capacitor introduced in the improved layout. This simplified model
is able to provide a reasonably good fit to the model from Fig. 3.27 up to approximately
130 GHz. This is achieved by setting LL = 66 pH, LT = 46 pH, CS = 57 fF, CC = 0.5 fF,
and CM = 80 fF.
The circuit from Fig. 3.29(a) can be solved in a similar manner as in Section 3.2.6 in
order to obtain analytic expressions for the S11 and S21 responses of the optimized radial
stub and locations of the respective poles and zeros. However, these analytic expressions
are significantly more extensive as the ones obtained in Section 3.2.6 and, for the sake
of clarity, they will be not provided here. Instead, the graphical mapping on the complex
frequency plane of respective poles and zeros of the S11 and S21 responses are shown in
Fig 3.30.
As can be noticed from pole-zero map of the S11 in Fig. 3.30(b), the addition of the
MIM-capacitor shifts the zero pair located at 85.3 GHz from the imaginary axis (see
Fig. 3.26) towards the complex-conjugate pair of poles at 87.2 GHz. This results in a
partial zero-pole compensation at the lower end of the operating frequency. As an effect,
the dip seen previously in the S11 response is significantly reduced. Increasing the value
of CM moves the zero pair towards the imaginary axis due to the capacitor becoming
transparent at high frequencies (acting as a nearly-perfect short-circuit), and reverting
the system performance to the one described in Section 3.2.6.
(a) (b)
Fig. 3.30. Pole-zero map of the calculated -parameters of the simplified -model of the optimized
novel radial stub. (a) response and (b) response.
Experimental Verification of the Optimized Radial Stub
The performance of the novel radial stub with an optimized response in single-sided
and double-sided configurations was experimentally evaluated using the test structures
shown in Fig. 3.31. Each of the half-stub is dimensioned with 230 μm, 25 μm,
, and with a separation between their vertices of sep 2 μm (see Fig. 3.17).
The MIM-capacitor is sized to 10 μm , which is equivalent to a capacitance value
of approximately 62.5 fF in the utilized GaN-on-SiC MMIC process.
A comparison of the measured and EM-simulated -parameters for both configura-
tions is displayed in Fig. 3.32. It can be noted that, as predicted by the aforemen-
tioned calculations and simulations, the dip in the response is significantly reduced,
by nearly 30 dB for both single- and double-sided configuration when compared with
Figs. 3.23(b) and 3.24(b), respectively.
(a) (b)
Fig. 3.31. Micrographs of the fabricated test structures of the optimized novel stub in (a) single-sided
and (b) double-sided (butterfly) configurations.
0 0
-5 -5
S-parameters (dB)
S-parameters (dB)
-10 -10
-15 -15
-20 -20
-25 S11 -25 S11
-30 S21 -30 S21
-35 Meas. -35 Meas.

Sim. Sim.
-40 -40
0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200
(a) (b)
Fig. 3.32. Measured (solid) and EM-simulated (dashed) S -parameters of the optimized novel radial stubs
in (a) single-sided and (b) double-sided (butterfly) configurations.
Since the stubs shown in Fig. 3.31 are dimensioned in a slightly different manner than the
test stubs analyzed in Section 3.2.5, a direct comparison of the measured S -parameters
of the single-sided novel stub with an optimized S11 response and an equally-sized non-
optimized single-sided novel stub (as in Fig. 3.17) is provided in Fig. 3.33. Here, one
can notice that for the optimized novel stub case not only is the S11 dip reduced, but
also the rejection bandwidth is shifted towards higher frequencies and further broaden
in comparison to the non-optimized novel stub case. The −15 dB BW is approximately
35 GHz for the non-optimized stub and nearly 40 GHz for the optimized stub. Similar
conclusions can be drawn after analyzing the zero-pole maps of the S21 responses, shown
in Figs. 3.26(a) and 3.30(a), where the spacing between the S21 zeros of the optimized
stub [Fig. 3.30(a)] is larger than in the non-optimized case [Fig. 3.26(a)].
0
-5
-10
S-parameters (dB)
-15
-20
-25
S11
-30
S21
-35
Opt.
-40
Non-opt.
-45
0 20 40 60 80 100 120 140 160
Frequency (GHz)
Fig. 3.33. Comparison of the measured S -parameters of the optimized (solid) and non-optimized (dashed)
novel radial stub.
3.3 Application of the Passive Network Concepts on

Circuit Level
In order to demonstrate the passive network concepts discussed in Sections 3.1 and 3.2
on circuit level, two broadband GaN power amplifiers with the aim to provide a coverage
of the complete W-band were designed. These MMICs incorporate two key bandwidth-
enhancing approaches from the preceding part of this chapter, namely the low-impedance
(and thus low-loss) microstrip lines in the matching networks as well as the novel type
of broadband radial stub in the biasing networks.
Employing these considerations in the MMIC design allowed for a significant improvement
of the overall performance, and ultimately lead to a demonstration of the first-ever GaN-
based power amplifiers that are able to cover the complete W-band.
3.3.1 Design of Full W-Band GaN Power Amplifiers

The initial design of the PA consists of three CS stages, parallelized in order to increase
the output power level. In case of insufficient input drive capabilities of the measurement
setup, a four-stage variant with a higher gain was additionally designed. The four-stage
version (chip codename: “Dratew”) is an extension of the three-stage one (chip co-
dename: “Dratewka”) by introducing an extra interstage gain block and re-optimizing
the entire design. The fabricated chip micrographs are shown in Fig. 3.34, whereas a
simplified schematic diagram of a single branch of the four-stage amplifier is sketched
in Fig. 3.35. The design target was to achieve 9 dB (three-stage) and 12 dB
(four-stage) gain within the W-band. The HEMTs in the particular stages of the PAs
were sized with the total gate width ratio of 1:2:2 in the three-stage amplifier and 1:2:2:2
in the case of the four-stage PA. This rather conservative driving ratio was chosen, as
in [112], to avoid premature saturation of the driving stages. Even- and odd-mode sta-
bility of the circuit was simulated over the complete bias sequence using the 4-Gamma
method [131]. This approach aims to mimic as close as possibly the real conditions dur-
(a) (b)
Fig. 3.34. Micrographs of the fabricated full W-band GaN power amplifiers MMICs.
(a) Three-stage PA ( 3.0 mm ). (b) four-stage PA ( 3.0 mm ).
3.3 Application of the Passive Network Concepts on Circuit Level 55
VG VG VD
VG VD
VD
in out
2x35 m 4x35 m 4x35 m
st
x2 th
1 stage 2nd and 3 rd stage 4 stage
Fig. 3.35. Simplified schematic of the four-stage power amplifier (single branch). The three-stage variant
consists of only one interstage block.
ing the measurements, for instance, during the on-wafer characterization of the circuit.
The bias sequence can be summarized as the following:
• firstly, the gate voltage is ramped down from the off state (VGS = 0 V and
VDS = 0 V) to the so-called cold pinch-off state (e.g., VGS = −7 V and VDS = 0 V);
• afterwards, the drain voltage is ramped up to the nominal operating value, or in
other words, from the cold pinch-off state to the so-called hot pinch-off state (e.g.,
VGS = −7 V and VDS = 15 V);
• finally, the gate voltage is ramped up until the desired bias current at the operating
drain voltage is achieved (e.g., VGS at which ID = 400 mA/mm).
3.3.2 Impact of the Radial Stub Configuration on the MMIC

Performance
As can be noticed in Fig. 3.34, not all used stubs are of the new type. This is due to a
good input matching (S11 ) of the new stub at the lower end of W-band [see Fig. 3.23(b)],
20
18
16
14
12
(dB)
10
S21
8
6 Mixed stubs
4 All stubs new
2 All stubs conventional
0
70 75 80 85 90 95 100 105 110 115
Frequency (GHz)
Fig. 3.36. Simulated S21 of the four-stage power amplifier within the W-band for different radial stub
configurations (VDS = 15 V and ID = 400 mA/mm).
30 30
25 S21 Meas. 25 S21 Meas.
20 S11 Sim. 20 S11 Sim.
S-parameters (dB)
S-parameters (dB)
15 S22 15 S22
10 10
5 5
0 0
-5 -5
-10 -10
-15 -15
-20 -20
40 50 60 70 80 90 100 110 40 50 60 70 80 90 100 110
(a) (b)
Fig. 3.37. Measured (solid) and simulated (dashed) small-signal responses of the (a) three-stage and
(b) four-stage W-band power amplifiers. VDS = 15 V and ID = 400 mA/mm in both cases.
which has been already discussed in Section 3.2. This effect resulted in an unwanted
dip in the gain response at these frequencies in the simulations. A comparison of the
simulated W-band S21 of the four-stage PA with three different stub configurations is
given in Fig. 3.36. As seen, replacing new stubs with conventional ones at the drain bias
paths of stages 1-3 provides an optimal compromise of bandwidth and gain within the
W-band, thus, this approach is followed in the presented power amplifier designs.
3.3.3 Measurement Results of the Power Amplifiers

Small-Signal Measurements
The on-wafer S -parameter measurements were performed up to 110 GHz with an

HP8510-XF vector network analyzer (VNA). The small-signal results of the three-
stage and four-stage power amplifiers are plotted in Fig. 3.37(a) and 3.37(b), respec-
tively. The three-stage PA provides more than 10 dB of small-signal gain between
60 and 110 GHz, with an average of 15.2 dB. The operating bandwidth of the four-
stage amplifier is between 70 and 110 GHz, where the minimum and average small-signal
gain is 13 and 21.8 dB, respectively.
The profound difference between simulation and measurement results is mostly related
to the HEMTs’ intrinsic parameters, which differ from the one from which the model was
extracted, which is due to a modified gate module processing. This mainly affects gm
alongside with the input and output capacitances. This issue has been already mentioned
in Section 3.1.5. The frequency shift of the PAs’ responses towards lower frequencies
together with a higher-than-expected gain created an unwanted peaking at the lower end
of the W-band, especially pronounced in the case of the four-stage power amplifier.
In order to verify the aforesaid assumption that the increase of the gm and capacitances
is the main reason for discrepancy between simulations and measurements, the three-
stage circuit has been re-simulated with a re-tuned HEMT model. A comparison of
30
25 S21 Meas.
20 S11 Re-sim.
S-parameters (dB)
15 S22
10
5
0
-5
-10
-15
-20
50 60 70 80 90 100 110
Frequency (GHz)
Fig. 3.38. Measured (solid) and re-simulated (dashed) small-signal responses of the three-stage W-band
GaN power amplifiers using a re-tuned HEMT model. VDS = 15 V and ID = 400 mA/mm.
this re-simulation with the measured small-signal response is shown in Fig. 3.38. The
tuning of the model was guided by comparing the results of the process monitor test
structures measured on both wafers (i.e., used for model extraction and processing of
the PAs). This allowed for assessing the relative change of the small-signal intrinsic
parameters between the wafers. As can be seen, the agreement between simulations and
measurements is significantly better as in the initial case shown in Fig. 3.37(a).
Large-Signal Measurements
The on-wafer scalar power measurements were conducted with an Agilent E8247C syn-
thesizer cascaded with an HP x6 multiplier and a set of power amplifier modules con-
nected at the input side, and an HP power sensor connected to the output. Losses in
18 30 18 30
16 Meas. 28 16 28
14 Sim. 26 14 26
Gain (dB), PAE (%)
Gain (dB), PAE (%)
12 24 12 24
Pout (dBm)
Pout (dBm)
10 22 10 22
8 20 8 20
6 18 6 18
4
Pout 16 4
Pout 16
Gain Gain Meas.
2 14 2 14
PAE PAE Sim.
0 12 0 12
70 75 80 85 90 95 100 105 110 70 75 80 85 90 95 100 105 110
(a) (b)
Fig. 3.39. Measured (solid) and simulated (dashed) CW frequency responses of the (a) three-stage
and (b) four-stage W-band power amplifiers for a constant Pin = 15 dBm. VDS = 15 V and
ID = 400 mA/mm in both cases.
20 10
18 9
16 8
14 7
PAE (%)
Gain (dB)
12 6
10 5
8 4
Frequency (GHz) 3 Frequency (GHz)
6
70 85 100 70 85 100
4 2
75 90 105 75 90 105
2 1
80 95 110 80 95 110
0 0
10 12 14 16 18 20 22 24 26 28 30 20 21 22 23 24 25 26 27 28 29 30
Pout (dBm) Pout (dBm)
(a) (b)
Fig. 3.40. Measured (a) transducer gain and (b) PAE versus output power for CW operation at different
frequencies of the three-stage amplifier (VDS = 15 V and ID = 400 mA/mm).
the waveguides and probe tips were removed in a calibration process. The large-signal
calibration procedure is similar to the one described in more detail in Section 4.1.4.
The results of a continuous wave (CW) frequency sweep from 70 GHz to 110 GHz of the
three-stage power amplifier for a constant input power (Pin ) of 15 dB are presented in
Fig. 3.39(a). The output power across this band is 25 2 dBm, with a corresponding gain
and PAE of 10 2 dB and 6 2 %, respectively. The agreement between measurements
and simulations is good within the W-band.
The measured transducer gain (GT ) versus the output power of the three-stage MMIC
is shown in Fig. 3.40(a). The maximum output power (Pout ) of 27.2 dBm is achieved
26 12
24 11 Frequency (GHz)
22 10 70 85 100
20 9 75 90 105
8 80 95 110
Gain (dB)
18
PAE (%)
7
16
6
14 5
12 Frequency (GHz) 4
10 70 85 100 3
8 75 90 105 2
6 80 95 110 1
4 0
10 12 14 16 18 20 22 24 26 28 30 20 21 22 23 24 25 26 27 28 29 30
(a) (b)
frequencies of the four-stage amplifier (VDS = 15 V and ID = 400 mA/mm).
[112] [139]
[140]
Output Power (dBm) [138] [134]
[100] [133]
[21] [132]
[136] [135]
IAF HRL QuinStar
NEDI Fujitsu Raytheon
[137]
Frequency (GHz)
Fig. 3.42. State-of-the-art W-band GaN power amplifier MMICs.
at 80 GHz at 8-dB gain compression. The corresponding PAE within W-band is given in
Fig. 3.40(b). The average PAE over the band is 6.5 %, with a peak value of 8.5 % at
80 GHz. However, due to the low driving ratio of the consecutive stages used in both
designs (see Section 3.3.1) these amplifiers are not optimized for efficient operation.
The resulting CW-frequency sweep of the four-stage amplifier from 70 GHz to 110 GHz
for a constant Pin of 15 dB is depicted in Fig. 3.39(b). The output power across the band
is 27 1 dBm, with a corresponding gain and PAE of 12 1 dB and 5–8.5 %, respectively.
The measurements are relatively well-matched to the simulations, especially at the higher
end of the W-band.
From the measured transducer gain versus the output power illustrated in Fig. 3.41(a),
one can see that the maximum Pout of 28.6 dBm is delivered at 80 GHz in about 12-dB
gain compression. Given the relatively small output total gate width (TGW) of 280 μm
used in the designs, a notable output power density on the order of 2.6 W/mm on circuit
level is reached. The multi-frequency PAE measurements of the four-stage version are
provided in Fig. 3.41(a). The average PAE over the band is 6.1 %, with a peak value of
8.6 % at 80 GHz.
3.3.4 Comparison with the State of the Art

Table 3.2 and Fig. 3.42 collect the reported state-of-the-art W-band GaN power amplifier
MMICs. As can be seen, the discussed PAs are the only chips able to cover the entire
W-band in this technology. For comparison, Table 3.2 gathers also the data of two
MMICs based on GaAs technology with a full W-band coverage, however at notably
Table 3.2. State-of-the-art W-band high-power MMICs.
BW jS21 j Pout PAE Size FoM§

Reference 2
(GHz) (dB) (dBm) (%) (mm ) (WGHz)
GaN-based W-band power amplifier MMICs
this work 70-110 10 25.6* 6.5* 3.75 × 3.0 14.5
** **
(3-stage) 27.2 8.5
this work 70-110 13 27 *
6.1* 4.25 × 3.0 20
** **
(4-stage) 28.6 8.6
yy
[21] 79-95 20 31.4 27yy n/a 16.5
[100] 71-86 22 31.8 9.5 4:0 2:0 13.9
[112] 75-100 16 34 12 †
5:4 2:75 51.9
z
[132] 88-99 11 31.5 21 n/a 12.6
[133] 92-96 15 31.8 20.5z n/a 4.4
[134] 87-95 10 32.3 11 2:9 1:6 10.1
[135] 82-95 11 30 6 2:75 1:5 7.7
[136] 76-90 15 30.6 12.3 2:0 1:8
zz zz
10.8
[137] 70-105 16 20 6 n/a 8.0
# #
24.5 13.2
[138] 80-87 12 33 z
15.3z n/a 8.7
[139] 84-94 18 34 13 3:5 1:9 18.3
[140] 81-86 22 33.5 10 4:0 2:5
† †
6.8
Full W-band power amplifier MMICs in other technologies
[141] 65-110 14.5 22.5 7.6 1:25 2:75 7.5
InGaAs
[142] 75-110 14 14.5 9.6 2:7 1:85 1.0
GaAs

§
FoM = Pout BW (fH 110 GHz)2 † 84 GHz z 93 GHz yy 83 GHz
zz
86 GHz # 90 GHz * avg. 70–110 GHz ** 80 GHz
lower power levels. The bandwidth in Table 3.2 is estimated as the 3-dB output power
bandwidth. To evaluate the power-bandwidth trade-off during the design, a figure of
merit (FoM) defined as the power-bandwidth product (WGHz) is provided. To account 2
for the pf 2 -limit [143], which indicates that the available
output power follows a / 1 f
functional relationship, a correction factor of (fH 110 GHz)2 for the power-bandwidth
product is introduced, where fH is the upper cutoff frequency of the circuit (in GHz),
whereas the 110 GHz, being the upper edge of the W-band, is used for normalization.
Excluding the circuit from [112], which in this measure is significantly ahead of the
remaining MMICs due to an impressive combination of high output power of 2.5 W
delivered over 25 GHz bandwidth, the power amplifiers developed within this thesis are
among the best reported to date. Furthermore, an advantage of using GaN over GaAs-
based technologies for broadband power generation even at these high frequencies is
noted.
3.4 Conclusions on Chapter 3 61

This chapter has discussed several aspects regarding the design of passive networks in
application for mm-wave GaN power amplifiers. In particular, the main focus has been
put on optimizing the bandwidth performance of two key passive parts of any active
MMIC, namely the matching and DC-biasing networks.
Matching network design has, besides the capabilities of the active devices, a decisive
impact on the overall performance of the circuit. The optimal matching network de-
sign by incorporating low-impedance transmission lines can push the circuit’s bandwidth
performance closer towards the theoretical limits set by the Bode-Fano criterion (see
Section 3.1.1) and the often-necessary transformation of the real part of the impedance
(see Section 3.1.2). Additionally, since the high-frequency gain of the GaN HEMTs is
still relatively moderate, minimizing the loss of the networks is another critical require-
ment in order to allow for a desired compression behavior of the driving stages of a PA,
as well as enhancing its output power and PAE. Both of the aforesaid demands can be
fulfilled by using low-impedance microstrip lines, however, at a cost of an increased chip
area. Moreover, employing wide microstrip lines can lead to several parasitic effects,
such as triggering higher-order propagation modes. Therefore, extensive EM-simulations
accompanied by experimental verifications of the used models is a crucial measure for
achieving a first-pass design success.
The amplifier’s bandwidth can be also enhanced by improving the performance of the
DC-bias networks. The radial stub has been identified as a key element of such networks
for mm-wave MMIC applications. In Section 3.2, a novel topology approach to the
radial stub with a superior bandwidth performance was introduced. By using two slightly
separated half-stubs, a second in-band resonance is created. As a result, this radial
stub can provide a −15 dB rejection over a 29 % fractional bandwidth, which is a nearly
two-fold improvement over the conventional radial stub. Using this stub in a double-
sided (butterfly) configuration results in a −15 dB rejection bandwidth of about 61 %,
which is again twice as high as in the case of a conventional butterfly stub. As the
performance improvement is achieved without any substantial increase of area, the novel
stub is a well-suited candidate for bandwidth enhancement of the DC-bias paths of active
circuits. Furthermore, the development of the novel radial stub with an optimized input
reflection response concept, described in Section 3.2.7, is subject to a German patent
application filing [P11].
In order to demonstrate the above-mentioned broadband passive network concepts, two
full W-band GaN amplifiers were designed. The circuits utilize low-impedance microstrip
lines for reactive matching and the novel type of radial stub in the DC-bias paths. All to-
gether, these measures resulted in power amplifiers that can deliver on average 25.6 dBm
(three-stage) and 27 dBm (four-stage) over a 70–110-GHz band. A peak output power
of 28.6 dBm is obtained at 80 GHz, corresponding to a PAE of 8.6 %. To date, no other
reported single solid-state circuit can deliver such power levels over the full W-band.
Enabled by the used technology, the high RF-power density up to 2.6 W/mm allows for
achieving much higher absolute power levels when more HEMTs are combined, making
wideband 1-W+ MMICs feasible for the foreseeable future. Such devices could ease the
design of high-resolution radar systems with exceptional properties and high-data-rate
communication links with unprecedented bandwidths.
63
4 Topology-Based Performance
Enhancements of GaN Power
Amplifiers
After discussing the concerns regarding the bandwidth performance of the passive net-
works of GaN power amplifiers in Chapter 3, this chapter deals with exploring a portion
of attainable improvements of GaN-based circuits’ high-frequency gain and bandwidth
on transistor level. In particular, design approaches employing different transistor con-
figurations are addressed in detail.
The excellent power densities offered by GaN HEMTs [132, 136] due to their physical
parameters such as high breakdown voltage and high saturated electron velocity [71],
cannot be fully exploited on circuit level when insufficient gain is available. In such case,
the transistors placed in the output amplifier stage cannot be properly driven by the
preceding stages due to the loss of the interstage matching networks as already discussed
in Section 3.1.3. Low gain-per-stage values can result in some undesirable PA behaviors,
such as premature saturation [112] or soft-saturation characteristic [144]. Moreover,
low gain levels substantially degrade the power-added efficiency of the amplifier [6]. On
the one hand, the PAE is deteriorated already on the transistor level [6]. On the other
hand, more amplifying stages that do not directly contribute to the output power, but
increase the overall power consumption are necessary. Finally, low-gain power amplifiers
require a higher driving power to achieve the specified Pout -level, which can increase the
cost and complexity of the characterization setup as well as the end-use RF system that
incorporates such an amplifier.
Besides the high-frequency power gain improvement, the bandwidth performance of GaN
MMICs can enhanced by employing more advanced transistor configurations. However,
applying more complex topologies at mm-wave frequencies is a challenging task due to
the layout-induced parasitic effects that can degrade the high-frequency performance.
Therefore, novel layout-based integration approaches are necessary to enable mm-wave
operation.
Implementing the concepts discussed in this chapter on MMIC level enabled achieving
state-of-the-art combinations of gain, bandwidth as well as large-signal parameters for
GaN technology. Respective power amplifier design demonstrators for each approach,
with an operation span from the Ka-band (26.5–40 GHz) to the D-band (110–170 GHz)
frequencies, are provided in the remainder of this chapter.
64 4 Topology-Based Performance Enhancements of GaN Power Amplifiers
4.1 D-Band GaN Power Amplifier Using a Cascode

Topology
There are numerous examples of millimeter-wave power amplifiers employing the cascode
topology in some high-speed semiconductor technologies [118, 145–156]. However, this
topology seems to be still a rather unorthodox choice within the designer’s community
for GaN MMICs operating at the W-band and beyond, which results in only few of such
circuits reported to date [25, 26, 157]. In this section, the design of a cascode-based
GaN power amplifier operating at the D-band frequencies is discussed. Using a cascode
topology allowed for achieving a state-of-the-art combination of gain, bandwidth, output
power, and PAE among the published solid-state amplifiers operating above 100 GHz.
4.1.1 The Cascode Topology

The cascode topology comprises two transistors, one in a common-source (CS) and
the other in a common-gate (CG) configuration, where the drain of the CS HEMT is
connected with the source of the CG HEMT [158], as shown in Fig. 4.1(a). Such an
arrangement allows for a significant suppression of the negative effect of the feedback
gate-drain capacitance ( gd ) on the high-frequency gain of the common-source config-
uration [159]. This phenomenon is known as the Miller effect [160].
In a field-effect transistor case, the Miller effect leads to an increase of the effective
input capacitance of the device due to an amplification effect of the gd by a factor
depending on the voltage gain ( ) of the device and its further addition to the gate-
source capacitance ( gs ) [159]. This effective input capacitance rise can be expressed
as [159]
in,eff gs gd (4.1)
The increased input capacitance due to the Miller effect not only limits the transis-
tor’s power gain at high frequencies, but also constricts the high-frequency broadband
matching network design thereof [159] (see Section 3.1.1).
In the cascode configuration, the CS HEMT stage is loaded with the CG HEMT, which
acts as a low-impedance current buffer [161]. The low input impedance load caused by
CG
HEMT
S D
D
G G
VCAS
CS S
HEMT RF
GND
(a) (b)
Fig. 4.1. The cascode topology. (a) Schematic. (b) Micrograph of a fabricated cascode test cell using
-μm GaN HEMTs.
4.1 D-Band GaN Power Amplifier Using a Cascode Topology 65
the CG transistor (RL;CS 1=gm ,CG ) reduces significantly the voltage gain of the CS
HEMT [161] (AV ,CS = gm ,CS RL;CS 1 for equally sized and biased devices), which
in turn reduces significantly the Miller effect of the CS transistor, as can be concluded
from analyzing (4.1). In contrast, the CG configuration is much less prone to the Miller
effect than the CS one [159]. This is due to its low-impedance characteristics, which
results in a nearly short-circuited feedback capacitance of the CG transistor [159] (for
the CG case, the feedback capacitance is the drain-source capacitance Cds ). Additionally,
the voltage gain, that is reduced in the common-source stage, is restored back by the
CG transistor [161], and the overall voltage gain of the cascode is similar to a standalone
CS or CG amplifier for a fixed load [161]. The suppression of the Miller effect leads to an
improved reverse isolation (S12 ) of the cascode stage in comparison with a CS stage [6].
The improved reverse isolation of the cascode results in a significantly higher maximum
stable gain (MSG) of this topology when compared with the common-source configura-
tion [159]. The MSG can be calculated directly from the S -parameters of the device as
the magnitude ratio of the forward and reverse transmission coefficients [6]:

S21
MSG =

S12 (4.2)
Therefore, the cascode topology appears as an appealing alternative for applications in

GaN power amplifiers operating at the higher mm-wave bands, where the available gain
of GaN HEMTs is limited.
The stability of the cascode topology at lower to moderate frequencies is better than
that of the common-source due to the improved reverse isolation [6, 162]. However,
the cascode suffers from a typical phenomenon where the magnitude of S22 is exceed-
ing unity above a certain frequency, resulting in a potentially instable device at higher
frequencies [116]. It has its origin in the fact that the CS stage can be considered as
high-impedance, which results in an open-source CG device [116]. In effect, the sign of
the real part of the admittance seen from the output of the cascode is frequency depen-
dent, which results in a potential instability of the cascode topology (see [116] for an
extensive analysis). Therefore, appropriate measures have to be taken in order to ensure
in-band stability of cascode-based amplifiers, for instance by inserting a series resistance
at the gate of the CG stage [116, 162]. An alternative stabilization approach employing
a shunt RLC -network at the output of the cascode cell is provided in Section 4.1.3.
4.1.2 Experimental Evaluation of a GaN HEMT Cascode Cell

The cascode performance in the GaN HEMT technology is evaluated with an test struc-
ture shown in Fig. 4.1(b). This structure comprises a CS and a CG device, each realized
with a 4 20-μm HEMT, and its measured S -parameters were directly used during the
design of the amplifier described in Section 4.1.3. In order to benchmark the performance
of this cascode cell, a simulated single 4 20-μm common-source HEMT is used as a
reference.
A comparison of the maximum stable gain (MSG) and maximum available gain (MAG)
of both configurations is plotted with solid lines in Fig. 4.2(a). It can be seen that
the cascode topology is able to provide significantly higher values of MSG than the
30 1.1
20 1.0
MSG/MAG, S12 (dB)
0.9
10
k-factor ( -)
0.8
0
0.7
-10 0.6
-20 0.5
|, 22
-30 0.4
S |
0.3
-40 Casc. MSG/MAG Casc. |S22|
0.2
-50 CS S12 CS k-factor
0.1
10 30 50 70 90 110 130 150 10 30 50 70 90 110 130 150
(a) (b)
Fig. 4.2. Small-signal performance comparison of a measured 4 20-μm GaN cascode cell (red) with a
simulated 4 20-μm GaN CS HEMT (blue). (a) MSG/MAG (solid) and S12 (dashed). (b) jS22 j
(solid) and k -factor (dashed). VD = 12 V and ID = 300 mA/mm in all cases.
common-source configuration. The main reason behind this effect is the much better
reverse isolation of the cascode, which is expressed with a smaller S12 magnitude that is
plotted with dashed lines also in Fig. 4.2(a). As already discussed in Section 4.1.1, the
improved reverse isolation leads to a direct improvement of the MSG. As can be noticed
in Fig. 4.2(a), an enhancement of approximately 20 dB in the S12 (voltage-ratio quantity)
of the cascode results in about 10 dB better MSG (power-ratio quantity), as expected
from (4.2). The improved S12 response of the cascode confirms also the suppression of
the Miller effect compared to the common-source case, discussed in Section 4.1.1.
In Fig. 4.2(b), a comparison of the magnitude of the S22 response for the cascode and CS
topologies is provided. As discussed before and shown in [116], the S22 magnitude of the
cascode cell tends to exceed unity above a certain frequency, which in the specific case
of the analyzed DUT is approximately from 60 GHz to 140 GHz. As a result, complex
conjugate matching of the output of this cell is not realizable with passive elements
within this frequency range and special care (for instance, in form of including extra
circuit elements) is required during the design phase to assure a stable operation.
In addition, Fig. 4.2(b) shows also the Rollett’s stability factor (k -factor) [163] for
both investigated topologies. The k -factor above unity is the necessary (however, not
sufficient) condition for a stable operation of a linear two-port network under an arbitrary
lossless termination [163]. Furthermore, the unloaded two-port should not have any
right-hand poles [164]. Although this criterion is not adequate for stability evaluation
of multi-stage and/or multi-branch amplifiers [131, 164–168], the k -factor is often used
to initially assess the stability of a single active device under a specific quiescent bias
condition.
It can be seen from Fig. 4.2(b) that below approximately 60 GHz the k -factor for the
cascode is closer to unity as for the CS case. This confirms the aforementioned better
stability of the cascode topology at lower to moderate frequencies than that of the
common-source due to the improved reverse isolation [6, 162]. Above 60 GHz, which
corresponds to the point where the magnitude of the S22 response for the cascode
Fig. 4.3. Micrograph of the fabricated D-band power amplifier MMIC ( 2.0 mm ).
exceeds unity, assuring a stable operation of the CS configuration should be to some

extent a less challenging task for the designer.
4.1.3 Design of a Cascode-Based D-Band Power Amplifier

In order to demonstrate the attractiveness of the cascode topology and its feasibility in
high-frequency GaN-based circuits, a power amplifier able to cover a significant part of
the D-band (110–170 GHz) was designed. Its micrograph is shown in Fig. 4.3, whereas
the electrical schematic of a single branch of the circuit is provided in Fig. 4.4. The
amplifier consists of four reactively-matched cascode stages. All of the cascode cells use
-μm HEMTs in CS and CG configuration, as illustrated in Fig. 4.1(b).
The matching networks were implemented using grounded coplanar waveguide (CPW)
technology with a ground–ground spacing of 50 μm. CPW provides a low-inductive
ground connection for the circuit elements, which is especially important when targeting
higher frequencies. As a result, this relaxes the substrate thickness requirements, which
eases the handling of the processed wafers. Additionally, CPW shows lower dispersion
than microstrip technology [117], which is beneficial for broadband circuit design.
During the design phase, measured and de-embedded -parameters of a -μm
cascode cell processed with one of the past technology runs on a wafer with a baseline
epitaxy were directly used in combination with the passive CPW process design kit (PDK).
VC Stab.
VD VG RLC
VG VC VD
VD 4x20
VD VG 4x20
VG VC
VC 4x20 OUT
50Ω
4x20
... ...
IN 4x20 4x20
4x20 ...
50Ω 4x20 ...
Stage 1 Stage 2 Stage 3 Stage 4
Fig. 4.4. Circuit schematic of a single branch of the D-band power amplifier.
30 -20 1.20 2.00

MSG/MAG Wafer 1 |S22|
1.15 1.75
25 -25
S12 Wafer 2 k-factor
1.10 1.50
MSG/MAG (dB)
20 -30
k-factor ( -)
1.05 1.25
-)
(dB)
| (
15 -35 1.00 1.00
22
S12
S
0.95 0.75
|
10 -40
0.90 0.50
5 Wafer 1 -45
0.85 0.25
Wafer 2
0 -50 0.80 0.00
10 30 50 70 90 110 130 150 10 30 50 70 90 110 130 150
(a) (b)
Fig. 4.5. Comparison of the measured small-signal performance of the 4 20-μm cascode cell used during
the design phase (Wafer 1 with a baseline epitaxy, red) and a mapping of the wafer on which
the D-band PA was processed (Wafer 2 with an improved epitaxy, blue). (a) MSG/MAG (solid
lines) and S12 (dashed). (b) jS22 j (solid) and the stability k -factor (dashed).
The measured maximum stable/available gain (MSG/MAG) response of the cascode cell
used during the design is plotted with red solid line in Fig. 4.5(a) and shows more than
12 dB of MSG up to almost 150 GHz. Therefore, around 9 dB of linear gain per stage
was assumed as reasonable when considering broadband matching and keeping a safe
stability margin. However, this gain value does not include the losses introduced by the
matching networks.
The stability of the circuit was simulated using the 4-Gamma method [131]. As already
mentioned in Section 4.1.1, the cascode cell suffers from a typical phenomenon where the
magnitude of S22 is exceeding unity above a certain frequency, resulting in a potentially
instable device [116], which is illustrated in Fig. 4.5(b). As an effort to stabilize the
amplifier within the operation band, a shunt-RLC circuit was incorporated in the output
matching network (OMN) of the final stage as indicated in Fig. 4.4. This circuit element
adds approximately 0.5 dB of loss to the OMN.
In order to circumvent the lack of a nonlinear cascode model, the large-signal analy-
sis was performed after careful investigation of the measured power performance of a
cascode-based LNA that was previously designed and reported in [26]. The measure-
ments of this LNA at 115 GHz showed that after compensating for the OMN loss (i.e.,
at the device reference plane), a single 4 20-μm cascode can provide approximately
16 dBm, 19 dBm, and 20 dBm of output power when driven into 1-dB, 3-dB, and 5-dB
gain compression, respectively. These values along with the assumed 9 dB of linear gain
per stage were used to determine the necessary number of cells combined in the output
stage as well as the number of amplification stages. The insight gained during the LNA
design from [26] was further used to tune the impedances presented by the OMN in
order to optimize the large-signal performance around 115–120 GHz.
The design target was to cover the lower end of the D-band (approximately
110–150 GHz) with a Pout 20dBm. Therefore, four of such cascode cells are com-
bined in the output stage. The PA was designed to provide a reasonable transducer gain
(GT 15 dB) already from the last three stages (stages 2–4 in Fig. 4.6). The additional
+5 dB
14 dBm 19 dBm
4
+6 dB -1 dB
12 dBm 18 dBm 17 dBm 22 dBm

3 ISMN3
...
-0.5 dB +9 dB -1.5 dB +8 dB -1 dB -1.5 dB
1 dBm 0.5 dBm 9.5 dBm 8 dBm 16 dBm 15 dBm 14 dBm 19 dBm 25 dBm 23.5 dBm
IMN 1 ISMN1 2 ISMN2 OMN
12 dBm
... ... 22 dBm
Fig. 4.6. Simplified large-signal design analysis of a single branch of the D-band power amplifier. The
dB-values above the circuit’s blocks indicate the predicted gain of each component, whereas the
dBm-values in between show the expected power levels at a specific node.
input stage was implemented to further maximize the transducer gain in order to assure
that the amplifier can be fully characterized within the whole frequency range with the
input power available from the measurement setup.
The complete large-signal design analysis is illustrated schematically in Fig. 4.6. The
analysis was performed starting from the output side. The four cascode cells in the output
stage should be able to provide close to 23 dBm of Pout when driven into 3–4-dB gain
compression when accounting for nearly 1.5 dB of OMN loss. The interstage matching
networks (ISMNs) were designed to be as low-loss as possible to minimize the risk of
premature compression of any of the preceding gain stages. The large-signal gain of
each cascode stage was approximated using the aforementioned linear-gain assumption
and the expected Pout -values at the specific compression points.
4.1.4 Measured Performance of the D-Band Power Amplifier

Small-Signal Performance
The on-wafer S-parameter measurements were performed up to 150 GHz with an Anritsu
VectorStar ME7838D VNA with a coaxial broadband test set with 0.8-mm connectors.
40 35
30 30
25
20 S11
S-parameters (dB)
S-parameters (dB)
20
S21
10 15 S11
S22 10
0 S21 Meas.
5
S22 Sim.
-10 0
Meas.
-20 -5
Sim.
-10
-30
-15
-40 -20
0 20 40 60 80 100 120 140 95 100 105 110 115 120 125 130 135 140 145 150
(a) (b)
Fig. 4.7. Measured (solid) and simulated (dashed) small-signal response of the D-band power am-
plifier plotted (a) over the full measured spectrum and (b) within the band of interest.
VD = 12 V and ID = 300 mA/mm.
36 16
34
30 12 110 130
28 115 135
Gain (dB)
PAE (%)
26 10
120 140
24 8 125 145
22 Frequency (GHz)
6
20 110 130
18 115 135 4
16 120 140 2
14 125 145
12 0
4 6 8 10 12 14 16 18 20 22 24 26 28 4 6 8 10 12 14 16 18 20 22 24 26 28
(a) (b)
frequencies of the D-band power amplifier for a Pout -optimized quiescent bias (VD = 15 V and
ID = 400 mA/mm).
The measured and simulated small-signal responses over the complete measured spec-
trum as well as magnified around the band of interest are shown in Fig. 4.7. The
maximum jS21 j is 34 dB at 138 GHz, whereas the 3-dB BW is 18 GHz (128–146 GHz).
However, the usable operation range of this PA is much wider. For instance, it can
provide more than 25 dB of gain over a 107–148-GHz band, which accounts for a 64 %
coverage of the D-band and a 67 % coverage of the F-band (90–140 GHz).
Some discrepancies between the measured and simulated responses within the operation
range can be noted in Fig. 4.7. These are related to the technology improvements
between the wafer from which the data used for the design was extracted and the wafer
on which the power amplifier was processed. As can be seen from Fig. 4.5(a), the MSG
of a single cascode cell is improved by almost 1.5 dB at the D-band, which explains the
increase of the overall gain of the four-stage PA by approximately 5 dB. The agreement
between the measurements and simulations outside the band is very encouraging. This
suggests that the passive PDK models can be considered as accurate, and confirms that
the in-band discrepancy comes mainly from the difference in the performance of the
active devices.
Large-Signal Performance
The on-wafer scalar continuous wave (CW) power measurements over the 110–145-GHz
band were performed with an Agilent N5254A PNA-X network analyzer cascaded with an
RPG-Radiometer Physics AFM12 WR6.5 active frequency x12 multiplier connected at
the input side, and an ELVA D-band power sensor connected to the output. Losses in the
waveguides and probe tips were removed in a calibration process. All components used in
the measurement setup, such as motorized attenuators and probes, were characterized
separately to evaluate the introduced losses. Afterwards, the input power level set at
the network analyzer was correlated with the actual power delivered to the DUT. This
was achieved by sweeping the power at discrete frequency points using a short through
36 16
34
30 12 110 130
28 115 135
Gain (dB)
PAE (%)
26 10
120 140
24 8 125 145
22 Frequency (GHz)
6
20 110 130
18 115 135 4
16 120 140 2
14
125 145
12 0
4 6 8 10 12 14 16 18 20 22 24 26 28 4 6 8 10 12 14 16 18 20 22 24 26 28
(a) (b)
frequencies of the D-band power amplifier for an efficiency-optimized quiescent bias (VD = 10 V
and ID = 300 mA/mm).
on-wafer standard (160 μm) as the DUT. After accounting for the loss introduced by the
wafer probe at the output side, the measured output power value was used to determine
the appropriate correction factors at the respective frequency points.
When biased for an optimum Pout (VD = 15 V, ID = 400 mA/mm), the PA can deliver
more than 21 dBm of output power over the 115–140-GHz band with still around 20 dB
of transducer gain at saturation (GT , sat. ), as depicted in Fig. 4.8(a). The output power
reaches a maximum value of 26.4 dBm (440 mW) at 120 GHz with a corresponding
output power density of 1.4 W/mm on MMIC level. The PAE at this bias point is 11.5 %
at 120 GHz as plotted in Fig. 4.8(b). The average values of the Pout and PAE over the
110–145-GHz range for this bias point are 22.9 dBm and 5.1 %, respectively.
30 20
28 10 V & 300 mA/mm 18
26 15 V & 400 mA/mm 16
24 14
Pout (dBm)
PAE (%)
22 12
20 10
18 8
16 6
14 4
Pout
12 2
PAE
10 0
110 115 120 125 130 135 140 145
Frequency (GHz)
Fig. 4.10. Measured CW frequency response of the D-band PA for a constant Pin = 0 dBm, at an
efficiency-optimized (empty symbols) and a Pout -optimized (full symbols) quiescent bias, re-
spectively.
When tuning the quiescent DC-bias for a more efficient operating region
(VD = 10 V, ID = 300 mA/mm), the PAE of the amplifier is increased to 16.5 %, whereas
the Pout is decreased to 25.3 dBm at 120 GHz, as illustrated in Fig. 4.9. The average
values of the Pout and PAE over the 110–145-GHz range for this bias point are 21.5 dBm
and 6.0 %, respectively.
The large-signal performance at the two discussed bias points is also compared over the
measured frequency range for a constant input power of 0 dBm in Fig. 4.10. The most
significant bias dependency of the output power occurs at the higher end of the measured
band, whereas the PAE changes more notably with the bias conditions at the lower end
of the measured frequency range.
4.1.5 Comparison with the State of the Art

Table 4.1 collects reported state-of-the-art D-band power amplifier MMICs. To date,
only few GaN-based circuits operating at the D-band were reported with the majority of
the designs being optimized for a low-noise performance [22–24, 26]. HRL Laboratories
presented a six-stage CS LNA designed in a 40-nm GaN technology that covers the full
D-band with a gain above 25 dB [23]. A five-stage CS LNA targeting 120 GHz was de-
signed by NASA Jet Propulsion Laboratory (JPL) using Raytheon’s 150-nm process [24].
When assembled in a module, this MMIC can deliver 17.4 dBm of output power with a
PAE of 4.3 %. Also our group proposed an LNA design, composed of four cascode stages
operating in the 105–120-GHz band [26]. It can provide up to 20 dBm of Pout and its
measured data served as a base for the amplifier discussed in this section.
The highest output power at the D-band has been demonstrated so far by QuinStar Tech-
nology with two power amplifiers designed in the 140-nm GaN process from HRL [22].
The first design (D1) produces a minimum of 25 dBm across the 98–122-GHz band,
whereas the second design (D2) produces 28–29 dBm from 102 GHz to 118 GHz (D2
measured in fixture). The maximum PAEs are 14.4 % at 102 GHz for the D1 and 12.7 %
at 112 GHz for the D2.
To complete the picture, also state-of-the-art D-band power amplifiers in other semi-
conductor technologies are provided in Table 4.1 [169–176]. Using InP HBT technology,
power levels up to 24 dBm can be achieved over a broad frequency range as demonstrated
in [171]. Moreover, efficiencies exceeding 20 % were presented in [169] and [173], how-
ever with nearly 5-dB lower corresponding output power levels when compared with the
amplifier discussed in this section.
Table 4.1. State-of-the-art D-band power amplifier MMICs.
Frequency jS21 j Pout, max PAEmax GT @Pmax

Reference MMIC Topology Technology§
(GHz) (dB) (dBm) (%) (dB)
26.4*,a 11.5*,a 26.4*,a
this work 4-stage cascode 100-nm GaN HEMT 107–148 25–34
25.3*,b 16.5*,b 27.3*,b
5-stage CS (D1) 140-nm GaN HEMT 98–122 21–25 28y 14.4y 18y
[22] z, M
5-stage CS (D2) 140-nm GaN HEMT 102–118 19.7–20.9 29.6z, M 12.7 13z, M
[23] 6-stage CS 40-nm GaN HEMT 110–170 25–30 12 (sim.) – –
*, M
[24] 5-stage CS 150-nm GaN HEMT 120 18.9 17.4*, M 4.3 10*, #
[26] 4-stage cascode 100-nm GaN HEMT 105–120 27-38 20.3yy 2.6yy 20yy
zz
[169] 2-stage CE 250-nm InP HBT 96–120 14.8–17.9 20.2zz 22.5 10zz
[170] 5-stage CE 250-nm InP HBT 115–150 27–30 21.8** 9.8** 17.5**
[171] 5-stage CE 250-nm InP HBT 110–150 29.4 24** 7** 15**
[172] 5-stage CE 250-nm InP HBT 110–190 24.3–26.1 20.7# 8.3# 13#
**
[173] 3-stage CB 250-nm InP HBT 125–150 17.3–20.3 20.5** 20.8 15**
[174] 2-stage stack 90-nm SiGe HBT 110–140 4.7–7.7 22* 3.6* 3*
4.1 D-Band GaN Power Amplifier Using a Cascode Topology
[175] 3-stage differential cascode 130-nm SiGe HBT 109–137 26.5 16.5* 12.8* 20.5*
[176] 4-stage CE 90-nm SiGe HBT 110–134 5–15 20.8zz 7.6zz 5zz
§
the technology node refers to the gate length (HEMTs) or emitter width (HBTs) of the used process
a *
CE: common emitter CB: common base Pout -opt. bias b PAE-opt. bias M in fixture/module 120 GHz
y z yy zz ** #
102 GHz 112 GHz 115 GHz 110 GHz 140 GHz 130 GHz
73
4.2 Millimeter-Wave Integrated fT -Doubler Topology

Chapter 3 provided several considerations regarding passive networks design on circuit
level for application in broadband amplifiers. Alternatively, a wideband performance can
be also achieved by employing more advanced transistor topologies, for instance, the
Darlington [177] or the fT -doubler [178] pair, that enhance the current gain of transistors
in the utilized semiconductor process. However, applying these topologies at mm-wave
frequencies is a challenging task due to the layout-induced parasitic effects that degrade
the high-frequency performance [179].
In this section, an fT -doubler topology employing a novel integrated layout based on GaN
HEMTs is described. This compact approach allows for minimizing the layout-induced
parasitic effects and, as a result, enables operation at mm-wave frequencies. In order
to demonstrate the broadband potential of the fT -doubler topology employing the novel
integrated layout approach, two fT -doubler amplifiers able to cover multiple mm-wave
waveguide bands are presented. The development of the integrated fT -doubler layout
concept described here is subject to German and U.S. patent application filings [P8, P13].
4.2.1 The Darlington Topology

The Darlington topology [177] is widely used as a building block of broadband high-
frequency circuits in bipolar transistor processes [180–184]. A classic Darlington pair
composed of two bipolar transistors is illustrated schematically in Fig. 4.11(a). In this
circuit arrangement, the emitter of the input transistor (Q1 ) is connected directly to the
base of the output transistor (Q2 ), so that the output current of the Q1 is feed directly
to the input of the Q2 [177]. The resulting current gain ( ) of this compound structure
can be approximated at low frequencies as the product of the -values of each transistor
of the pair [177]. Moreover, such a circuit arrangement leads to a series connection
of the input capacitances of Q1 and Q2 , which results in a decreased effective input
capacitance of the compound structure [185].
However, in FET-based technologies (such as GaN HEMT), a true Darlington pair cannot
be directly realized due to the lack of DC current flowing into the gate terminal, other
than a negligible leakage current.
C1 D1
B1 G1

C2 D2
Q1 E1 B2
Q2 Q1 S1 G2
Q2
E2 S2
L
(a) (b)
Fig. 4.11. Schematic illustration of the (a) Darlington and (b) fT -doubler configurations.
4.2 Millimeter-Wave Integrated fT -Doubler Topology 75
4.2.2 The fT -Doubler Topology

The fT -doubler topology [178] is a modified Darlington pair [177]. As already mentioned
above, a true Darlington pair cannot be directly realized in an FET-based process due to
the lack of DC current flowing into the gate terminal. Therefore, a supplementary DC
path to a reference potential for the source of the first transistor must be provided. For
instance, this can be achieved with a shunt RL-network shown in Fig. 4.11(b) [186, 187].
Small-Signal Equivalent Circuit Analysis
The small-signal performance of the fT -doubler configuration can be examined with aid of
the equivalent circuit shown in Fig. 4.12(a) [185]. In this circuit, the fT -doubler configu-
ration is expressed with two FETs (Q1 and Q2 ), each represented with a commonly-used
simplified small-signal intrinsic FET equivalent circuit [6]. The source of Q1 is con-
nected with the gate of Q2 , forming a node where the aforementioned extrinsic shunt
RL-network is further attached.
In an effort to evaluate the potential of the fT -doubler configuration, its small-signal
performance can be benchmarked against the common-source configuration, which con-
ventionally serves as a reference (similarly as in Section 4.1). To facilitate a direct com-
parison between both configurations, the compound equivalent circuit of the fT -doubler
cell from Fig. 4.12(a) can be approximated by a more familiar common-source-like form
depicted in Fig. 4.12(b). The effective values of the parameters, indicated by the suffix
e in Fig. 4.12(b), can be calculated accordingly by using the intrinsic parameters seen in
Fig. 4.12(a). A general formulation of the transformation between both configurations
from Fig. 4.12 for arbitrary two-port networks is provided in Appendix A. In this section,
a particular example involving a small-signal equivalent circuit of a HEMT as in Fig. 4.12
is examined. In order to make the analysis further straightforward, the extrinsic inductor
Lext will be neglected, that is, treated as a perfect short circuit.
Before calculating the effective small-signal parameters of the common-source-like cir-
cuit, it is practical to convert the schematic of the fT -doubler from Fig. 4.12(a) into a
form, where the series RC connections (i.e., the rgs -Cgs branches of both transistors) are
In G 1
Cgd,1 D1 Out
+
V In Cfb,e Out
Cgs,1 _ 1
gm,1V1 rds,1 Cds,1

rgs,1 Cin,e +
_Vin
gm,eVin rout,e Cout,e
S1
G2 D2 rin,e
+
Rext Cgs,2 V
_ 2

Cgd,2 gm,2V2 rds,2 Cds,2
rgs,2 S2
Lext
ext.
(a) (b)
Fig. 4.12. Small-signal equivalent circuit representation of the fT -doubler configuration in its (a) com-
pound and (b) effective common-source-like forms.
In G 1
Cgd,1 D1 Out In G1 Cgd,1 D1 Out
+
Cgs,1 V
_ 1
gm,1V1 rds,1 Cds,1 r'gs,1 C'gs,1 V'

+
g'm,1V1' rds,1 Cds,1
rgs,1 _ 1
S1 S1
G2 D2 D2
+ G2
Rext Cgs,2 V
_ 2

Cgd,2 Cgd,2
gm,2V2 rds,2 Cds,2 Rext '
+ g'm,2V2' rds,2 Cds,2
rgs,2 r'gs,2 Cgs,2 V' _
2
Lext S2 Lext S2
ext. ext.
(a) (b)
Fig. 4.13. Small-signal equivalent circuit representation of the fT -doubler in its compound form with
(a) series and (b) parallel rgs -Cgs configurations.
transformed to a respective parallel configuration. This transformation is schematically

0 0
compared in Fig. 4.13(b). The resulting values of the parallel connection of rgs and Cgs
are given as [188]
rgs,n = rgs,n 1 + Qs,n
2 0
(4.3)
and
2
Qs,n
0
Cgs,n = Cgs,n ; (4.4)
1 + Q2s,n
where
1
Qs,n = : (4.5)
! rgs,n Cgs,n
Finally, it is necessary to include the effect of the voltage divider formed by rgs;n -Cgs;n
seen in Fig. 4.13(a) on the dependent current source in the parallel arrangement from
Fig. 4.13(b). This can be achieved by modifying the transconductance value accordingly:
gm,n
gm,n
0
= : (4.6)
1+j ! rgs,n Cgs,n
The effective input resistance of the fT -doubler equivalent circuit from Fig. 4.13(b) mainly
0 0
results from parallel connection of rgs,2 , Rext , and rds,1 in series with rgs,1 multiplied by a
factor 1 + gm,1 rgs,2 k Rext , and can be expressed as
0 0

= rgs,1 (1 + gm,1 rgs,2 k Rext ) + rgs,2 k Rext k rds,1
rin,e
0 0 0 0 0
1
rgs,2 Rext 1 1 1 (4.7)
0
= rgs,1 1 + gm,1 0
+ 0
+ + :
rgs,2 + Rext rgs,2 Rext rds,1 0 0
Likewise, the effective input capacitance emerges principally from the parallel combina-
0 0
tion of Cgs,2 and Cds,1 that is connected further in series with Cgs,1 , that is,
Cgs,1 (Cgs,2 k Cds,1 ) Cgs,1 (Cgs,2+ Cds,1 )

0 0 0 0
0
=
Cin,e = : (4.8)
0
Cgs,1 + (Cgs,2 0
k Cds,1 ) Cgs,1 + Cgs,2 + Cds,1
0 0
0
The effective output resistance is primarily composed of a parallel connection of rgs,1 ,
0
rgs,2 , and Rext , which is joined in series with rds,1 . In turn, this structure is connected in
parallel with rds,2 , resulting together in

= r +rrds,1 ++RRx ;

rout,e = rds,2 k rds,1 + 0
rgs,1 k rgs,2 k Rext
0
rds,2
(4.9)
ds,2 ds,1 x
where
Rx =
1 + 1 + 1 1
: (4.10)
0 0
r r R gs,1 gs,2 ext
0 0
The effective output capacitance comprises a parallel connection of Cgs,1 and Cgs,2 , that
is linked in series with Cds,1 and, all together, is combined in parallel with Cds,2 . This
effective capacitance has the form of approximately
= Cds,2 k Cds,1 (Cgs,1 k Cgs,2) = Cds,2 + Cds,1 (Cgs,1 + Cgs,2) :

0 0 0 0
Cout,e
C + (C k C )
ds,1 gs,1
0
C +C +C gs,2
0
ds,1 gs,1
0
gs,2
0
(4.11)
The effective feedback capacitance is dominated by the parallel arrangement of Cgd,1

with the series connection Cds,1 and Cgs,1 attenuated by a factor 1 + gm,1 rgs,2 k
0 0 0
Rext .
Therefore, this effective feedback capacitance can be approximated as follows:

= Cgd,1 k Cgs,1 Cds,1 1 0
Cds,1 + Cgs,1 1 + gm,1 rgs,2 k Rext

Cfb,e 0 0 0
Cds,1 Cgs,1
0
= Cgd,1 +
rgs,2 Rext
: 0
(4.12)
Cds,1 + Cgs,1 1 + gm,1

+R
0 0
0
r gs,2 ext
In order to evaluate the effective transconductance of the fT -doubler, a set of equa-

tions implementing Kirchhoff’s current law (KCL) can be applied to the circuit from
Fig. 4.13(b) with the output shorted to ground. The low-frequency KCL equation at
the S1 /G2 node in Fig. 4.13(b) can be expressed as
( ) = 0;
0 0
v2 v2
k Rext
0 0
gm,1 vin v2 0
(4.13)
rgs,2 rds,1
whereas the KCL equation at the output port can be written accordingly as
k Rext = 0:
0
0 0
v2
iout gm,2 v2 0
(4.14)
rgs,2
After solving and rearranging the above system of equations, the effective small-signal
transconductance of the fT -doubler configuration can be approximated as

rgs,2 + Rext
0
gm,1 gm,2 +
rgs,2 Rext
0 0
iout

0
gm,e = + Rext 1 ;
0
(4.15) 0
vin r
vout =0 0
gm,1 + gs,2
0
rgs,2 Rext + rds,1
which value is dominated by the transconductance of Q2 .
Phase ( )
90
0.2 0.5 1.0 2.0 5.0 120 60
S11 S22 Compound
Compound 150
CS-like
30
-0.2j CS-like -5.0j
S21
-0.5j -2.0j
S12 ´ 15
180 0
4 3 2 1 0 1 2 3 4
-1.0j Magnitude
(a) (b)
Fig. 4.14. Comparison of the simulated S -parameters of the fT -doubler’s small-signal equivalent circuit
representation in its compound (red) and effective common-source-like (blue) forms. (a) S11
(dotted) and S22 (solid) on a 50-Ω Smith chart. (b) Polar plot of the S12 multiplied by 15
(dotted) and the S21 (solid). The simulation spans from 0.1 GHz to 100 GHz.
0 0
In the final step, it is necessary to transform the parallel arrangement rin,e -Cin,e into a
series-connected branch as in Fig. 4.12(b). This can be done by following an analogous
approach as in (4.3)–(4.6), that is [188],
1
rin,e = rin,e
0

1 + Q2p
(4.16)
and
1 + Q2p
Cin,e = Cin,e
0
; (4.17)
Q2
p
where
Qp = ! rin,e Cin,e :
0 0
(4.18)
Moreover, the effect of the voltage divider formed by rin,e -Cin,e on the effective transcon-
ductance needs to be included in the final shape of the common-source-like form of the
fT -doubler depicted in Fig. 4.12(b):
gm,e = gm,e (1 + j
0
! rin,e Cin,e ): (4.19)
In order to validate the followed approach of expressing the small-signal equiva-

lent circuit of the fT -doubler in a CS-like form, a comparison of the simulated
S -parameters of the both circuits shown in Fig. 4.12 shall be performed. The val-
ues of the intrinsic parameters are extracted from the 100-nm in-house GaN HEMT
baseline process [108], with gm = 450 mS/mm, Cgs = 0.6 pF/mm, Cds = 0.13 pF/mm,
Cgd = 0.09 pF/mm, rgs = 3 Ω mm, and rds = 31 Ω mm. These values are extracted
for a bias point of VDS = 10 V and ID = 300 mA/mm. Both Q1 and Q2 are assumed as
2 45-μm devices. Again, the extrinsic inductor Lext in Fig. 4.12(a) is neglected, i.e.
treated as a perfect short circuit.
The simulated S -parameters up to 100 GHz of both circuits from Fig. 4.12 are compared
in Fig. 4.14. As can be seen, the results of both circuit representations are in relatively
good agreement, which indicates that the effective CS-like circuit depicted in Fig. 4.12(b)
can provide some qualitative insight into the small-signal performance of the fT -doubler.
Table 4.2. Simulated small-signal parameters of an fT -doubler composed of two 2 45-μm HEMTs with
the analogous parameters of 2 45-μm and 4 45-μm CS devices.
Small-signal fT -doubler Common-source Common-source

parameter (2 2 45 μm) (2 45 μm) (4 45 μm)
rin (Ω) 54.2 33.3 16.7
Cin (fF) 29.5 54 108
rout (Ω) 177.5 343 171.5
Cout (fF) 22.2 11.7 23.4
Cfb (fF) 12.8 8.1 16.2
gm (mS) 39.1 40.5 81
Comparison of the Small-Signal Performance with the Common-Source Topology
As shown above, the fT -doubler topology can be qualitatively described in the small-signal
regime with an equivalent circuit akin to the one often used for the common-source
configuration and depicted in Fig. 4.12(b). These findings provide some compelling
circumstances for a direct comparison of the small-signal performance of both topologies.
Table 4.2 compares the simulated small-signal parameters of an fT -doubler composed of
two 2 45-μm HEMTs with the analogous parameters of 2 45-μm and 4 45-μm CS
devices. Using both common-source transistors for comparison provides a more complete
picture in terms of the evolution of the small-signal quantities of fT -doubler with regard to
a single device that the fT -doubler is composed of (2 45-μm CS), as well as with regard
to a HEMT with an equivalent DC-power consumption (4 45-μm CS) due to a similar
total gate width (TGW) of both structures. The effective small-signal parameters of
the CS-like structure from Fig. 4.12(b), calculated by means of Equations (4.3)–(4.19)
show a weak frequency dependency. The numerical values listed in Tab. 4.2 for the
fT -doubler case are obtained at a frequency of 10 GHz. For the common-source device
cases, the circuit parameters are based directly on the intrinsic properties such that
rin rgs , Cin Cgs , rout rds , Cout Cds , and Cfb Cgd , whereas in the case of the
fT -doubler, equations (4.7)–(4.15) are applied with Rext = 26 Ω. Choosing this value
for Rext will be explained afterwards with Equation (4.24). The numerical values of the
intrinsic parameters, similarly as in Fig. 4.14, are approximately based on the 100-nm
in-house GaN HEMT baseline process [108], with gm = 450 mS/mm, Cgs = 0.6 pF/mm,
Cds = 0.13 pF/mm, Cgd = 0.09 pF/mm, rgs = 3 Ω mm, and rds = 31 Ω mm. These
values are extracted for a bias point of VDS = 10 V and ID = 300 mA/mm.
By looking at the input parameters collected in Table 4.2, it can be noticed that the
input resistance is approximately 63 % and 225 % higher than for the 2 45-μm and
4 45-μm CS devices, respectively. At the same time, the input capacitance of the
fT -doubler is around 45 % lower than for the 2 45-μm CS and 73 % lower than for the
4 45-μm CS. Both effects, that is, the increase of the input resistance and decrease
of the input capacitance of the fT -doubler arise from the series connection of the inputs
of both transistors in the pair, as can seen in Fig. 4.12(a).
On the other hand, when considering the output parameters from Table 4.2, it can be
concluded that the output resistance is only slightly higher, whereas the output capaci-
tance is marginally lower than in the 4 45-μm CS case. Consequently, this relation has
its origin in the fact that the output of the fT -doubler can be approximated by a parallel
connection of both transistors of the pair, as depicted in Fig. 4.12(a).
As can be further found from analyzing Table 4.2, the feedback capacitance of the
fT -doubler is about 58 % higher than for the 2 45-μm CS case, and around 21 % lower
as for the 4 45-μm CS device case. Finally, the small-signal transconductance of the
fT -doubler is slightly lower than that of a 2 45-μm CS and, as already shown in (4.15),
is dominated by the gm -value of the output transistor of the structure (Q2 ).
Furthermore, the afore-performed conversion of the small-signal equivalent circuit of
the fT -doubler from the compound form in Fig. 4.12(a) into the CS-like form seen in
Fig. 4.12(b) enables a straightforward comparison of the intrinsic current-gain cutoff
frequency (fT ) of both topologies. The intrinsic fT is related to the intrinsic electron
transmit time [71], and in case of a field-effect transistor it is often approximated as [189]
fT 2(C gm+ C : (4.20)

gs gd )
After substituting the numerical values from Table 4.2 into (4.20), it can be found that
the intrinsic fT -values are around 104 GHz and 150 GHz for the common-source and
fT -doubler configurations, respectively. This implies that the fT can be raised by 44 %
when the configuration from Fig. 4.11(b) is applied.
As a reminder, the conclusions drawn so far on the small-signal operation of the
fT -doubler, hold only provided that both Q1 and Q2 are equally sized as well as biased at
the same DC-operating point and with further neglecting of the inductor Lext .
Remarks on the Bode-Fano Limit for Input Matching of the fT -Doubler
In Section 3.1.1, the Bode-Fano matching limit is evaluated for a common-source HEMT
case. Due to the above-conducted conversion of the small-signal equivalent circuit of
the fT -doubler from the compound form in Fig. 4.12(a) into the CS-like form seen in
Fig. 4.12(b), the analysis already performed in Section 3.1.1 should be also conveniently
applicable in this case. Since the input of the HEMT is usually the band-limiting factor
(see Section 3.1), only the Bode-Fano limit for input matching will be considered.
Recalling equation (3.9), one can notice that the Bode-Fano bandwidth limit for input
matching of a HEMT is directly proportional to the product (time constant) of its Rin and
Cin (see Fig. 3.1). Simulations show that the impedance that must be presented to the
input of the aforementioned 2 2 45-μm fT -doubler in order to maximize the power

transfer (complex-conjugate matching) at 70 GHz is given as Zin, fT -2
= 13:7 + j 34:3 Ω.
Therefore, the values of the series RC circuit used for modeling the input of a HEMT
in Fig. 3.1, are in this case Rin,fT -2 = 13.7 Ω and Cin,fT -2 = 66.3 fF. On the other hand,
a similar simulation reveals that the according impedance that must be presented to the
input of a 4 45-μm CS transistor at 70 GHz is Zin,CS

= 5:7 + j 12:4 Ω. In result, the val-
ues of the series RC circuit used for modeling the input of this HEMT are Rin,CS = 5.7 Ω
and Cin,CS = 183.2 fF.
It appears that the RC time constant of the fT -doubler is in the above case equal to
Rin,fT -2 Cin,fT -2 = 0.91 ps, whereas the time constant of the common source is equal to
Rin,CS Cin,CS = 1.04 ps. This leads to a potential 14 % matching-bandwidth advantage
of the CS over the fT -doubler, given the same targeted reflection coefficient and center
operating frequency. However, if the center frequency had been increased, a significant
advantage in terms of the Bode-Fano input matching-bandwidth limit would have been
achieved since BWmax,in / f02 in (3.9).
The dominant pole of a common-source small-signal equivalent circuit from Fig. 4.12(b)
can be evaluated using the Miller-effect approximation method [161]. The corresponding
−3 dB cutoff frequency is of the following form [161]
1
f−3 dB
2 rin,e k RS Cin,e + Cfb,e (1 + gm,e rout,e k RL) ; (4.21)
where RS and RL are the source and load resistances, respectively. After solving (4.21)
numerically using the values collected in Table 4.2 and assuming that both the input
and output is typically intended to be matched to 50 Ω, the −3 dB cutoff frequency can
be estimated as 99 GHz for the 2 2 45-μm fT -doubler case and 72.6 GHz for the
4 45-μm CS case. Therefore, the fT -doubler shows in this example an increase of the
dominant pole frequency of about 36 % over the common-source topology.
Including these findings in (3.9) and assuming that the center operating frequency can
be raised correspondingly with the frequency of the dominant pole from (4.21), the
Bode-Fano input matching limit of the 2 2 45-μm fT -doubler shows an approximately
two-fold advantage over the 4 45-μm CS device for the considered technology case.
Moreover, it can be noted that in the above example, the Rin,fT -2 is about 140 %
higher than the respective Rin,CS . Considering the conclusions drawn from Sec-
tions 3.1.2 and 3.1.4, it can be additionally presumed that employing an fT -doubler
topology can also further ease the design of impedance transformation networks due to
a potentially lower discrepancy between the Rin and the lowest characteristic impedance
of transmission lines feasible in modern MMIC processes (see Section 3.1.4). This should
effect in a lower Q-factor resulting from the =4-transformation as can be deduced from
(3.12).
Determination of the RL-Values of the Source-Loading Network

As already mentioned at the beginning of this subsection, providing a supplementary DC
path to a reference for the source of Q1 is necessary for realizing a functional fT -doubler
in an FET-based technology variant. One possibility of implementing such a path is the
aforesaid shunt RL-network shown in Fig. 4.11(b) [186, 187].
Besides providing the path for direct-current, this source-loading RL-network can be also
used to improve one of the drawbacks of the classic Darlington topology (which in FET
technology can be approximated with setting Rext to large value), that is, an unequal
current distribution between Q1 and Q2 at low-to-moderate frequencies [186]. This is due
to an unequal input voltage split between both transistors at lower frequencies [186]. In
result, the transistor Q2 provides almost the entire low-frequency output current [186].
This implies a proper sizing of Q2 in order to sustain this current, so that Q2 should
have twice the TGW of the Q1 [186]. Therefore, a Darlington-based amplifier requires
50 % more TGW than a common-source amplifier designed for the same output power
level [186]. This results in a an increased DC-power consumption of the Darlington
amplifier which impairs the circuit’s efficiency [186].
However, the DC and RF drain currents carried by both transistors in the pair can be to
some extent equalized by a proper choice of the values of Rext and Lext [186]. In order
to find the optimum value of the Rext for balancing the drain currents in the fT -doubler
pair, it is helpful to analyze the small-signal equivalent circuit from Fig. 4.12(a) in its
low-frequency simplification, that is, with all capacitors treated as open-circuit and all
inductors as short-circuit elements. From the Kirchhoff’s voltage law (KVL) it can be
noted the input voltage of the composite structure comprises the sum of gate-source
voltages of both transistors, vgs,1 and vgs,2 , respectively, or
vin = vgs,1 + vgs,2: (4.22)
Assuming that the output of the structure is shorted to ground, both gate-source voltages
can be related in the following manner:
vgs,2 = gm,1 vgs,1 (rds,1 Rext):
k (4.23)
In pursuance to ensure equal distribution of the drain currents between Q1 and Q2 and
assuming that both transistors are of same size, it can be concluded that both the input
voltage of the fT -doubler must be distributed equally between both transistors, so that
vgs,1 and vgs,2 are identical. After inserting the relation vgs,1 = vgs,2 into (4.23) and
rearranging the terms, the optimum Rext value for low-frequency drain current balance
is found as
Rext = rds,1 :
gm,1 rds,1 1

(4.24)
Furthermore, in an effort to make the balance of the drain currents sustainable for a
broad range of frequency, the time constant of the Rext Lext -circuit should be less than
or equal to the time constant of the input of Q2 [190], which is dominated by the rgs,2
and Cgs,2 k Cgd,2 . This relation can be approximately expressed as
Lext . r (C + C ); (4.25)
Rext gs,2 gs,2 gd,2
from which, after considering (4.24), the value of the Lext can be determined as
Lext . rds,1 rggs,2 (rCgs,2 +1Cgd,2) :

(4.26)
m,1 ds,1
Evaluating (4.24) and (4.26) numerically with the afore-listed intrinsic parameter val-
ues for an fT -doubler composed of two 2 45-μm HEMTs leads to Rext = 26.6 Ω and
Lext . 55.1 pH.
For the purpose to ascertain the validity of the above analysis, the distribution of the gate-
source voltages as well as the drain currents between Q1 and Q2 is simulated for three
different Rext Lext configurations with the aid of the equivalent circuit from Fig. 4.12(a).
The results are plotted in Fig. 4.15 for a 1-V input test source case.
Provided that the Rext Lext -network is completely discarded, which can be considered as
a classic Darlington case, one can see that, as discussed above, almost the entire low-
frequency input voltage and thus the output current are assigned to Q2 , as shown with
dotted lines in Figs. 4.15(a) and 4.15(b), respectively.
When only Rext of a value given by (4.24) is considered, the low-frequency bal-
ance between gate-source voltages and drain currents of Q1 and Q2 achieved
1.0 50
0.9 with RextLext 45 with RextLext
Gate-Source Voltage (V)
only Rext 40 onlyRext
Drain Current (mA)

0.8
without RextLext without RextLext
0.7 35
0.6 30
0.5 25
0.4 20
0.3 15
0.2 10
0.1 Q1 Q2 5 Q1 Q2
0.0 0
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
(a) (b)
Fig. 4.15. Simulated (a) gate-source voltage and (b) drain current distributions for each HEMT of the
small-signal equivalent circuit of the fT -doubler from Fig. 4.12(a) for different shunt RL-
network configurations. The structure is driven at its input with a 1-V input test source.
(dashed lines in Fig. 4.15). However, with the increasing frequency both quantities are
becoming more discrepant.
Finally, when the Rext Lext -network is fully implemented with the values provided in (4.24)
and (4.26), the gate-source voltage as well as the drain current distributions between
both HEMTs can be considered as approximately uniform over a broad frequency span,
as depicted with solid lines in Fig. 4.15.
Layout-Induced Limitations in Millimeter-Wave Operation
Although several examples of circuits utilizing the fT -doubler topology and realized in
FET-based semiconductor processes have already been reported [185–187, 190–195],
these circuits usually operate below mm-wave frequencies. One of the reasons is the
influence of the parasitic effects associated with the layout of the fT -doubler cell, which
significantly degrades its high-frequency performance [179].
The nodes that are the most influential on the high-frequency performance are the
connection between the source of the first transistor (S1 ) and the the second transistor’s
gate (G2 ) terminals, as well as the connection between the drains of Q1 and Q2 (D1 and
D2, respectively) [179].
The impact of the phase imbalance at the D1 /D2 node on the high-frequency perfor-
mance of the fT -doubler is illustrated in Fig. 4.16. The phase shift between the drain
of Q1 and Q2 is simulated with an ideal transmission line par , as drawn in Fig. 4.16(a).
With the increasing electrical length of this parasitic transmission line, the output sig-
nals of Q1 and Q2 can be no longer considered as in-phase and, as a result, the power
combining efficiency is deteriorated. This effect is depicted in Fig. 4.16(b), where the
simulated MSG/MAG response is plotted for different values of the phase shift (the
phase shift values in the figure are referenced to 50 GHz). As can be noticed, when
increasing the D1 /D2 phase imbalance, the MSG/MAG frequency at which the Rollet’s
20
In G1 Cgd,1 D1 Out 18 D1/D2 phase imbalance ( °)

+ 16 0 20 40
Cgs,1 V
MSG/MAG (dB)
_ 1
14 10 30 50
gm,1V1 rds,1 Cds,1
rgs,1 θ par
12
S1
G2 D2 10
+
_V2 8
Rext Cgs,2
Cgd,2 gm,2V2 rds,2 Cds,2 6
rgs,2 S2 4
Lext
ext. 2
0
10 20 30 40 50 60 70 80 90 100
Frequency (GHz)
(a) (b)
Fig. 4.16. Influence of the phase imbalance between D1 and D2 on the high-frequency performance of the
fT -doubler. (a) Small-signal equivalent circuit indicating the parasitic phase shift. (b) Simulated
MSG/MAG response for different values of the phase imbalance. The phase shift degree values
are referenced to 50 GHz.
stability k -factor is equal to unity is decreasing, which results in significantly less power
gain available from the fT -doubler beyond that point.
Another limiting effect on the high-frequency operation of the fT -doubler is the parasitic
inductance contained within the S1 /G2 signal path [190]. This inductance arises mainly
from the physical wiring used to connect both transistors of the pair and is indicated
as Lpar in the small-signal equivalent circuit of the fT -doubler in Fig. 4.17(a). As can
be seen from Fig. 4.17(a), together with the capacitance associated with the input of
Q2 , the parasitic inductance forms a low-pass filter [190], which can be in some cases a
bottleneck in the high-frequency operation of the fT -doubler circuit. The cutoff frequency
of this low-pass LC -filter can be approximated as follows [190]
1
fc;LC : (4.27)
2 Lpar (Cgs,2 + Cgd,2 )
Similarly as for the phase imbalance at the D1 /D2 node case, the effect of the parasitic
inductance in the S1 /G2 signal path is illustrated with the aid of the simulated MSG/MAG
response for different values of Lpar in Fig. 4.17(b). As seen, the k -factor unity point of
the fT -doubler structure is reduced from about 80 GHz when Lpar is negligible to below
50 GHz for Lpar = 125 pH. To put these inductance values into a broader perspective,
when a hybrid assembly of the fT -doubler using two discrete HEMTs is required, the
parasitic inductance associated with a single bonding wire is about 300 pH [190].
Furthermore, in addition to the low-pass filter created by the combination of Lpar with
the input capacitance of Q2 , also the value of Lext must be adjusted accordingly to
compensate for the altered time constant of the input path of the second transistor [190].
As has been already shown before, this is necessary for ensuring a broadband drain current
balance between both HEMTs of the fT -doubler pair.
20
Cgd,1 18 Lpar (pH)
In G1 D1 Out 0 75
+
V 16
Cgs,1
MSG/MAG (dB)
_ 1
25 100
gm,1V1 rds,1 Cds,1 14
rgs,1 50 125
12
S1
G2 D2 10
Lpar +
_V2
Cgd,2 8
Rext Cgs,2
gm,2V2 rds,2 Cds,2 6
rgs,2 S2 4
Lext
ext. 2
0
10 20 30 40 50 60 70 80 90 100
Frequency (GHz)
(a) (b)
Fig. 4.17. Influence of the parasitic inductance in the S1 /G2 path on the high-frequency performance of
the fT -doubler. (a) Small-signal equivalent circuit indicating the parasitic Lpar . (b) Simulated
MSG/MAG response for different values of Lpar .
An AC-Coupled fT -Doubler
The above-presented analysis of the fT -doubler topology has so far assumed that the
source of the first transistor (S1 ) is directly connected to the second transistor’s gate
(G2 ). This implies identical DC potentials on both S1 and G2 . However, in normally-on
semiconductor technologies (such as the GaN HEMT utilized in this work) this arrange-
ment can lead to sub-optimal bias conditions of Q2 .
Assuming that the source of Q1 is connected (through the RL-network) to the same
reference DC potential as the source of Q2 and that the drain-source bias is positive,
the gate-source bias of Q2 (VGS,2 ) will result in a positive value due to the voltage
drop on the external resistor, which can be simply expressed as VS,1 = VG,2 = ID,1 Rext .
This will effect in Q2 operating beyond its peak transconductance bias, which can be
critical due to the fact the gm -value of the second transistor sets the effective gm of
the complete structure as shown in (4.15). As seen from the transfer-characteristic
measurements of the baseline variant of the used 100-nm GaN HEMT technology at a
fixed drain-source voltage of 10 V, shifting the VGS from the gm -peak bias point (about
−2 V) to 1 V can result in a drop of the gm value from approximately 450 mS/mm
to around 125 mS/mm [108], or by 72 %. Accordingly, an in-house development of
a bias-dependent small-signal model for this technology variant revealed that for the
aforementioned VGS shift the Cgs decreases by around 25 %, Cds drops by roughly 20 %,
Cgd increases by about 120 %, rds declines by approximately 20 %, and rgs grows by almost
150 %. Additionally, a positive VGS,2 value allows for a lower voltage swing at the gate
of Q2 before the structure runs into compression due to the forward conduction onset
of the gate diode [196].
Alternatively, the reference DC potential chosen for the source of Q1 can be more neg-
ative in respect to the one of Q2 , so that the VGS,2 can be tuned in an optimal manner.
However, this requires adding an additional bias potential to the circuit and increases the
wiring complexity of the complete MMIC.
D1 In G1 Cgd,1 D1 Out
G1 +
Cgs,1 V

_ 1
Cblock D2 gm,1V1 rds,1 Cds,1

Q1 S1 G2
Q2 rgs,1
S1
G2 D2
Lext S2
+
_V2
Rbias Rext Cblock Cgs,2
Cgd,2 gm,2V2 rds,2 Cds,2
Rbias rgs,2 S2
Rext G2 Lext
Bias ext.
(a) (b)
Fig. 4.18. (a) Schematic and (b) small-signal equivalent circuit of the AC-coupled fT -doubler.
In such case, separating the DC potentials between S1 and G2 with a capacitor can
be advantageous [187]. This results in an AC-coupled fT -doubler topology which is
schematically illustrated in Fig. 4.18(a). Such an AC-coupled approach allows for biasing
the second HEMT independently, for example through an external resistor. Hence, both
transistors can operate in desired conditions, for instance, at their peak gm bias points.
Moreover, having the possibility to apply a negative bias at G2 should allow for a higher
voltage swing at this terminal before the gate diode of Q2 opens. This should result in
a later compression of the whole structure.
However, a drawback of the AC-coupled approach is that it is not suitable for operation
at low frequencies. This is due to the presence of the blocking capacitor, which together
with the resistance within the G2 bias path forms a high-pass filter, as seen from the
small-signal equivalent circuit in Fig. 4.18(b). The cutoff frequency of this filter can be
approximated by
1
fc ,AC 2 R C : (4.28)
bias block
At low frequencies, the gain of the fT -doubler cell is significantly reduced since the
transistor Q2 does not fully contribute to the output RF-power.
A simulated small-signal performance comparison of the fT -doubler in its AC-coupled
and DC-coupled versions is shown in Fig. 4.19. For the AC-coupled case, the additional
RC elements are chosen as Rbias = 100 Ω and Cblock = 135 fF, which results in a high-
pass cutoff frequency of around 11.8 GHz. When all of transistors in the structure are
biased with a gate-source voltage at their peak gm -points, the low-frequency gain of the
AC-coupled fT -doubler is, as predicted, substantially lower. The low-frequency difference
of the S21 magnitude in Fig. 4.19(a) is around 6 dB (voltage-ratio quantity), whereas
the MSG is approximately 3 dB lower (power-ratio quantity) as depicted in Fig. 4.19(b).
This observation partially confirms the aforesaid presumption that Q2 provides little
contribution to the to the output RF-power of the AC-coupled fT -doubler at the low-
frequency operation end. One can also notice that beyond the above-calculated cutoff
frequency (11.8 GHz) the gain responses of the AC-coupled fT -doubler start to converge
with the increasing frequency towards the optimally-biased DC-coupled case.
16 30
14 AC-coupled, VGS,2 @ gm,peak 27
DC-coupled, VGS,2 @ gm,peak
12 24
DC-coupled, VGS,2 = 1 V
MSG/MAG (dB)
10 21
S21 (dB)
8 18
6 15
4 12
2 9
AC-coupled, VGS,2 @ gm,peak
0 6 DC-coupled, VGS,2 @ gm,peak
-2 3 DC-coupled, VGS,2 = 1 V
-4 0
0 10 20 30 40 50 60 70 80 90 100 1 10 100
(a) (b)
Fig. 4.19. Simulated small-signal performance comparison of an AC-coupled fT -doubler and a DC-coupled
fT -doubler for two gate-source voltages of Q2 . (a) S21 and (b) MSG/MAG responses. Q1 is
assumed to operate at its gm -peak point in each case.
However, when considering the aforementioned small-signal parameter degradation due

to the shift of the VGS,2 (i.e., a more realistic scenario), the small-signal performance of
the DC-coupled fT -doubler is significantly deteriorated, especially at higher frequencies,
as shown in Fig. 4.19 with blue lines for VGS,2 = 1 V (Q1 is assumed to operate still at
its gm -peak point).
4.2.3 Millimeter-Wave fT -Doubler: A Novel Integrated Layout

Approach
As has been already noted before, several approaches to fT -doubler amplifiers in FET-
based technologies are described in the literature [185–187, 190–195]. The listed prior
works include designs using both, hybrid assembly methods, where each transistor of
the pair is placed on a separate die and the interconnections along with the RL-
networks are implemented on an auxiliary carrier substrate (off-chip) [190, 191], as well
as monolithically integrated, single-chip solutions, where the routing is realized on chip
[185–187, 192–195]. Although utilizing the monolithically-integrated approach, from ex-
amining the chip layouts provided in [185–187, 192–195] it appears that both FETs of
the fT -doubler pair can be still considered as discrete (separate) transistors. Therefore,
still some on-chip wiring is required to connect each other in a proper manner. De-
pending on the back end of line (BEOL) properties and the associated design rules of
the utilized process, these on-chip interconnections can introduce parasitic effects that
severely impact the high-frequency operation of the circuit. This is potentially one of
the main reasons why none of the FET-based fT -doubler amplifiers reported to date is
able to operate well through the millimeter-wave frequencies.
Considering the conclusions from the prior works briefly reviewed above as well as the
remarks provided in Section 4.2.2 on the layout-induced parasitic effects and their limiting
impact on the high-frequency performance of the fT -doubler topology, it is essential to
G2 Bias
Gate finger
Thin-film
resistor
Thin metal
Airbridge
Thick metal
MIM capacitor
IN OUT IN OUT
(G1) (D1+D2) (G1) (D1+D2)
G2 Bias
(a) (b)
Fig. 4.20. Proposed integrated layout approach to an fT -doubler cell in its (a) DC-coupled and
(b) AC-coupled variants.
develop a layout concept of the fT -doubler cell that will enable its usage also at mm-wave
frequencies.
In order to achieve a high-frequency operation of the fT -doubler, it is necessary to mini-
mize the layout-induced parasitics associated with this topology. As has been identified
in [179] and Section 4.2.2, the nodes that are the most influential on the high-frequency
performance are the connection between the source of the first transistor (S1 ) and the the
second transistor’s gate (G2 ) terminals, as well as the connection between the drains of
Q1 and Q2 (D1 and D2 , respectively). To avoid high-frequency performance degradation
of the structure, the electrical length of these connections should be minimized [179].
The proposed integrated layout approach to a DC-coupled fT -doubler cell is shown in
Fig. 4.20(a), whereas an AC-coupled integrated layout is drawn in Fig. 4.20(b). The
layouts comprise multi-finger HEMTs, where both Q1 and Q2 are two-finger devices.
In both cases, the parasitic reduction at the D1 =D2 node is realized by using a shared
active area for D1 and D2 . As a result, the interconnection parasitics at this node are
eliminated.
The connection between the source of the first transistor and the second transistor’s
gate of the AC-coupled fT -doubler is realized with a trace using the MET1 as shown in
Fig. 4.20(a), where the length of the trace is limited by the design rules of the process.
In case of the AC-coupled variant, the S1 =G2 interconnection is DC-separated with an
MIM-capacitor indicated in Fig. 4.20(b). The top plate of the capacitor is connected
with an airbridge to S1 , whereas the G2 connection is routed using the bottom-plate
metalization layer (MET1) in a similar manner as in the DC-coupled case. The bias
lines of the Q2 -gates are realized with airbridges crossing over the ground plane. This
feature makes the layout compliant with the CPW environment. Applying this layout
approach in a MSL environment is even more straightforward, as no additional ground-
plane crossovers are necessary.
4.2 Millimeter-Wave Integrated T -Doubler Topology 89
In both layout variants, the source of is connected to the ground using a trace on
both metalization layers, which realizes the inductance, in series with a thin-film resistor.
Manipulating the width and length of this structure can help achieving the desired values
of the shunt -network for optimum operation. Integrating all of the -elements in
the close proximity of the active HEMT area in this layout approach results in a device
with a footprint comparable to a common-source HEMT of equal total gate width.
Besides the reduced parasitics, the aforementioned compact footprint and convenient
compatibility with CPW and MSL passive environments are further factors in favor of
employing this layout approach in mm-wave MMIC designs.
The integrated T -doubler layout concepts described in this section and shown in Fig. 4.20
are subject to German and U.S. patent application filings [P8, P13].
4.2.4 Experimental Evaluation of the Integrated AC-Coupled

T -Doubler
A micrograph of the fabricated AC-coupled T -doubler test cell is shown in Fig. 4.21. In
this case, and are both equally sized as -μm HEMTs. A wafer mapping of
the short-circuit current gain ( ) of 30 processed T -doubler test cells is provided in
Fig. 4.22(a). In order to benchmark the performance of this structure, a similar mapping
of a -μm common-source HEMT is shown as a reference. The sizing of the CS
HEMT is selected to result in the same total gate width as in the T -doubler case to
provide an equivalent comparison in terms of the footprint and power consumption.
The T -doubler provides approximately 6 dB more than the CS HEMT at 100 GHz.
Considering the typical slope of this parameter versus the frequency, i.e., −6 dB per
octave [197], it can be concluded that the T -doubler can provide a two-fold improvement
of the T over the CS HEMT. The lower for frequencies below 20 GHz can be
associated with the impact of the high-pass filter formed through the connection of
the integrated blocking capacitor (135 fF) with the resistance within the bias path
(100 Ω), as discussed in Section 4.2.2.
A wafer mapping measurement of the MSG/MAG of both topologies is plotted in
Fig. 4.22(b). Although showing a lower power gain than the CS HEMT at low fre-
quencies, the T -doubler can provide a higher gain beyond 80 GHz. The low-frequency
power gain deficit of 2 dB with respect to the CS HEMT is related to the lower voltage
Fig. 4.21. Micrograph of the fabricated -μm integrated AC-coupled T -doubler test cell.
40 20
35 fT -doubler 18 fT-doubler
30 CS HEMT 16 CS HEMT
MSG/MAG (dB)
14
25
h21 (dB)
12
20 10
15 8
6
10
4
5 2
0 0
1 10 100 10 20 30 40 50 60 70 80 90 100 110
(a) (b)
Fig. 4.22. Wafer mapping of the (a) h21 and (b) MSG/MAG of a fabricated 2 2 45-μm integrated
AC-coupled fT -doubler (red). A 4 45-μm CS HEMT is used as a reference (blue). Shown
are 30 cells per topology. VD = 15 V and ID = 300 mA/mm.
gain of the fT -doubler due to an inferior effective transconductance per total gate width,
as shown with Equation 4.15.
Layout Impact on the High-Frequency Performance of the fT -Doubler
In Section 4.2.2, the impact of the layout-induced parasitic effects on the mm-wave
performance of the fT -doubler topology has been discussed. However, besides the “inner"
parasitic effects mentioned in Section 4.2.2 which can compromise the high-frequency
performance, also the layout arrangement of the extrinsic RL-network plays a substantial
role in optimizing the ultimate efficacy of the fT -doubler.
In order to provide an illustration to the above statement, the measured small-signal
performance of two nearly-alike layout variants of the fT -doubler cell shown in Fig. 4.23
are compared with each other. The baseline layout variant “A" from Fig. 4.23(a) has been
already evaluated before (see Fig. 4.22). The layout variant “B", drawn in Fig. 4.23(b),
differs from the variant “A" mainly due to the location of the RL-network. In the
“A"-variant case, the RL-network is located at the input side of the fT -doubler, whereas
for the “B"-variant case, this network is moved towards the output side, next to the DC-
blocking MIM capacitor. This modification can be considered as rather subtle at first.
However, locating the RL-network together with the MIM capacitor at the output side
extends the distance between the active drain areas and the output port of the structure
in order to stay in compliance with the design rules of the process. This in turn results
in an increase of the extrinsic drain access inductance and losses, arising from the longer
airbridge connection.
A wafer mapping of the h21 and MSG/MAG responses of 30 processed fT -doubler cells
for both layout variants is plotted in Fig. 4.24. Again, a 4 45-μm CS HEMT serves
as a reference. It can be seen in Fig. 4.24(a) that the measured h21 responses of both
layout variants start to diverge from each other at around 40 GHz, resulting in about
G2 Bias G2 Bias
Gate finger
Thin-film
resistor
Thin metal
Airbridge
Thick metal
MIM capacitor
IN OUT IN OUT
(G1) (D1+D2) (G1) (D1+D2)
Variant
G2 Bias
"B"
G2 Bias
(a) (b)
Fig. 4.23. Integrated AC-coupled fT -doubler cell in two layout variants. (a) Variant “A" and
(b) variant “B".
2-dB magnitude difference at 100 GHz in favor of the baseline “A" variant. Considering
the MSG/MAG response from Fig. 4.24(b), one can note that “B"-variant layout is able
to provide significantly less power gain beyond 70 GHz in comparison with the baseline
“A" variant. The slightly lower value of the MSG for the “B"-variant case is due to
higher parasitic losses of the longer airbridge connection at the output side of this layout
variant.
The experimental evaluation of the small-signal performance between two different layout
implementations marks the importance of careful consideration of the layout choices and
the resulting performance trade-offs when employing this topology in mm-wave MMICs.
40 20
35 fT-doubler, var. "A" 18 -doubler, var. "A"
fT
fT-doubler, var. "B" -doubler, var. "B"

16 fT
30
CS HEMT
MSG/MAG (dB)
14 CS HEMT
25
h21 (dB)
12
20 10
15 8
6
10
4
5 2
0 0
1 10 100 10 20 30 40 50 60 70 80 90 100 110
(a) (b)
Fig. 4.24. Wafer mapping of the (a) h21 and (b) MSG/MAG of a fabricated 2 2 45-μm integrated
AC-coupled fT -doubler in variants “A" (red) and “B" (green). A 4 45-μm CS HEMT is used
as a reference (blue). Shown are 30 cells per topology. VD = 15 V and ID = 300 mA/mm.
(a) (b)
Fig. 4.25. Micrograph of the three-stage T -doubler amplifier MMICs. (a) AMP1 ( mm ).
(b) AMP2 ( mm ).
4.2.5 Broadband Amplifiers Employing the Integrated T -Doubler
In order to demonstrate the potential of the T -doubler topology using the novel in-
tegrated layout approach for broadband MMIC applications, two amplifiers able to
cover several mm-wave waveguide bands were designed. Each circuit comprises three
reactively-matched -μm T -doubler stages (in layout variant “A"). The mi-
crographs of the fabricated MMICs are shown in Fig. 4.25(a) (AMP1) and Fig. 4.25(b)
(AMP2).
The matching networks are realized in a CPW environment with a ground–ground spacing
of 50 μm. During the design phase, measured and de-embedded -parameters of the
T -doubler test cell were directly used in combination with the passive CPW process
design kit. The stability of the circuit was simulated using the 4-Gamma method [131].
Small-Signal Performance
The on-wafer -parameter measurements were performed up to 110 GHz with an

HP8510-XF VNA. A small-signal wafer mapping of 11 samples of the AMP1 circuit
is shown in Fig. 4.26(a). This amplifier can deliver more than 13 dB of small-signal
gain over a 26–71-GHz band. This is equivalent to a fractional operating bandwidth
of 92.8 % (1.45 octaves). The small-signal gain of the second amplifier is better
than 10 dB from about 28 GHz to 90 GHz, as presented in Fig. 4.27(a). This corre-
sponds to a fractional operating bandwidth of 105 % or 1.68 octaves. As a result, the
amplifiers are able to provide a full coverage of several mm-wave waveguide bands,
including the Ka-band (26.5–40 GHz), Q-band (33–50 GHz), U-band (40–60 GHz),
V-band (50–75 GHz), and the E-band (60–90 GHz). The small-signal measurement re-
sults show a reasonable agreement with the simulations.
Large-Signal Performance
The on-wafer scalar CW power measurements over the 26–90-GHz band were performed
with an Agilent E8257D analog signal generator cascaded with a set of custom power
amplifier and multiplier modules connected at the input side, and a Keysight U8488A
power sensor connected to the output. Losses in the probe tips were removed in a
calibration process. An on-wafer CW mapping of 11 samples of the AMP1 circuit
25 22
S21 S11 S22 20
Pout (dBm), Gain (dB), PAE (%)

20
18
15
16
S-parameters (dB)
10 14 Pout Gain PAE

5 12
0 10
8
-5
6
-10
4
Meas.
-15 2
Sim.
-20 0
10 20 30 40 50 60 70 80 90 100 25 30 35 40 45 50 55 60 65 70
(a) (b)
Fig. 4.26. Measurement results of 11 samples of the fT -doubler AMP1 amplifier. (a) Measured (solid)
and simulated (dashed) S -parameters (VD = 10 V and ID = 250 mA/mm). (b) Measured CW
frequency response for a constant Pin = 10 dBm (VD = 12.5 V and ID = 400 mA/mm).
for a constant Pin = 10 dBm is depicted in Fig. 4.26(b). This amplifier can provide
from 16 dBm to 21.2 dBm of output power over a 26–70-GHz band, with an average
value of 19 dBm. The respective PAE is ranging from 1 % to 4.5 %. The large-signal
performance of the AMP2 amplifier driven with a constant Pin = 8 dBm is plotted in
Fig. 4.27(b). In this case, the output power ranges from around 14.5 dBm to 20.6 dBm
between 30 and 90 GHz, with an average value of 17.5 dBm. The PAE of the AMP2
circuit spans from 1 % to 4.4 % over the operating band.
25 22
S11 S21 S22 Pout
Pout (dBm), Gain (dB), PAE (%)
20 Gain
20
Meas. Sim. 18 PAE
15
S-parameters (dB)
16
10 14
5 12
0 10
-5 8
6
-10
4
-15 2
-20 0
10 20 30 40 50 60 70 80 90 100 30 35 40 45 50 55 60 65 70 75 80 85 90
(a) (b)
Fig. 4.27. Measurement results of the fT -doubler AMP2 amplifier. (a) Measured (solid) and simulated
(dashed) S -parameters (VD = 10 V and ID = 350 mA/mm). (b) Measured CW frequency re-
sponse for a constant Pin = 8 dBm (VD = 12.5 V and ID = 350 mA/mm).
Table 4.3. State-of-the-art FET-based Darlington and fT -doubler amplifiers.
Reference Topology Technology Frequency (GHz) jS21 j (dB) Pout (dBm)

this work
fT -doubler GaN HEMT 26–71 13–19 16–21.2
(AMP1)
this work
fT -doubler GaN HEMT 28–90 10–19 14.5–20.6
(AMP2)
[185] Darlington GaAs pHEMT 1.5–29.5 17–18 4.5–15.3
[187] fT -doubler GaAs MESFET 0.2–5 – 23–25
[187] fT -doubler GaN HEMT 0.2–7.5 9–13 29–33
[190] fT -doubler GaN HEMT 6.5–10.4 10 38–40.3
[191] fT -doubler GaN HEMT 0.3–4 9–12 30
[192] Darlington GaN HEMT 0.05–19 11 31.5–32
[193] Darlington GaAs pHEMT 0–29.8 10 10.2
[194] Darlington Si CMOS 18–33 14–16 16–19.5
[195] fT -doubler GaN HEMT 0–50 5.5–11 16.5–18.7*
* output third-order intercept point value
Comparison with the State of the Art
Table 4.3 collects the reported FET-based amplifiers using the Darlington or fT -doubler
topologies. It can be noted that all of the circuits are able to provide significant band-
widths, which confirms the broadband potential of the fT -doubler topology. However,
none of the amplifiers reported to date is able to operate at such high frequencies.
The compact approach described in this part of the thesis allows for minimizing the
layout-induced parasitic effects, which enables operation at millimeter-wave frequencies.
As a result, the amplifiers presented in this section are the first demonstration of FET-
based integrated fT -doubler circuits operating above 50 GHz.

This chapter has discussed enhancing the performance of mm-wave GaN power amplifiers
by employing different transistor topologies. In particular, the main focus has been put
on increasing the high-frequency gain of the amplifier with cascode configuration and
optimizing the bandwidth performance with an fT -doubler pair.
The improved reverse isolation of the cascode results in a significantly higher MSG of
this topology when compared with the common-source configuration (see Section 4.1.1).
Therefore, the cascode topology appears as an appealing alternative for applications
in GaN power amplifiers operating at the higher mm-wave bands, where the available
gain of GaN HEMTs is limited. However, appropriate measures have to be taken in
order to ensure in-band stability of cascode-based amplifiers, since the cascode suffers
from a typical phenomenon where the magnitude of S22 is exceeding unity above a
certain frequency, resulting in a potentially instable device at higher frequencies (see
Section 4.1.1).
In order to demonstrate the attractiveness of the cascode topology and its feasibility in
high-frequency GaN-based circuits, a power amplifier able to cover a significant part of
the D-band (110–170 GHz) was designed (see Section 4.1.3). The four-stage cascode
power amplifier can cover the 107–148-GHz band with more than 25-dB of small-signal
gain. Over the 120–145-GHz band, it can deliver on average 23.3 dBm of output power
and 5.2 % of PAE. The 120-GHz peak values of the output power and power-added
efficiency are 26.4 dBm and 16.5 %, respectively, with transducer gain exceeding 26 dB
at saturation. The combination of the small- and large-signal parameters of this ampli-
fier establishes new benchmarks for solid-state power amplifiers operating at such high
frequencies.
Alternatively to the passive networks design considerations provided in Chapter 3, a wide-
band performance can be achieved also by employing more advanced transistor topolo-
gies, such as the Darlington pair or the fT -doubler, which both enhance the current gain
of transistors in the utilized semiconductor process. However, applying these topologies
at mm-wave frequencies is a challenging task due to the layout-induced parasitic effects
that degrade the high-frequency performance (see Section 4.2.2).
In section Section 4.2.3, an fT -doubler topology employing a novel integrated layout
based on GaN HEMTs is described, together with an experimental evaluation of its
performance shown in Section 4.2.4. The compact approach described in this part of the
thesis allows for minimizing the layout-induced parasitic effects, which enables operation
at millimeter-wave frequencies. As a result, the amplifier presented in this section is
the first demonstration of an FET-based integrated fT -doubler circuit operating at such
high frequencies. The development of the integrated fT -doubler layout concept described
there is subject to German and U.S. patent application filings [P8, P13].
In order to demonstrate the potential of the fT -doubler topology using the novel inte-
grated layout approach for broadband MMIC applications, two amplifiers able to cover
several mm-wave waveguide bands were designed and described in Section 4.2.5. These
amplifiers are able to provide a full coverage of several mm-wave waveguide bands, in-
cluding the Ka-band (26.5–40 GHz), Q-band (33–50 GHz), U-band (40–60 GHz), V-band
(50–75 GHz), and the E-band (60–90 GHz).
97
5 Layout Considerations for G-Band

GaN Amplifiers
Due to the combination of its physical parameters such as high breakdown voltage and
high saturated electron velocity [71], GaN could potentially be the material of choice
for high-power MMICs operating at the complete mm-wave spectrum, also at its higher
end. However, despite the rapid advance in GaN HEMT technology [11–14], the re-
ported available gain of the devices is still limited at higher mm-wave frequencies in com-
parison to the competing high-speed semiconductor processes, such as indium gallium
arsenide (InGaAs) mHEMT [15], InP HEMT [16], InP HBT [17], SiGe HBT [18, 19],
or Si CMOS [20]. This is one of the main reasons why only few GaN amplifiers op-
erating above 100 GHz have been reported so far [21–26]. Therefore, the transistor’s
high-frequency gain has to be considered as one of the most precious resources of the
performance budget.
One of the possible solutions to increase the high-frequency gain of the HEMTs is to
employ different transistor topologies, such as the cascode configuration discussed in Sec-
tion 4.1. Alternatively, one an also significantly improve the mm-wave gain of common-
source HEMT already on transistor by means of optimizing its layout. Moreover, using
proper device dimensioning approaches can lead to less complex matching network de-
sign requirements for transforming the GaN-specific impedance levels. Finally, in order
to achieve high values of gain on the circuit level, many stages need to be usually cas-
caded. Therefore, scaling of the passive networks is necessary to enable compact yet
high-performance GaN MMICs operating beyond the 200-GHz mark.
This chapter discusses the aforementioned concepts in detail. Implementing them on
MMIC-level allowed for demonstrating amplifiers operating within the complete G-band
(140–220 GHz) frequency spectrum and advancing the performance of GaN-based cir-
cuits beyond the 200-GHz frontier.
5.1 Geometry-Based High-Frequency Gain

Enhancement of GaN HEMTs
Chapter 4 has specified methods of improving the mm-wave gain of GaN power amplifiers
by optimizing multi-transistor topology configurations, such as the cascode or fT -doubler.
In this section, the focus is switched to optimizing the high-frequency performance of
GaN HEMTs in the basic common-source configuration by customizing its geometrical
properties. This can be achieved by modifying the internal layout of the transistor as
well as choosing a proper gate width in order to facilitate the design of the impedance
matching networks of high-frequency GaN amplifiers.
98 5 Layout Considerations for G-Band GaN Amplifiers
5.1.1 Transistor Layout Considerations for G-Band GaN Amplifiers

Besides selecting the unit gate width (UGW) and the number of fingers of the transistor
(dimensioning of GaN HEMTs is discussed in Section 5.1.3), the other geometrical degree
of freedom available for the designer is choosing the spacing distances between the tran-
sistor’s terminals, in particular the gate-source spacing (LGS ) and the gate-drain spacing
(LGD ). A simplified cross-section of a GaN HEMT device is sketched in Fig. 5.1(a),
where both spacings are indicated together with the gate length (LG ).
The corresponding intrinsic small-signal equivalent circuit elements of a high-frequency
HEMT model are displayed in Fig. 5.1(b). The choice of the transistor’s terminal spac-
ings (i.e., LGS and LGD ) will have an effect on the values of the equivalent circuit elements
and on the resulting device performance. In the remainder of this section, the influence
of these circuit elements on the transistor’s RF performance (expressed by some com-
mon figures of merit) is investigated. Next, in Section 5.1.2, the dependence of these
parameters is experimentally verified over a broad bias range for two transistor layout
cases.
The small-signal equivalent circuit elements from Fig. 5.1(b) can be expressed in a more
familiar form of an intrinsic common-source (CS) HEMT model shown in Fig. 5.2 [108].
This model is simplified in a way that the time delay term of the intrinsic transcon-
ductance is neglected. The two-port device model from Fig. 5.2 can be described with
its admittance matrix, so that the following relation holds:

I1 Y11 Y12 V1
=I2 Y21 Y22: V2 (5.1)
The individual Y -parameters can be calculated directly from analyzing the schematic in
Fig. 5.2 as [198, 199]

I1 j!Cgs j!Cgd
Y11 = + ; (5.2)
V1 V2 =0 1 + j!rgs Cgs 1 + j!rgd Cgd

I1 j!Cgd
Y12 = ; (5.3)
V2 V1 =0 1 + j!rgd Cgd
SiN SiN
Gate Gate
Source Drain Source Drain
LGS LG LGD rgs Cgs Cgd rgd
gm
Cds
rds
HEMT active layers HEMT active layers
Substrate Substrate
(a) (b)
Fig. 5.1. Simplified cross-section overview of a GaN HEMT device indicating the (a) gate-source and
gate-drain spacings and the (b) corresponding intrinsic small-signal equivalent circuit elements.
5.1 Geometry-Based High-Frequency Gain Enhancement of GaN HEMTs 99
I1 Cgd rgd I2
+
Cgs V
_ i
V1 gmVi rds Cds V2

rgs
Fig. 5.2. Small-signal equivalent circuit model for a CS HEMT. The time delay term is neglected.

I2 gm j!Cgd
Y21 V1 V2 =0
= 1 + j!r 1 + j!rgd Cgd
; (5.4)
gs Cgs
and
I2 j!Cgd
Y22
V2 V1 =0
= gds + j!Cds +
1 + j!rgd Cgd
; (5.5)
where
1
gds = : (5.6)
rds
The impact of the circuit elements on the high-frequency performance of the cir-
cuit from Fig. 5.2 is evaluated with the aid of three small-signal figures of merit,
that is, the current-gain cutoff frequency (fT ), the maximum frequency of oscil-
lation (fmax ), and the maximum stable gain (MSG) at 100 GHz. As shown later
on, these quantities can be directly calculated from the Y -parameters given in
(5.2)–(5.5). For any numerical evaluations, the values of the particular elements are
assumed as gm = 530 mS/mm, Cgs = 600 fF/mm, Cds = 140 fF/mm, Cgd = 65 fF/mm,
rgs = 1.7 Ω mm, rgd = 1.9 Ω mm, and rds = 45 Ω mm. These values are extracted ac-
cordingly to the relations provided in (5.32)–(5.38) from a measurement at 10 GHz of
a 4 45-μm GaN HEMT biased at VDS = 10 V and ID = 300 mA/mm.
Current-Gain Cutoff Frequency (fT )
The current-gain cutoff frequency (fT ) is one of the most commonly referenced figures
of merit when benchmarking semiconductor process nodes for RF applications. The
intrinsic fT is related to the intrinsic electron transmit time [71], and it is defined as
the frequency at which the small-signal short-circuit current gain (h21 ) of the CS device
reduces to unity [6]. The h21 is defined as the ratio of the output and input currents
with the output port short-circuited [161], that is,

I2 Y21
h21 = : (5.7)
I1 V2 =0 Y11
Substituting (5.2) and (5.4) into (5.7) yields in

2 2 !gm rgd Cgd )2
jh21j = YY21 = (g!m 2+(!C rgs+CCgsC)gd2 )+ +!2(C!C
2 2
gd
2
: (5.8)
11 gs gd gs Cgd (rgs + rgd )
0.0 1.0
Short-Circuit Current Gain (dB)
0.8
h21 (rigorous) -2.5
0.6
0.4
Relative Error (%)
Sensitivity ( -)
Error
-5.0
0.2
-7.5
0.0
-0.2
-0.4
-10.0
-0.6
fT
-12.5
-0.8
-15.0
-1.0
Frequency (GHz) gm Cgd Cgs Cds rgd rgs gds
(a) (b)
Fig. 5.3. Analytic investigation of the fT sensitivity of a HEMT. (a) Numerical comparison of the rigorous
(dashed) expression for h21 from Eq. (5.8) and its simplified version (solid) from Eq. (5.9) with
the corresponding error. (b) Numerical sensitivity of the fT to the small-signal equivalent circuit
elements.
By assuming that gm
! 2 rgs Cgs Cgd , (Cgs + Cgd )2 ! 2 Cgs
2 C 2 (r + r )2 , and g r
gd gs gd m gd 1,
the rigorous expression from (5.8) can be approximated to:
jh j = ! (C g + C
21
gs
m
gd )
=
gm
2f (Cgs + Cgd )
: (5.9)
The numerical evaluation of the rigorous expression from (5.8) and its simplified version
(solid) from (5.9) for the aforementioned intrinsic parameter values is plotted together
with the corresponding error in Fig. 5.3(a). As can be noted, the error introduced by the
simplification performed in (5.9) is lower than 7.5 % until the h21 reaches unity or 0 dB.
j j
When noting that fT : h21 (fT ) = 1, the current-gain cutoff frequency can be expressed
in its familiar form [189], given previously in (4.20):
fT = 2 (Cg + C m
: (5.10)
gs gd )
In order to evaluate the impact of the particular intrinsic element on the fT value, a
sensitivity analysis can be performed. The relative sensitivity of the parameter p to
element x (Sxp ) is defined as [200, 201]
@p
Sxp p
@x
=
@p x
@x p
: (5.11)
x
Therefore, after applying (5.11) to (5.10), the relative sensitivities of the fT to gm , Cgs ,
and Cgd are given as
SgfTm @g@f gf
T
m
m
T
=
2 (Cgs + Cgd
1
)
gm
gm = 1; (5.12)
2 (Cgs + Cgd )
@fT Cgs Cgs

SCfT
gs
@C f = Cgs + Cgd
; (5.13)
gs T
and
@fT Cgd Cgd
SCfTgd @C f = Cgs + Cgd
; (5.14)
gd T
respectively. The numerical evaluation of the sensitivity expressions from (5.12)–(5.14)

for the above-listed intrinsic parameter values is provided in Fig. 5.3(b). It can be con-
cluded that the fT value is directly proportional to the gm value and inversely proportional
tp the sum of Cgs and Cgd values. Since Cgs is usually much larger than Cgd , the gate-
source capacitance dominates in this relation and is the main limiting factor of achieving
high fT values, as seen in Fig. 5.3(b).
Maximum Frequency of Oscillation (fmax )
The second commonly referenced figure of merit within the RF community is the maxi-
mum frequency of oscillation (fmax ). It is the highest frequency at which an active device
can still provide any power gain [202]. It is often defined as the frequency at which the
unilateral power gain (U ) approaches unity [6]. The unilateral power gain, also known
as the Mason’s invariant [203], is the maximum power gain that can be obtained from
an active two-port network after it has been made unilateral with the help of a lossless
and reciprocal embedding network, which provides the required feedback [203, 204]. The
unilateral power gain of a two-port network can be expressed by means of its admittance
parameters as [204]
U=
j Y21 Y12 j2
:
4 Re(Y11) Re(Y22) Re(Y12) Re(Y21) (5.15)
The unilateral power gain of the circuit from Fig. 5.2 can be assessed by inserting the
expressions (5.2)–(5.5) into (5.15):
gm 2 (1 + ! 2 r 2 C 2 )
U= :
gd gd
(5.16)
4!2gdsrgsCgs2 +4!2rgdCgd2 gm + gds + !2rgsCgs2 1+ gds(rgd + rgs)
By assuming that gm gds and gds (rgd + rgs ) 1, the rigorous relation from (5.16) can
be simplified to the following form:
2 (1 + ! 2 r 2 C 2 )
U = 2 gm gd gd
:
4! g r C 2 + r C 2 (g + ! 2 r C 2 )
ds gs gs gd gd m gs gs
(5.17)
from (5.17) for the assumed intrinsic parameter values is provided together with the cor-
responding error in Fig. 5.4(a). As can be seen, the error introduced by the simplification
performed in (5.17) is lower than 3 % up to about 200 GHz. Furthermore, noting that
fmax : U (fmax ) = 1 reveals that the fmax can be approximated from (5.17) as
p
gm Cgd (Cgs rgs rgd rgd Cgd ) gds rgs Cgs
2

fmax = :
82rgsCgs2 rgdCgd2 (5.18)
3.5 1.0
0.8
Unilateral Power Gain (dB)
3.0
U (rigorous) 0.6
Sensitivity ( -)
0.4
Relative Error (%)

Error 2.5
2.0 0.2
0.0
1.5
-0.2
1.0 -0.4
max
-0.6
f
0.5
-0.8
0.0
-1.0
(a) (b)
Fig. 5.4. Analytic investigation of the fmax sensitivity of a HEMT. (a) Numerical comparison of the rigorous
(dashed) expression for the unilateral power gain from Eq. (5.16) and its simplified version (solid)
from Eq. (5.17) with the corresponding error. (b) Numerical sensitivity of the fmax to the small-
signal equivalent circuit elements.
Again, investigating the sensitivity of the fmax to the transistor’s intrinsic parameters
can provide insight into their impact on this figure of merit. The relative sensitivity of
the fmax to gm , Cgd , Cgs , rgd , rgs , and gds is found by applying (5.11) to (5.18) and given
as
@fmax gm
p
gm Cgd (rgd Cgd Cgs rgs rgd )
Sgm
fmax
= 2g C (r C C pr r ) + 2g r C 2 ; (5.19)
@gm fmax m gd gd gd gs gs gd ds gs gs
@fmax Cgd
p
Cgs (gm Cgd rgs rgd 2gds rgs Cgs )
SCfmax
gd

@Cgd fmax
=
2gm Cgd (rgd Cgd
p 2
Cgs rgs rgd ) + 2gds rgs Cgs
; (5.20)
@fmax Cgs gm Cgd (Cgs rgs rgd 2rgd Cgd )

p
SCfmax
gs

@Cgs fmax
=
2gm Cgd (rgd Cgd
p 2
; (5.21)
@fmax rgd
p
Cgs (gm Cgd rgs rgd 2gds rgs Cgs )
Srfgd
max

@rgd fmax
=
4gm Cgd (rgd Cgd
p 2
; (5.22)
@fmax rgs gm Cgd (Cgs rgs rgd 2rgd Cgd )

p
Srfgsmax
@rgs fmax
=
4gm Cgd (rgd Cgd
p 2
; (5.23)
and
2
gds rgs Cgs
Sgfmax
ds
@f@gmax fgds = 2 + 2g r C 2
2gm rgd Cgd
p ;
2gm Cgd Cgs rgd rgs
(5.24)
ds max ds gs gs
respectively. The numerical evaluation of the sensitivity expressions from (5.19)–(5.24)

for the aforementioned intrinsic parameter values is shown in Fig. 5.4(b). One can note
that the fmax value is most pronouncedly affected by the gm (positively correlated) and Cgs
(negatively correlated). However, in this case also rgs , gds , and Cgd provide a significant
antagonistic contribution to the fmax value.
Maximum Stable Gain (MSG)
The last investigated figure of merit in this section is the maximum stable gain (MSG),
which is the maximum power gain achievable from a potentially instable two-port after
stabilizing it and applying simultaneous conjugate-complex matching at both ports [205].
It can be also alternatively considered as the measure of the non-reciprocity of a two-port
network [206]. The MSG can be calculated directly from the S -parameters of the device
as the magnitude ratio of the forward and reverse transmission coefficients [6, 205] as
provided in (4.2), which is equivalent to the magnitude ratio of the forward and reverse
transmission admittances of the circuit [33]. Therefore, the maximum stable gain of the
circuit from Fig. 5.2 can be calculated as the ratio of (5.4) and (5.3):

21 21 m (1 +
= = 2
MSG S Ygd gd )
+ 1
g j!r C ;
12 12 S
gs gs gd Y gd ! r C C j!C
(5.25)
which can be further simplified to

= 2 m(1 +
MSG g j!r C gd )

g 1+ !2r 2 C 2 :
! r C C j!C
gd
!C
m
1 + !2r 2 C 2
gd gd
gs gs gd gd
= gd
(5.26)
gs gs
from (5.26) for the assumed intrinsic parameter values is provided together with the
corresponding error in Fig. 5.5(a). The error introduced by the simplification performed
in (5.26) is lower than 5 % up to about 100 GHz. The sensitivity of the MSG value to
g C C r r
m , gd , gs , gd , and gs is inspected by applying (5.11) to (5.26) and provided as

1+ !2r 2 C 2
1 + !2r 2 C 2
gd gd
SgMSG @MSG
@g MSG
g = m
!C gs gs

g m
;
=1
!2r 2 C 2
(5.27)
m
m gd g 1+
!C
m
1 + !2r 2 C 2
gd gd
gd gs gs
1.0
MSG Sensitivity at 100 GHz ( -)
0 0.010
-2 0.8 0.008
0.6
Maximum Stable Gain (dB)
-4 0.006
-6 0.4 0.004
Relative Error (%)
0.002
-8 0.2 0.000
0.0
rgd
-10
-12 -0.2
-14 -0.4
MSG (rigorous) -16 -0.6
Error -18 -0.8
-20 -1.0
(a) (b)
Fig. 5.5. Analytic investigation of the MSG sensitivity of a HEMT. (a) Numerical comparison of the
rigorous (dashed) expression for the unilateral power gain from Eq. (5.25) and its simplified
version (solid) from Eq. (5.26) with the corresponding error. (b) Numerical sensitivity of the
MSG at 100 GHz to the small-signal equivalent circuit elements.
0.1
0.0
-0.1
MSG Sensitivity ( -)
-0.2
-0.3
-0.4
-0.5 Cgd
-0.6 Cgs
-0.7 rgd
-0.8 rgs
-0.9
-1.0
0 20 40 60 80 100 120 140 160 180 200
Frequency (GHz)
Fig. 5.6. Frequency dependency of the MSG sensitivity to the relevant small-signal equivalent circuit
elements.
@MSG Cgd 1
SCMSG = 2 C2 ; (5.28)
gd
@Cgd MSG 1 + ! 2 rgd gd
1
SCMSG
gs
@MSG
@C
Cgs
MSG
=
1 + !2r 2 C 2
1; (5.29)
gs gs gs
1
SrMSG @MSG
@r
rgd
MSG
=1
1+ !2r 2 2 ; (5.30)
gd Cgd
gd
gd
and
1
SrMSG
gs
@MSG
@r
rgs
MSG
=
1 + !2r 2 C 2
1; (5.31)
gs gs gs
respectively. As can be seen from (5.28)–(5.31), the MSG sensitivities to Cgd , Cgs , rgd ,
and rgs are frequency dependent. Therefore, the numerical evaluation of the sensitiv-
ity expressions from (5.28)–(5.31) for the aforementioned intrinsic parameter values is
performed at 100 GHz and is shown in Fig. 5.5(b). At 100 GHz, the most significant
contributors to the MSG value are gm and Cgd , with a medium influence coming from
Cgs and rgs . The impact of the rgd is in this case negligible as visible in the inset of
Fig. 5.5(b). The frequency dependency of the MSG sensitivity to Cgd , Cgs , rgd , and rgs is
plotted in Fig. 5.6. The sensitivities of MSG to Cgd and rgd show a very weak frequency
dependency, whereas the sensitivities to Cgs and rgs show a significant frequency reliance.
This origins in the fact that the Cgs is considerably larger than the Cgd .
5.1.2 Experimental Comparison of Two GaN HEMT Layouts

After investigating the impact of the particular intrinsic parameters of the small-signal
equivalent circuit on some basic RF figures of merit, this section will provide an exper-
imental evaluation of the influence of the gate-source and gate-drain spacing of a GaN
HEMT case on the value of its intrinsic parameters together with their bias dependency.
The used devices under test (DUTs) are two 4 45-μm GaN HEMTs with symmetri-
cal and asymmetrical spacing distances. In the symmetric layout case, the spacings are
selected as LGS = LGD = 0.7 μm, whereas the spacings for the asymmetric device are
chosen as LGS = 0.5 μm and LGD = 1.5 μm. The parameters plotted in the remainder
of this section are extracted from measurement data at 10 GHz for a drain-source bias
voltage ranging from 2.5 V to 12.5 V and a drain bias current density spanning from
100 mA/mm to 450 mA/mm.
The small-signal equivalent circuit elements from Fig. 5.2 can be related to the measured
Y -parameters after rearranging (5.2)–(5.5) and assuming the low-frequency limit [207],
where ! 2 rgd
2 C2
gd 1 and ! 2 rgs
2 C2
gs 1 hold, and given as follows [207, 208]:

gm = jY21 Y12 j 1 + !2 rgs2 Cgs2 ; (5.32)
Cgs Im(Y
1
= 11 + Y12 ); (5.33)
!
rgs Re(Y
1
= 11 + Y12 ); (5.34)
!2 Cgs2
Cgd Im(Y
1
= 12 ) ; (5.35)
!
rgd Re(Y
1
= 12 ) ; (5.36)
!2 Cgd
2
Cds =
1
!
Im(Y 22 + Y12 ); (5.37)
and
gds = Re(Y22 + Y12 ): (5.38)
Before evaluating numerically the bias-dependent performance of the equivalent circuit

elements, it has to be noted that, in an ideal case, the electrode spacings (LGS and LGD )
should not affect the intrinsic parameters of the HEMT, but rather only the respective
access resistances. However, in order to reach the upper edge of the attainable high-
frequency device performance, the gate-source and gate-drain spacings have to be scaled
in a fairly aggressive manner [197]. This can lead to an onset of the soft-breakdown
or punch-through phenomena in the charge area zones at the epitaxial interfaces of the
device [209–211], which in turn can substantially influence also the intrinsic parameters,
especially at higher drain voltage bias points.
A rigorous analysis including proper de-embedding of the measured data of the extrinsic
device, which is required for accurate determination of the contact and access resistances
with a careful comparison of the extracted values of the intrinsic equivalent circuit ele-
ments, is a rather tedious and comprehensive modeling task [108, 212–214], which goes
beyond the scope of this design-oriented thesis. As a more simple alternative, a direct
extraction of the effective (quasi-intrinsic) equivalent circuit elements is performed. The
goal of this approach is to compare the effective parameters from the equivalent cir-
cuits shown in Fig. 5.2 for two transistor layout variants. Therefore, the values of these
effective parameters incorporate to some extent also the extrinsic effects, such as the
resistances of the drain and source access regions.
450 450
650 650
600 400 600 400
600
550 350 550 350
(mS/mm)
(mS/mm)
(mA/mm)
(mA/mm)
500 600 550 500 550
300 300
450 450
500 250 250
400 400
m
m
D
D
500
g
g
200 200
I
350 450 350
450
300 400 150 300 150
350 300 350
250 250 250 400 300
100 100
2.5 5.0 7.5 10.0 12.5 2.5 5.0 7.5 10.0 12.5
VDS (V) VDS (V)
(a) (b)
Fig. 5.7. Measured bias dependence of the normalized gm for a (a) symmetric and (b) asymmetric gate-
source and gate-drain spacing variant.
Small-Signal Transconductance (gm )
The measured bias dependence of the small-signal transconductance for both spacing
variants is shown in Fig. 5.7. It can be noted that the low-voltage peak gm value is similar
in both cases and is approaching 650 mS/mm. However, it appears that the asymmetric
device shows a lower degradation of this parameter with the increasing drain-source bias
voltage than its symmetric counterpart. This could indicate that the asymmetric layout
is to some extent more robust to the short-channel effects due to its extended LGD when
compared to the symmetric HEMT.
The RF-transconductance of a HEMT can be described using the one-dimensional linear
charge control model [215] as
1
gm = " Wd Gveff
r
2 ; (5.39)
eff Ecrit LG Ceff
1+
qns
where "r is the dielectric constant, veff is the effective charge velocity, WG is the gate
width, deff is the effective gate-to-channel separation distance, Ecrit is the critical electric
field, LG is the gate length, Ceff is the effective channel capacitance, q is the elementary
charge, and ns is the sheet charge density. It can be concluded from analyzing (5.39)
that the gm is directly proportional to the charge velocity, which tends to show a satu-
rating behavior at high electric fields, in particular when approaching 200 kV/cm for GaN
HEMTs [216].
Given that the used GaN HEMT technology is a depletion mode (normally-on) type, the
applied gate-source is usually negative, e.g., about VGS = −2.5 V for achieving a drain
current bias of ID = 300 mA/mm. This results in a gate-drain voltage of about 15 V for
applying a VDS = 12.5 V. Hence, in a first-order and very simplified approximation, the
electric field for the asymmetric DUT (LGD = 1.5 μm) can be estimated to be around
100 kV/cm, whereas for the symmetric DUT case (LGD = 0.7 μm) the electric field can
be assumed to be around 215 kV/cm, which for the latter case is already beyond the
above-cited value for the onset of the charge velocity saturation [216].
450 450
700 700
650 400 650 650 400
600 550 350 600 350

(fF/mm)
(fF/mm)
(mA/mm)
(mA/mm)
550
550 300 550 600 300
500
500 250 500 250
gs
gs
450
C
C
D
D
450 200 450 500 200
I
400 150 400 150
400
450
350 350
350 100 100
2.5 5.0 7.5 10.0 12.5 2.5 5.0 7.5 10.0 12.5
VDS (V) VDS (V)
(a) (b)
Fig. 5.8. Measured bias dependence of the normalized Cgs for a (a) symmetric and (b) asymmetric gate-
In reality, the electric field distribution is not uniform as assumed above, but shows
rather a peaking behavior around gate edge region on the drain side, as can found
from device electrostatic simulations [210, 217]. Furthermore, the electric field strength
dependence shows a functional relationship to effects such as impurity level, charge
density, temperature, phonon scattering [216, 218], which are beyond the scope of this
thesis.
Small-Signal Gate-Source Capacitance (Cgs ) and Resistance (rgs )
The measured bias dependence of the normalized small-signal gate-source capacitance

for both spacing variants is provided in Fig. 5.8. As can be expected, the asymmetric
HEMT variant shows a higher value of this parameter due to a reduced gate-source
spacing distance with respect to the symmetric device. The reduction of the LGS by
about 29 % yielded an increase of the Cgs by approximately 10 %, as can be concluded
from comparing Fig. 5.8(a) with Fig. 5.8(b).
450 450
3.2 3.2
3.0 400 3.0 400
2.8 2.8 1.6
2.0 350 1.7 350
(mA/mm)
(mA/mm)
2.6 2.6
(W×mm)
(W×mm)
2.6
2.4 2.2 300 2.4 2.0 300
2.2 250 2.2 250
2.8
gs
gs
2.0 2.1 2.0

r
r
D
200 1.9 200

I
2.2
1.8 2.4 1.8
1.6 3.0 150 1.6 1.8 150
1.4 1.4 2.4
100 100
2.5 5.0 7.5 10.0 12.5 2.5 5.0 7.5 10.0 12.5
VDS (V) VDS (V)
(a) (b)
Fig. 5.9. Measured bias dependence of the normalized rgs for a (a) symmetric and (b) asymmetric gate-
On the contrary, the small-signal rgs has a lower value for the asymmetric device due
to a decreased gate-source distance. As can be noted from the comparison of the
measured bias dependence of the normalized gate-source resistance for both spacing
variants shown in Fig. 5.9, the reduction of the LGS by about 29 % resulted in a decrease
of this parameter by around 20 %.
Small-Signal Gate-Drain Capacitance (Cgd ) and Resistance (rgd )
The measured bias dependence of the normalized small-signal gate-drain feedback ca-
pacitance for both spacing variants is plotted in Fig. 5.10. As can be expected, the
symmetric HEMT variant shows a higher value of this parameter due to a reduced gate-
drain spacing distance with respect to the asymmetric device. The reduction of the LGD
by about 53 % yielded an increase of the Cgd by approximately 8 % at VDS = 12.5 V.
However, as can be concluded from comparing Fig. 5.10(a) with Fig. 5.10(b), this holds
true only for the high-VDS region, whereas for the lower drain-source bias the Cgd is similar
for both DUTs.
As for the gm case, this effect can again indicate that the asymmetric device with an
extended gate-drain spacing is to some extent more robust to short-channel effects.
An increasing drain potential leads to an increase of the surface potential at the drain
side [219]. This causes a decrease of the channel charge on the drain side, which in
turn results in a decreased Cgd value [219]. Nevertheless, in short-channel devices a
considerable drain-induced barrier lowering (DIBL) effect can appear due to a reduced
electrostatic isolation between gate and drain [197], which leads to an undesirable drain
field punch-through into the channel [211]. Due to the barrier lowering, the decrease
of the channel charge is less significant with the increasing drain potential and thus the
drop of Cgd with the increasing drain-source voltage is less pronounced [219].
The small-signal rgd has a lower value for the symmetric device due to a decreased gate-
drain distance. As can be noted from the comparison of the measured bias dependence
of the normalized gate-drain resistance for both spacing variants shown in Fig. 5.11, the
450 450
150 150
140 130
140 400 140 400
130 120 85 130 120 85 70
120 350 120 350
(fF/mm)
(fF/mm)
140
(mA/mm)
(mA/mm)
130
110 110 300 110 90 300
100 70 100 80 65
90 250 90 250
gd
gd
100 65
80 80
C
C
D
200 200
I
90 110 60
70 75 70 75
60 150 60 150
80 100
50 50
100 100
2.5 5.0 7.5 10.0 12.5 2.5 5.0 7.5 10.0 12.5
VDS (V) VDS (V)
(a) (b)
Fig. 5.10. Measured bias dependence of the normalized Cgd for a (a) symmetric and (b) asymmetric
gate-source and gate-drain spacing variant.
450 450
3.0 3.0 2.6
2.8 400 2.8 2.4
400
2.6 1.4 2.6
2.4 350 2.4 350
2.2 1.8 2.2
(mA/mm)
(mA/mm)
(W×mm)
(W×mm)
2.0 300 2.0 1.8
300
1.8 1.8 2.2
1.6 1.6
250 1.6 1.6
250
1.4 1.2 1.4
gd
rgd
1.2 0.8 1.2
r
D
200 200
1.0 1.4
I
1.0
0.8 1.0
150
0.8 2.0 150
0.6 0.6 0.6 1.2
0.4
100
0.4 100
2.5 5.0 7.5 10.0 12.5 2.5 5.0 7.5 10.0 12.5
VDS (V) VDS (V)
(a) (b)
Fig. 5.11. Measured bias dependence of the normalized rgd for a (a) symmetric and (b) asymmetric
reduction of the LGD by about 53 % resulted in a decrease of this parameter by around

25–50 %.
Besides the lower absolute value of the rgd , the symmetric HEMT shows also a stronger
reduction of this parameter with the increasing VDS than in the asymmetric layout case.
This can again indicate that the symmetric device is more prone to short-channel ef-
fects as the undesirable drain field punch-through into the channel arising due to the
DIBL effect increases the conductance of the gate-drain region at high drain voltages
[197, 211, 219, 220].
Small-Signal Drain-Source Capacitance (Cds ) and Conductance (gds )
By analyzing the measured bias dependence of the normalized Cds for both layout variants
shown in Fig. 5.12, one can note that there exists a nearly-fixed value shift of this
parameter of about 15–20 fF/mm over a broad bias range in favor of the asymmetric
450 450
210 210
200 400 200 400
200
190 350 190 180 350
Cds (fF/mm)
Cds (fF/mm)
(mA/mm)
(mA/mm)
190
180 180
160 300 300
170 180 150 170 140
250 170 250
160 160
150
D
200 200
I
150 170 150

160
140 150 140 150
130 130
100 100
2.5 5.0 7.5 10.0 12.5 2.5 5.0 7.5 10.0 12.5
VDS (V) VDS (V)
(a) (b)
Fig. 5.12. Measured bias dependence of the normalized Cds for a (a) symmetric and (b) asymmetric
450 450
65 65 55
50 20
60 400 60 400
55 55 50
50 350 50 350
(mS/mm)
(mS/mm)
55
(mA/mm)
(mA/mm)
25 45
45 300 45 30 300
40 40 25
35 30 250 250
35 45 35
35
gds
gds
30 30
D
200 200
I
25 25 40
40 150 150
20 20
15 15
100 100
2.5 5.0 7.5 10.0 12.5 2.5 5.0 7.5 10.0 12.5
VDS (V) VDS (V)
(a) (b)
Fig. 5.13. Measured bias dependence of the normalized gds for a (a) symmetric and (b) asymmetric
DUT. This suggests that the improvement of Cds in the asymmetric HEMT comes solely
from the larger drain-source spacing distance with respect to the symmetric device.
On the other hand, the asymmetric DUT shows a less pronounced decrease of gds with
the increasing VDS than the symmetric transistor. As can be seen in Fig. 5.13, the
low-voltage gds value is similar in both cases, whereas at the higher-voltage end the
asymmetric device displays a nearly-20 % improvement of this parameter with respect
to the symmetric HEMT. As already mentioned in the discussion regarding Cgd and rgd ,
this can imply that the asymmetric device is to some extent more robust to the short-
channel effects, in particular to the drain-induced barrier lowering. The DIBL effect leads
to an undesirable drain field punch-through into the channel at higher drain voltages that
increases the conductance of the gate-drain region [197, 211, 219, 220].
Small-Signal Figures of Merit: fT , fmax , and MSG at 100 GHz
Finally, the performance of the two transistor layout variants discussed in this section will
be benchmarked using the three common small-signal RF figures of merit, that is, the
fT , fmax , and the MSG value at 100 GHz. These quantities have been already discussed
in Section 5.1.1, together with their respective sensitivity to the small-signal equivalent
circuit elements of a HEMT model. Here, the bias dependency of these figures of merit
are presented for both layout variants. The values of fT , fmax , and the MSG at 100 GHz
are directly extracted from the measured h21 , unilateral power gain, and MSG curves,
respectively.
The measured bias dependence of fT for both transistor layouts is provided in Fig. 5.14.
The maximum value of fT for the symmetric device case is significantly greater than in the
asymmetric case. This can be attributed to the lower Cgs value of the symmetric HEMT
(see Fig. 5.8), which was previously identified as the most deteriorating contributor to
the fT value, as show in Fig. 5.3(b).
However, as the drain voltage bias increases, the fT advantage of the symmetric DUT
starts to diminish. This effect can be related to above-discussed more sustainable gm
value of the asymmetric device over the drain-source voltage bias variation, as already
450 450
180 180
170 400 170 400
160 160
150 350 150 150
350
(mA/mm)
(mA/mm)
(GHz)
(GHz)
140 170 160 300 140 300
130 130 130
120 250 120 140 250
fT
fT
110 150 110
D
200 200
I
140
100 100 130 120
120 110
90 150 90 150
100 90 110
80 80 100
100 100
2.5 5.0 7.5 10.0 12.5 2.5 5.0 7.5 10.0 12.5
VDS (V) VDS (V)
(a) (b)
Fig. 5.14. Measured bias dependence of fT for a (a) symmetric and (b) asymmetric gate-source and
gate-drain spacing variant.
presented in Fig. 5.7. Within the low-ID -and-high-VDS region, the fT value of the asym-
metric HEMT is becoming already higher than in the symmetric layout case. This bias
region can be considered as the so-called deep class-AB bias [84] for this technology
variant, which is a desired trade-off operation bias for high-efficiency mm-wave power
amplifiers [6, 84].
Figure 5.15 displays the measured fmax performance of both DUTs over the considered
bias range. One can see that not only is the absolute value of fmax higher for the
asymmetric case, but also a more favorable bias distribution of this quantity is noted for
this layout variant.
On the one hand, similarly as in the fT case, the Cgs was found to have the highest
negative impact on the fmax value, as presented in Fig. 5.4(b). As already mentioned,
Fig. 5.8 showed that the gate-source capacitance is noticeably larger for the asymmetric
layout case. On the other hand, the discussed combined improved performance of the
gm , rgs , Cgd , and gds seen in Figs. 5.7, 5.9, 5.10, and 5.13, respectively, overcomes the
negative consequences arising from the higher Cgs .
450 450
360 360 200
340 400 340 280
400
320 240 320 240 300
350 350
(mA/mm)
(mA/mm)
300 300 220

(GHz)
(GHz)
280 300 310 300 280 340 300

260
260 260 250 260 320 250
fmax
fmax
240 240
D
200 200
I
220 280 220

200 150 200 150
220
180 200 100 180
100
2.5 5.0 7.5 10.0 12.5 2.5 5.0 7.5 10.0 12.5
VDS (V) VDS (V)
(a) (b)
Fig. 5.15. Measured bias dependence of fmax for a (a) symmetric and (b) asymmetric gate-source and
gate-drain spacing variant.
450 450
12.5 12.5
12.0 400 12.0 12.0 400
MSG at 100 GHz (dB)
MSG at 100 GHz (dB)

11.5 11.0 11.5
11.0 350 11.0 350
(mA/mm)
(mA/mm)
10.5 11.5 300 10.5 300
10.0 10.5 10.0
9.5 250 9.5 11.0 250
9.0 9.0 11.5
ID
ID
200 200
8.5 9.5 8.5 9.0 10.5
10.0
8.0 150 8.0 150
8.5 9.0 8.5 9.5 10.0
7.5 8.0 7.5
100 100
2.5 5.0 7.5 10.0 12.5 2.5 5.0 7.5 10.0 12.5
VDS (V) VDS (V)
(a) (b)
Fig. 5.16. Measured bias dependence of MSG at 100 GHz for a (a) symmetric and (b) asymmetric gate-
Since the fmax value is directly related to the (unilateral) power gain, an alternative
perspective can be considered as well. The power gain is the combination of the current
and voltage gains. The overall current gain, which can be directly related to the fT value,
is generally higher for the symmetric DUT variant.
However, the voltage gain, which
can be approximated in the first order by the gm gds ratio [161], is high enough for the
asymmetric HEMT layout case in order to prevail over the current gain shortcomings,
and thus results in a better overall power gain.
The bias-dependent maximum stable gain value measured at 100 GHz for both spacing
variants is plotted in 5.16. The MSG value of the asymmetric DUT is about 0.5 dB
higher than for the symmetric layout case over the complete bias range, with an even
bigger advantage in the low bias current regime (up to 1 dB). This effect origins in the
improved gm (see Fig. 5.7) and Cgd (see Fig. 5.10) performance, which were recognized
in Fig. 5.5(b) as the critical contributors to the MSG performance. This noticeably
higher gain achievable from a single asymmetric HEMT compounds to a significantly
higher gain of the amplifier circuits operating beyond 100 GHz, which usually comprise
multiple cascaded transistor stages.
In summary, it can be concluded that the asymmetric spacing variant is more advan-
tageous for being applied in high-frequency GaN MMICs. With the current status of
the GaN HEMT technology, the transistor’s high-frequency gain is the most precious
resource of the designer’s performance budget for amplifiers operating beyond 100 GHz.
Therefore, the focus of this chapter prioritizes the small-signal performance of GaN cir-
cuits. However, besides the small-signal performance discussed in this section, also some
large-signal consequences are briefly discussed below.
On the one hand, selecting the asymmetric layout with an extended gate-drain spacing
should result in a better breakdown voltage [197], which allows for a higher output voltage
swing, and in turn effects in a higher output power. Alternatively, the extended gate-drain
ledge should reduce the electric field peaking on the drain side for given drain voltage,
which ought to result in better device reliability [71]. Finally, achieving a better gain
performance at lower bias currents allows for choosing more efficient operating biases
in order to improve the power-added efficiency and relax the junction temperature for a
given output power, which will as well improve the lifetime of the device.
1.6
1.5
1.4
Ron (W mm)
1.3
×
1.2
1.1
1.0 LGS = 0.5 µm
0.9 LG = 0.1 µm
0.8
0.5 1.0 1.5 2.0 2.5 3.0
LGD (µm)
Fig. 5.17. Calculated dependency of the normalized on-state resistance of a 100-nm GaN HEMT on its
gate-drain spacing for a fixed gate-source distance.
On the other hand, extending the gate-drain spacing too much will negatively affect
the on-state resistance (Ron ) of the transistor and introduce undesirable losses, which
could at some point overcome the aforementioned advantages of the asymmetric layout
variant. The Ron is composed of the Rsh of the 2DEG and the contact resistances (Rcont )
of the source and drain terminals. In the first-order approximation, the resulting on-state
resistance of a HEMT normalized to its total gate width can be expressed as
Ron 1
= T GW Rcont,S + Rsh (LGS + LG + LGD) + Rcont,D : (5.40)
The typical Rsh and Rc values of the used mm-wave 100-nm GaN HEMT process are
approximately 300 Ω/sq and 0.25 Ω mm, respectively [13, 14]. Therefore, the approx-
imate theoretical Ron values for the symmetric and asymmetric device cases discussed
in this section are 0.95 Ω mm and 1.13 Ω mm, respectively. A calculated simplified
dependency of the Ron of a GaN HEMT on its gate-drain spacing for a fixed LGS value
is provided in Fig. 5.17. In reality, the sheet and contact resistances (and thus the
Ron) are non-linear and further depended on the operating bias and temperature of the
HEMT [221].
5.1.3 Dimensioning GaN HEMTs for High-Frequency Applications

The basic degree of freedom to modify the transistor’s geometry available to the circuit
designer from any FET-based semiconductor foundry, is the option to select the unit
gate width (UGW) and the number of gate fingers. The product of the two accounts
for the total gate width (TGW) of a transistor.
In the low-voltage, high-speed semiconductor technologies, such as InGaAs mHEMT [15],
InP HEMT [16], InP HBT [17], SiGe HBT [18], or Si CMOS [20], the TGW of the used
devices (or the emitter area for the HBT devices, respectively) usually scales down to-
gether with the increasing frequency of operation [6, 115], resulting often in UGW values
below 10 μm [222–224]. On the one hand, increasing the unit gate width introduces a no-
table attenuation due to the finite gate resistance [6], which reduces the high-frequency
gain. When the UGW becomes a significant fraction of the operating wavelength also
a substantial gate delay arises from the finite resistance and inductance of the gate fin-
ger [108], so that the distributed effects can deteriorate the performance [115]. On
the other hand, expanding the number of gate fingers effects in wider gate and drain
feeders (bus bars), which can lead to an out-of-phase power combing already on the
device level between the inner and outermost fingers and, in turn, to a decrease of the
high-frequency gain [6, 115]. Moreover, the inner gate fingers of a multi-finger HEMT
suffer from a larger source inductance than the outermost fingers due the airbridge con-
nections, which has also a negative effect on the high-frequency gain and can further
add electrical asymmetries on the device level [6].
However, gallium nitride is a high-voltage technology, where the drain-source oper-
ating bias voltages of the GaN HEMTs are usually higher than 10 V, also in the
technology variants targeting operation at the W-band (75–110 GHz) and beyond
[21, 22, 24, 26, 112, 134, 139]. Hence, one can expect that for GaN HEMTs with a small
periphery show relatively high values of the real part of the desired output impedance.
As has been discussed in Section 3.1.1 and shown in Fig. 3.1, the output port impedance
of a HEMT device can be represented as a parallel RC connection [6, 115]. The real
part of this impedance, or Rout , is in the first-order low-frequency approximation di-
rectly proportional
to the ratio of the drain-source voltage bias to the drain current
bias, that is, VDS ID [6, 84]. For a given class of amplifier operation bias, the VDS is
independent of the HEMT’s TGW, but the drain current scales together with the gate
periphery. Therefore, for a typical bias condition for the used mm-wave GaN HEMT
technology of VDS = 10 V and ID = 300 mA/mm, the normalized low-frequency Rout is
expected to be on the level of about 30 Ω mm. At the W-band frequencies, the optimum
power-match Rout of the used technology was verified to be 8.14 Ω mm, as discussed
in Sections 2.5 and 3.1.1, which is a notably higher value than in other high-speed semi-
conductor processes. For instance, the optimum Rout of an InGaAs mHEMT is about
1.25 Ω mm at the W-band [225]. Thus, the Rout of small GaN HEMTs tailored for
high-frequency operation can considerably exceed the system impedance (usually 50 Ω),
which makes the matching network (MN) design challenging.
In order to illustrate the GaN-specific output impedance aspects discussed above, the
G-band performance of the used small-signal GaN HEMT model is evaluated at a fre-
quency of 180 GHz, which is the approximate mid-frequency of the G-band. In addition,
it lies also very close to the water absorption line at 183 GHz, which provides numerous
scientific instrumentation applications [67].
The dependency of the unit gate width on the simulated output resistance and capac-
itance values provided by the HEMT model is shown in Fig. 5.18 for three variants of
the number of gate fingers. The Rout and Cout values are calculated from the following
relation [5]:
YL = 1 = 1 + j!Cout;
ZL Rout (5.41)
where ZL is the desired load impedance resulting from a simulated conjugate-complex

or power matching scenario. Assuming that a single transistor is intended to be in-
cluded in the output stage of an amplifier (i.e., no on-chip power combining), the
Rout can be matched to the system impedance (50 Ω) using, for instance, a quarter-
wavelength (=4) transmission line, which is a convenient and practical way of imple-
200 90
Gate fingers
Gate fingers 80
175 2
2 70
Cout at 180 GHz (fF)

Rout at 180 GHz ( W)
150 4
4
60 6
125 6
50
100
40
75 30
50 20
25 10
0 0
10 15 20 25 30 35 40 45 50 10 15 20 25 30 35 40 45 50
Unit Gate Width (µm) Unit Gate Width (µm)
(a) (b)
Fig. 5.18. Simulated dependency of the output (a) resistance and (b) capacitance of a GaN HEMT for a
conjugate-complex matching scenario at 180 GHz on the unit gate width and number of gate
fingers.
menting the transformation of the real part of an impedance [33], as discussed in Sec-
tion 3.1.2. The characteristic impedance (Z0 ) of such a =4 line should be selected
p
as Z0;=4 = Rout 50 Ω [33]. However, the range of the realizable line impedances is
limited by the design rules of the used process. In case of the employed passive grounded
CPW environment with a ground–ground spacing of 50 μm, the minimum and maxi-
mum design-rule-compliant line impedances are about 30 Ω and 85 Ω, respectively. This
confines the desirable values of Rout to [33]
2
Z0, min ; Z02, max
Rout,min ; Rout,max = : (5.42)
50 Ω
Therefore, for the used 50-μm CPW passive technology, the desirable value of Rout
ranges from approximately 18 Ω to 145 Ω. One can see from Fig. 5.18(a) that the Rout
decreases with the increasing TGW. Considering the above-listed desirable Rout span,

the most favorable unit gate widths are 30 μm for a two-finger device, 16–50 μm for

a four-finger device, and 35 μm for a six-finger device.
The simulated Cout shows in general an opposite relationship, that is, it increases together
with the increasing TGW, as shown in Fig. 5.18(b). As discussed in Section 3.1.1, an
increased Cout can be a bandwidth-limiting factor for the output matching due to the
Bode-Fano limit [113, 114]. It can be noticed in Fig. 5.18(b) that the simulated Cout
starts to decrease beyond the an UGW value of around 40 μm for the six-finger transistor
case. This can indicate that the parasitic output inductance associated with this device
geometry is approaching values significant enough to partially resonate out the Cout at
180 GHz.
In Fig. 5.19(a), the simulated dependency of the maximum available gain (MAG) at
180 GHz on the UGW and number of fingers is depicted. The MAG shows a maximum
for UGW value range from 20 μm to 25 μm for all numbers of gate fingers. The decline of
the MAG value for unit gate widths below 20 μm can be correlated to significant parasitic
end-effects of the HEMT layout, such as the increased gate-drain capacitance arising
3.7 15
3.6 Gate fingers
10
2
MAG at 180 GHz (dB)
3.5 5
)
4
W
3.4 0
at 180 GHz (
6
3.3 -5
3.2 -10
3.1 -15 Gate fingers
2
in
3.0 -20
X
4
2.9 -25
6
2.8 -30
10 15 20 25 30 35 40 45 50 10 15 20 25 30 35 40 45 50
Unit Gate Width (µm) Unit Gate Width (µm)
(a) (b)
Fig. 5.19. Simulated dependency of the (a) MAG and (b) input reactance for a conjugate-complex match-
ing scenario of a GaN HEMT at 180 GHz on the unit gate width and number of gate fingers.
from the signal cross-talk between the gate and drain feeders [31]. Since the MAG is
closely related with the fmax value [6, 200], one can note from Fig. 5.4(b) in Section 5.1.1
that the Cgd has a relatively strong negative influence on this figure of merit. The reduced
value of the MAG for unit gate widths above 25 μm can be associated to the increased
loss that origins from the finite gate finger resistance and inductance, which scale up
together with the increasing UGW [108]. In addition, it can be noticed that the MAG
value at 180 GHz is, according to the small-signal HEMT model, nearly identical for two-
finger and four-finger devices for a given UGW. Therefore, the model does not predict
any significant negative impact from the more distributed gate and drain feeders of the
four-finger device as well as from an increased source inductance of the inner finger on
the MAG performance, even at such high frequency of operation. This effect is beneficial
for high-frequency power amplifier design, since the four-finger device is able to produce
twice the output power of a two-finger transistor for a given unit gate width. However,
the negative effects of a wider layout of a six-finger device and the increased source
inductance of the airbridge connections are starting to become visible in Fig. 5.19(a).
The simulated input reactance (Xin ) at 180 GHz scaling with the UGW and number of
fingers is plotted in Fig. 5.19(b). The input reactance is calculated as Xin = Im(ZS ),
where ZS is the desired source impedance resulting from a simultaneous conjugate-
complex matching scenario. The simulated Xin shows a zero-crossing at 180 GHz for
different transistor geometries, that is, for about UGW = 41 μm for a two-finger device,
UGW = 23 μm for a four-finger device, and UGW = 12 μm for a six-finger device. Select-
ing a HEMT geometry with a zero or small value of the input reactance can significantly
ease the broadband input matching as discussed in Section 3.1.1.
Considering the GaN-specific transistor-dimensioning aspects discussed above and shown
in Figs. 5.18 and 5.19, one can conclude that, according to the used small-signal model,
the optimal device size for operation at around 180 GHz is a four-finger HEMT with a
unit gate width of 23 μm. This 4 23-μm GaN HEMT shows an optimum simulated
trade-off between the high-frequency gain and the input and output impedance levels at
1.0j
0.5j 2.0j
3.4 dB
2.8 dB
GA
0.2j 5.0j
3.4 dB
GP
2.8 dB 180 GHz
0.2 0.5 1.0 2.0 5.0
Fig. 5.20. Simulated available gain (GA , blue) and power gain (GP , red) circles of a 4 23-μm HEMT at
180 GHz on a 50-Ω Smith chart.
180 GHz. Moreover, the impedance levels presented by the HEMT’s input and output
ports for this transistor size show a favorable relationship for the resulting complexity of
the interstage matching network (ISMN) required to achieve a broadband and low-loss
matching. In order to illustrate this relationship, the available gain (GA ) and power gain
(GP ) circles [226] at 180 GHz for this HEMT are depicted in Fig. 5.20. The source
and load impedances required for a conjugate-complex matching are 7:5 j 0:4 Ω and
9:4 + j 24:6 Ω, respectively, which results in a gain per stage of nearly 3.5 dB (excluding
network losses and assuming a nearly-perfect narrowband match). As can be noticed, the
real parts of these impedances are relatively similar. This eases the design of a low-loss
ISMN, which can be implemented with a single series transmission line. When choosing
a smaller device (e.g., a two-finger HEMT), the GP -targets would be less favorable due
to an increased real part of the output impedance.
Since GaN-based amplifier MMICs operating beyond 100 GHz incorporate usually a high
number of stages ( 4) in order to provide sufficient gain. The performance of the ISMN
is usually the passive network that defines the overall bandwidth, gain, and consumed
chip area of the amplifier. Therefore, when selecting a HEMT geometry, its impact on
the resulting ISMN complexity has to be carefully considered, as it can consume the
potential gain increase on the transistor level.
5.1.4 Application of the Transistor Layout Concepts in Broadband

G-Band GaN Amplifiers
In order to demonstrate the concepts regarding the transistor geometry discussed in this
section on high-frequency circuit level, two broadband GaN power amplifiers with the
aim to operate at the G-band (140–220 GHz) frequencies were designed.
The micrographs of the four-stage and five-stage amplifier MMICs are shown in
Fig. 5.21(a) and Fig. 5.21(b), respectively. The amplifiers consist of reactively matched
common-source gain stages, where the matching networks are implemented using
grounded CPW technology with a ground–ground spacing of 50 μm. The CPW envi-
ronment is selected due its high-frequency advantages mentioned in Section 4.1.3, such
(a) (b)
Fig. 5.21. Micrographs of the fabricated G-band GaN power amplifier circuits.
(a) Four-stage MMIC (2:25 0.95 mm2 ). (b) Five-stage MMIC (2:6 0.95 mm2 ).
as low-inductive ground connection, relaxed substrate thickness requirements, and lower

dispersion than in microstrip technology [117].
All of the employed common-source HEMTs incorporate an asymmetric gate-source and
gate-drain spacing layout approach, which experimental evaluation was performed in
Section 5.1.2 shows a high-frequency performance advantage over the symmetric layout
case. Furthermore, the transistors are dimensioned as four-finger devices with a unit gate
width of 23 μm in all cases. The circuit-level benefits of using 4 23-μm GaN HEMTs
for G-band applications has been discussed in the previous Section 5.1.3. Finally, the
stability of both circuits was simulated using the 4-Gamma method [131].
Measured Small-Signal Performance
The S -parameter measurements were performed from 130 GHz to 225 GHz with an
Agilent N5254A PNA-X network analyzer and VDI WR5.1-VNAX frequency extenders.
The S -parameter wafer mapping of the four-stage MMIC is presented in Fig. 5.22(a),
where 12 cells are considered. This amplifier can provide up to 10.5 dB of small-signal
Meas. 15 Meas.
15
Sim. Sim.
10 10 S11
S11
S-parameters (dB)
S21
S-parameters (dB)
5 S21 5
S22 S22
0 0
-5 -5
-10 -10
-15 -15
-20 -20
140 150 160 170 180 190 200 210 220 140 150 160 170 180 190 200 210 220
(a) (b)
Fig. 5.22. Measured (solid) and simulated (dashed) small-signal responses of the G-band GaN amplifiers.
(a) Four-stage amplifier with 12 cells processed on the wafer shown. (a) Five-stage amplifier
with 9 cells processed on the wafer shown. VDS = 12 V and ID = 300 mA/mm in both cases.
gain at 185 GHz with a 3-dB bandwidth of 40 GHz (152–192 GHz). The homogeneity
of the small-signal response over the wafer is considered as excellent for such a high-
frequency design.
A similar wafer mapping of the five-stage amplifier is shown in Fig. 5.22(b). In this
case, the performance of 9 cells is displayed. This power amplifier shows a small-signal
gain of 13 dB at 183 GHz. The 3-dB bandwidth is in this case 39 GHz (150–189 GHz).
The homogeneity over the wafer is also considered as very encouraging, given the high
frequency of operation.
It can be seen from Figs. 5.22(a) and 5.22(b) that there are some discrepancies between
the measured (solid lines) and simulated (dashed lines) results. These are due to the fact
that the small-signal HEMT model was extracted from a wafer using a different epitaxial
stack compared with the wafer on which the presented circuits were processed. For the
wafer used for transistor modeling, a slightly more aggressive approach to vertical scaling
of the epitaxial structure was followed, which has an significant effect on the transistor’s
intrinsic parameters.
Measured Large-Signal Performance
The on-wafer scalar continuous wave (CW) power measurements within the
181–190-GHz band were conducted with an Agilent E8247C synthesizer cascaded with
an HP 83558A mm-wave source module, followed by a custom W-band power amplifier
module and a G-band VDI x2 multiplier connected on the input side. The output power
was measured using an ELVA G-band power sensor. Losses in the waveguides and probe
tips were removed in a calibration process in a similar manner as for the D-band large-
signal characterization case described in Section 4.1.4. This setup is able to provide
between 2 and 5 dBm of input power over 181–190 GHz.
Due to the limited available input power, only the five-stage MMIC was characterized in
large-signal as it is the only circuit that shows enough gain to be driven into any gain
16 3.2 16 Pout 3.2

10 V 12.5 V 15 V
14 2.8 14 2.8
Pout (dBm), Gain (dB)
PAE
12 2.4 12 2.4
Pout (dBm)
PAE (%)
PAE (%)
10 2.0 10 2.0
8 1.6 8 1.6
181 GHz
6 1.2 6 1.2
P out
4 0.8 4 0.8
Gain
2 0.4 2 0.4
PAE
0 0.0 0 0.0
-10 -8 -6 -4 -2 0 2 4 180 182 184 186 188 190
P in
(dBm) Frequency (GHz)
(a) (b)
Fig. 5.23. Measured large-signal CW response of the five-stage G-band amplifier. (a) Large-signal re-
sponse to an input power sweep at 181 GHz (VDS = 10 V, ID = 350 mA/mm). (b) Large-signal
response to a frequency sweep with a constant input power of 2 dBm for different VDS : 10 V
(empty symbols), 12.5 V (half-full), and 15 V (full). ID = 250 mA/mm in all cases.
compression. As shown in Fig. 5.23(a), the five-stage amplifier can deliver 15.8 dBm
(38 mW) of output power at 181 GHz with a PAE value of 2.4 %. The corresponding
output power density at this frequency is 413 mW/mm. However, the measurement setup
allowed for driving this amplifier only into 0.6 dB of gain compression, which indicates
that the presented results are still relatively far from the limits of this power amplifier.
Figure 5.23(b) illustrates the VDS -dependency of the large-signal response over the
181–190-GHz band for a constant Pin = 2 dBm and ID = 250 mA/mm. For VDS = 10 V,
the output power is higher at the lower-end of the measured band, whereas for VDS = 15 V
it is better for the higher frequencies. The best Pout -flatness is achieved for a trade-off
drain bias of 12.5 V.
5.2 Advancing GaN Amplifiers Beyond 200 GHz

After presenting geometry-based approaches to enhance the high-frequency gain of GaN
HEMTs, this section will switch the focus on developing passive networks that can sup-
port compact multi-stage amplifiers operating beyond the 200-GHz mark. In particu-
lar, scaling of coplanar waveguide (CPW) technology is discussed. Compact matching
networks are one of the key enablers of multi-stage amplifiers operating at very high
frequencies, which allow advancing the performance of GaN-based circuits towards the
sub-millimeter-wave frontier.
5.2.1 Scaling the Coplanar Waveguide Passive Networks
As already mentioned in Section 4.1.3, grounded CPW technology is a suitable choice for
implementing matching networks in MMICs operating at higher mm-wave bands. CPW
provides a low-inductive ground connection for the circuit elements, which is especially
important when targeting higher frequencies. As a result, this relaxes the substrate
thickness requirements, which eases the handling of the processed wafers. Additionally,
CPW shows lower dispersion than microstrip technology [117], which is beneficial for
broadband circuit design. In order to take full advantage of the continuous improvement
of GaN HEMT technology on circuit level and to support applications beyond 200 GHz,
also the passive network environment has to scale accordingly with the geometry of the
active devices.
On the one hand, the scaling of the CPW networks is driven by the need of increasing
the compactness of the resulting circuits. Practical GaN amplifiers operating beyond
W-band require a high number of transistor stages in order to provide sufficient circuit
gain. Therefore, dense MMIC layouts are required for applications that put a limit on the
chip size, such as phased arrays, where the spacing between the array elements should
be constrained to one-half of the operating wavelength [227]. Moreover, a compact chip
size helps to suppress unwanted cavity resonances when packaging into waveguide-based
modules is desired [224, 228].
On the other hand, the dimension of the CPW environment need to be scaled down
together with the increasing frequency in order to circumvent various parasitic effects
5.2 Advancing GaN Amplifiers Beyond 200 GHz 121
E-Field
H-Field
GG
G S G G S G
wg g s g wg
Via Via h Via Via
VV

(a) (b)
Fig. 5.24. Cross-sectional view of the grounded coplanar waveguide transmission line with (a) indication
of its crucial dimension parameters and (b) an illustrative distribution of the electromagnetic
field of the even propagation mode [118].
associated with this type of network, which can significantly hamper the overall circuit
performance.
High-Frequency Parasitic Effects in Coplanar Waveguide Networks
The cross-sectional view of the grounded CPW transmission line together with its critical
physical dimensions is shown in Fig. 5.24(a). The characteristic impedance of the CPW
lines is set by selecting a proper ratio of the width of the center signal strip s to the
spacing between the the both topside ground planes GG [229–231]. An illustrative
distribution of the electromagnetic field of the even propagation mode of the grounded
CPW is sketched in Fig. 5.24(b) [118]. As can be noted, the even propagation mode
can be viewed as a combination of a pure coplanar mode (E-field lines propagating from
the signal trace to the both topside ground planes) and a microstrip mode (E-field lines
propagating from the signal trace to the bottom ground plane) [230, 231]. By selecting
the GG spacing to be lower than the substrate thickness h, the coplanar mode becomes
the dominant of the two [231].
The field distribution of the fundamental propagation mode of the CPW shown in
Fig. 5.24(b) assumes an ideal situation, where all the ground planes (i.e., both topside
planes and the backside plane) can be considered as equipotential [230, 231]. However,
due to the distributed nature of transmission lines, this may not be always the case,
especially at mm-wave frequencies, where higher-order propagation modes can emerge.
The two basic higher-order parasitic propagation modes are the slotline mode and the
parallel-plate modes [230–232].
The slotline mode is illustrated in Fig. 5.25(a) and arises due to a potential difference
between the two topside ground planes [231, 232]. It can be significantly suppressed by
applying airbridges along the line and in the vicinity of any discontinuities, which provide a
local equalization of the potentials between both topside ground planes [117, 230–232].
The parallel-plate mode is illustrated in Fig. 5.25(b) and arises due to a potential dif-
ference between the topside and backside ground planes [232]. This mode cannot be
suppressed by using airbridges since it has the same symmetry as the fundamental CPW
mode shown in Fig. 5.24(b) [232]. In this case, through-substrate vias are necessary
E-Field
G S G G S G

(a) (b)
Fig. 5.25. Cross-sectional view of the grounded coplanar waveguide transmission line with an illustrative
distribution of the electric field of the parasitic (a) slotline and (b) parallel-plate propagation
modes.
to locally equalize the potentials between the ground planes on both sides of the sub-
strate [233].
However, including through-substrate vias in a grounded CPW structure generates fur-
ther risks of higher-order mode propagation. In the case that the via–via spacing, indi-
cated by V V in Fig. 5.24(a), approaches one-half of the operating guided wavelength
(/2), rectangular waveguide propagation modes are supported [233, 234], in particular
a TE10 -like mode [33]. Similarly, rectangular waveguide-like modes can be also supported
when the substrate thickness h approaches this critical dimension (/2) in a grounded
CPW environment [33].
An onset of higher-order propagation modes can lead to an significant power leakage from
the fundamental CPW mode [233] and unwanted resonances within the band of interest
or unexpected strong interactions between neighboring discontinuities (e.g., T-junctions),
which can effectively prevent the circuit from any useful operation.
Coplanar Waveguide Design Considerations for Applications Beyond 200 GHz
When developing a CPW passive network library, the circuit designer has to operate
within certain constrains of the used MMIC process, which are usually collected as design
rules. From the passive network design perspective, the most relevant process features
are the substrate thickness, the electrical properties of the substrate, availability of the
metalization layers and the properties of the corresponding separating dielectric layers,
the minimum width and spacing of the metal strips, and the minimum spacing between
through-substrate vias.
Since the above-listed features are usually fixed for a given process node, the main
CPW-design decision is related to selecting the proper ground–ground spacing between
the topside ground planes, which is indicated by GG in Fig. 5.24(a). On the one hand,
selecting a small GG value allows for an easier suppression of the aforesaid high-frequency
parasitic effects and more compact MMIC layouts, which are required at high frequencies
as already discussed above. On the other hand, scaling down the GG dimension increases
the conduction loss of a CPW transmission line of a given characteristic impedance due
to a decreasing width of the signal metal strip in a similar fashion as for the microstrip
line case, discussed in Section 3.1.4. Moreover, a small GG limits the range of realizable
line impedances due to the process design rules. The upper Z0 limit is fixed by the
minimum allowed metal width [see feature s in Fig. 5.24(a)], whereas the lowest realizable
impedance is limited by the minimum spacing between two metal strips allowed by the
process, indicated by feature g in Fig. 5.24(a).
Therefore, the GG spacing has to be selected carefully to provide an optimum circuit-
level performance within the frequency range of interest. This can be accomplished by
choosing the largest feasible GG spacing (for a reduced conduction loss) that allows for
a sufficient layout density and suppression of higher-order parasitic effects.
One aspect that constrains the maximum GG spacing is the via–via spacing, V V . As
already mentioned, the absolute maximum distance between the vias should be kept
below /2 at the highest operating frequency [233]. However, a significant perfor-
mance degradation and onset of resonances are observed already for lower V V spacing
distances [233, 235, 236]. Therefore, mm-wave circuit designers tend to set the V V
spacing below /4 at the highest operating frequency [117, 235].
The lowest V V spacing can be achieved by locating the via directly at the edge of the
topside ground plane edge, leading to V V = GG . However, a via placed near the edge of
the side ground plane can considerably disturb the electromagnetic field distribution of
the fundamental CPW mode seen in Fig. 5.24(b) [231, 233]. This effect is likely to be not
captured by the grounded CPW models available in CAD software packages and by the
closed-form design equations available in the literature [230, 231]. As a result, more EM-
simulation iterations are required from the designer in order to obtain a good prediction
of the performance, which increases the circuit design cycle time. Nevertheless, shifting
the vias away from the ground plane edge [see wg in Fig. 5.24(a)] by a distance of
wg = GG=2 should already reduce the effect of the vias on the characteristic impedance
of the CPW line below 1 % [231]. Therefore, a relation of V V = 2GG is considered
when selecting the ground–ground spacing. Since the guided wavelength at 300 GHz,
which is the upper edge of the mm-wave band, is about 320 μm in silicon carbide (SiC),
the GG should not exceed 40 μm in order to assure that V V < =4 holds within the
complete mm-wave range.
A further advantage of scaling down the GG spacing is limiting the portion of power
transferred from the fundamental CPW propagation into the parasitic higher-order
modes (mainly the slotline mode) that happens at the network discontinuities, such
as bends or T-junctions. In [231], it was shown that a five-fold downscaling of a 50-Ω
T-junction (with airbridges present) resulted in a nearly five-fold decrease of the magni-
tude of the power of the incident CPW mode converted into the parasitic slotline mode
(S21,CPW!slotline ) at 40 GHz. The reduction of the mode conversion due to GG -scaling is
expected to be even more pronounced with increasing the frequency of operation [231].
Moreover, a low value of the GG compared to the substrate thickness h results in an
improved dispersion properties of CPW networks [231, 237]. Keeping the GG smaller
than h reduces the field overlap between the fundamental CPW propagation mode and
the first two TE and TM surface modes, which minimizes the dispersion effect [237]. A
reduced dispersion is beneficial for broadband circuit design [117].
As has been already mentioned above, decreasing the GG distance leads to increased
conduction losses of a CPW line for a given characteristic impedance. On the other hand,
the substrate radiation losses can be significantly reduced due to GG -downscaling, since
1.2 1.2
Conduction Conduction
1.0 200 GHz 1.0 300 GHz
Radiation Radiation
Loss (dB/mm)
Loss (dB/mm)
0.8 Total 0.8 Total
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100
GG Spacing (µm) GG Spacing (µm)
(a) (b)
Fig. 5.26. Calculated conduction, radiation, and total loss per unit length of a 50-Ω grounded CPW
transmission line for different values of the GG spacing at (a) 200 GHz and (b) 300 GHz in the
used GaN-on-SiC MMIC technology.
these losses are proportional to / (GG=)2 [237]. The evaluation of the conduction
and radiation loss per unit length at 200 GHz and 300 GHz is shown in Fig. 5.26. The
conduction loss per unit length of a grounded CPW 50-Ω line in the used GaN-on-SiC
MMIC technology is calculated using closed-form equations provided in [230], whereas
the substrate radiation loss is calculated using the formulae from [237]. As can be noted,
the radiation loss value is starting to dominate the conduction loss value when the GG is
approaching /8, that is, around 67 μm and 55 μm at 200 GHz and 300 GHz, respectively.
The optimum calculated total loss (sum of the conduction and radiation loss) is located
for GG 50 μm at 200 GHz and for GG 40 μm at 300 GHz.
Based on the above-discussed design consideration regarding the GG spacing, the value of
this parameter for CPW-based circuits targeting operation at the higher end of the mm-
wave spectrum is selected to be 25 μm. This spacing value should provide an adequate
compromise between the networks’ conduction losses, suppression of the higher-order
parasitic effects, and the attainable layout density for applications up to at least 300 GHz.
Nonetheless, the advantages of compacter multi-stage layouts and better suppression of
parasitic effects have been prioritized over the increased conduction loss throughout the
decision process. Furthermore, this GG -spacing value provides also some margin for the
future improvement of the GaN HEMT technology, which could potentially allow for
operation also beyond the mm-wave spectrum.
Finally, the CPW networks are implemented using only the first metal layer (MET1)
for the signal traces and topside ground planes. The galvanic metal layer (METG) is
used only for the airbridges and for the top plates of MIM capacitors. Alternatively, the
full metal stack could be used (i.e., MET1+METG). However, this approach has the
disadvantage of creating in-line discontinuities (under- or over-passes) in the vicinity of
the airbridges, which encumbers accurate modeling of the networks and increases the
MMIC layout complexity. Moreover, the design rules corresponding to the full metal
stack are more restrictive in terms of the minimum width and spacing of the metal
structures (4 μm in both cases) than for MET1, which limits the realizable scope of the
Au Au Au Au Air Au Au
SiN
AlGaN/GaN layers
SiC Effective material
Au Au
(a) (b)
Fig. 5.27. Cross-sectional view of the material stack of the grounded coplanar waveguide transmission
line in the used GaN-on-SiC MMIC technology. (a) Actual full material stack (not to scale).
(b) Simplified effective material stack used for modeling purposes.
CPW line impedances. In case of using only the MET1 layer, the respective minimum
spacing and width are 2 μm, which allows for implementing CPW transmission lines with
a characteristic impedance ranging from around 28 Ω to 85 Ω.
Using a thinner metal layer for signal traces creates a risk of a substantial increase of
the RF loss. However, at the targeted frequencies of operation (beyond D-band or
above 170 GHz), the MET1 thickness is at least 3 times the skin depth [121, 122]
(see Equation (3.20) from Section 3.1.4). Therefore, the metal thickness should not
affect the overall loss by more than 5 % within the frequencies of interest [121, 122].
Nevertheless, one has to still mind the current carrying capability of thin conductor lines
when these are used for drain biasing networks. Operating the metal lines at high current
densities can lead to an electromigration effect [6], which can induce permanent damage
in the conductor. In order to reduce this risk, a full metal stack can be used for the
routing paths where high absolute currents are expected to be the case.
5.2.2 Modeling of Coplanar Waveguide Networks Based on

Electromagnetic Simulations
The coplanar waveguide network models implemented in modern microwave CAD soft-
ware packages, such as Keysight ADS® or Qucs® , are usually based on closed-form
design equations available in literature [230, 231, 238], which are mostly derived by
using conformal mapping methods [7, 128]. These models usually assume that the com-
plete integrated circuit material stack is composed only from the topside and backside
metalization layers and a single-material dielectric substrate in between.
However, the material stack of modern MMIC technologies is more complex. In the
used GaN-on-SiC process, on top of the 75-um thick SiC substrate ("r ,SiC = 9:8 [239])
the thin AlGaN/GaN heterostructure is grown ("r ,AlGaN = 9:14 : : : 9:5, based on the Al
concentration [101]). The AlGaN/GaN heterostructure is protected by a SiN passivation
layer ("r ,Si3 N4 = 7:5 [240]), on top of which the gold metalization used for MET1 is
deposited. The MET1 is then further coated by a thin SiN layer, which is also used
as the dielectric layer in the MIM capacitors. An illustrative cross-sectional sketch of
the complete material stack (not to scale) of the used GaN-on-SiC MMIC technology is
provided in Fig. 5.27(a).
In order to allow for a rapid prototyping opportunity of high-frequency amplifiers using

the 25-μm CPW networks, a basic library including essential microwave network elements
has been developed with the aid of EM simulations. The library is wrapping-up the basic,
well-established CP W G circuit model available from the Keysight ADS® environment,
which is based on the closed-form design equations from [238]. The CP W G element
expects three design parameters of the CPW line, that is, its physical length, the width
of the signal trace, and the gap width between the signal trace and the topside ground
planes. The two latter parameters are indicated in Fig. 5.24(a) by dimensions s and
g , respectively. Moreover, a substrate definition is required, which includes the basic
physical and electrical properties of the dielectric material (thickness, dielectric constant
and loss tangent) as well as of the conductor material (thickness, surface roughness,
conductivity).
Since the CP W G element assumes that the material stack is composed only from the
topside and backside metalization layers and a single-material dielectric substrate in be-
tween, the actual full material stack shown in Fig. 5.27(a) needs to be simplified to its
effective version depicted in Fig. 5.27(b). This is achieved by performing 3D full-wave
EM simulation using the frequency-domain solver in CST Microwave Studio® of alike
CPW lines in both material stack variants from Fig. 5.27. The electrical properties of
the effective substrate material are adjusted accordingly, so that a good agreement with
the actual full material stack is achieved for all of the required signal trace widths over
a broad frequency range.
In Fig. 5.28, a comparison between the EM-simulated S -parameters and the character-
istic line impedance of a 100-μm long CPW line is shown. The signal trace’s width is
swept from 2 μm to 20 μm with a 2-μm step. This simulation experiment revealed that an
1.0j
0.5j 2.0j 100
Full stack Eff. stack
Full stack 90
Eff. stack
Line Impedance ( W)
80 2 µm
0.2j 5.0j
2 µm 70
60
0.2 0.5 1.0 2.0 5.0
S11 50
20 µm
-0.2j S21 -5.0j 40
30
20 µm
-0.5j -2.0j 20
0 50 100 150 200 250 300 350
-1.0j Frequency (GHz)
(a) (b)
Fig. 5.28. EM simulations of the of a CPW line for different signal trace widths using the actual full
(dashed) and simplified effective (solid) material stacks. (a) S11 and S21 on a 50-Ω Smith
chart. (b) Line characteristic impedance. The signal trace width ranges from 2 μm to 20 μm
with a 2-μm step. The line length is 100 μm in all cases. The simulation spans from 1 GHz to
330 GHz. The dielectric constant of the effective substrate material is "r ,eff = 10:45.
optimum fit between both material stacks shown in Fig. 5.27 is attained for a dielectric
constant of the effective substrate material of "r ,eff = 10:45.
This value may seem counter-intuitive at first, since neither of the materials of the full
stack shown in Fig. 5.27(a) has a dielectric constant above 10. However, the topside
metalization in the actual material stack is coated with SiN, whereas the simplified stack
assumes that the metal traces are “covered" by free space. Hence, in this case, the
effective dielectric constant needs to be higher than any of the involved materials to
account for this structural dissimilarity.
Furthermore, simplifying the full material stack to its effective form has another design-
related advantage. Although 3D full-wave EM simulations using the full material stack
provide the most accurate results, this type of approach implies a considerable compu-
tation cost [241]. In particular, modeling and generating the simulation mesh of the
thin dielectric layers increase substantially the duration of the simulation [241], which
can significantly expand the design cycle time. Therefore, extracting a reliable effec-
tive material stack can remarkably reduce the involved computational effort of the EM
simulation without a notable loss of accuracy [241].
Besides the aforementioned CPW transmission line model (based on the CP W G element
from the Keysight ADS® environment), the EM-extracted 25-μm CPW library contains
Port
3 1.0j
0.5j 2.0j
s=s2 s=s2
g=g2 g=g2 Model
l=g1/2 l=g1/2 EM full stack
Port Port 0.2j 5.0j

1 2
s=s1 s=s1 s=s1 S11 S31*
g=g1 g=g1 g=g1
l=g2/2 l=s2+g2 l=g2/2
(a)
0.2 0.5 1.0 2.0 5.0
Line width
S21
-0.2j -5.0j
4.5 µm
11.5 µm
15.5 µm
-0.5j -2.0j
-1.0j
(b) (c)
Fig. 5.29. Simulation model of the CPW T-junction. (a) Schematic model using CPW transmission lines,
after [117]. (b) EM model view in CST Microwave Studio® indicating the critical dimensions.
(c) Comparison of the simulated S -parameters using the schematic model (solid) and EM solver
with the full material stack (dashed) for 3 different signal line widths on a 50-Ω Smith chart.
The conjugate value of the S31 is used in order to visually separate it from the S21 response.
The simulation spans from 1 GHz to 330 GHz.
three further scalable basic circuit elements, which include a T-junction, a series MIM
capacitor, and a parallel-to-ground MIM capacitor.
The parasitic response of the T-junction is modeled with five transmission lines,
as proposed in [117] and illustrated in Fig. 5.29(a). In order to verify this approach,
the simulated response of this schematic model is compared with the EM simulation
including the full material stack of the 3D model shown in Fig. 5.29(b). The compared
-parameters for three different center conductor widths are plotted in Fig. 5.29(c). In
order to visually separate the and responses, the complex conjugate of the latter
parameter is used. One can note, that the agreement between both simulations is very
good up to 330 GHz.
The series MIM capacitor model includes an airbridge, the top and bottom plates, and
the capacitance, as shown in Fig. 5.30(a). The airbridge and the top plate are described
with a general transmission line model (the element from the Keysight ADS®
environment). The parameter values for both components are based on existing models
from the in-house 50-μm CPW passive PDK. The MIM capacitor is modeled using an
ideal lumped capacitor, which value is calculated as the product of its physical dimensions
and capacitance per area (0.25 fF/μm2 ). Finally, the bottom plate is represented by a
CPW transmission line. The corresponding 3D model of the series capacitor is shown in
Fig. 5.30(b). The simulated -parameters of the schematic model and the EM model
incorporating the full material stack are plotted in Fig. 5.30(c) for different physical
dimensions of the capacitor. Again, the agreement between the simulated responses up
to 330 GHz is considered as satisfactory.
Bottom
Top plate
Airbridge plate MIM
TLINP TLINP C
CPWG
(a)
(b)
(c)
Fig. 5.30. Simulation model of the CPW series MIM capacitor. (a) Schematic model. (b) EM model
view in CST Microwave Studio® . (c) Comparison of the simulated -parameters using the
schematic model (solid) and EM solver with the full material stack (dashed) for 4 different MIM
capacitor dimensions on a 50-Ω Smith chart. The simulation spans from 1 GHz to 330 GHz.
1.0j
0.5j 2.0j
Model
Half-top Half-top EM full stack
Airbridge plate
MIM
plate Airbridge
0.2j
MIM W L (µm2) 5.0j
12 7 12 20
TLINP TLINP
C
TLINP TLINP 25 7 25 20
0.2 0.5 1.0 2.0 5.0
(a)
-0.2j -5.0j
S11
S21
-0.5j -2.0j
-1.0j
(b)
(c)
Fig. 5.31. Simulation model of the CPW parallel MIM capacitor. (a) Schematic model. (b) EM model
view in CST Microwave Studio® . (c) Comparison of the simulated S -parameters using the
schematic model (solid) and EM solver with the full material stack (dashed) for 4 different MIM
capacitor dimensions on a 50-Ω Smith chart. The simulation spans from 1 GHz to 330 GHz.
The parallel-to-ground MIM capacitor is modeled using a similar approach as for the
above-described series capacitor. As can be seen from its schematic description shown
in Fig. 5.31(a), the parallel MIM capacitor is composed of two half top plates and two
airbridge connections. These elements are represented in the same manner as for the
series capacitor case, that is, with general T LINP transmission line models. In between
of the two half-top plates, the ideal lumped capacitor to ground is placed. Due to the
availability of a low-inductive ground connection in CPW, this simple model should be
valid also at high frequencies [117]. The 3D model of the parallel capacitor is shown
in Fig. 5.31(b), whereas a simulated comparison between the schematic model and EM
model including the full material stack for different MIM capacitor sizes is depicted in
Fig. 5.31(c). As can be seen, a reasonable agreement is achieved between the responses.
Experimental Verification of the Scaled Coplanar Waveguide Model Library
In order to experimentally evaluate the accuracy and scalability of the 25-μm CPW
passive library, respective test structures were fabricated for the above-described circuit
elements, that is, the T-junction, the series MIM capacitor, and the parallel-to-ground
MIM capacitor. The S -parameter measurements up to 220 GHz were performed with an
Anritsu VectorStar ME7838G VNA. In addition, an on-wafer line-reflect-reflect-match
(LRRM) calibration [242, 243] was applied to shift the reference planes directly at the
respective DUTs.
1.0
0.9
0.8
0.7
Stub W L (µm 2)
S21 (-)
0.6
11.5 300
0.5 11.5 350
0.4 11.5 400
3.5 300
0.3 3.5 350
0.2 3.5 400
Meas. 20 300
0.1 Sim. 20 350
0.0 20 400
0 20 40 60 80 100 120 140 160 180 200 220
Frequency (GHz)
(a) (b)
Fig. 5.32. Experimental verification of the 25-μm CPW T-junction with an open-circuit stub. (a) Micro-
graph of the test structures. From left to right: varying the center conductor width of the stub
- 11.5 μm (stub’s Z0 =50 Ω), 3.5 μm (75 Ω), and 20 μm (30 Ω). From top to bottom: varying
the length of the stub - 300 μm, 350 μm, and 400 μm. (b) Measured (solid) and simulated
(dashed) S21 response of the structures. The Z0 of all through lines is 50 Ω.
In an effort to enable two-port measurements, the T-junction model is verified by con-

necting an open- and short-circuit stub to its third port, as shown in Fig. 5.32(a) and
Fig. 5.33(a), respectively. In both cases, the length fo the stubs (300 μm, 350 μm, and
400 μm) as well as the width of the stub’s signal trace (11.5 μm, 3.5 μm, and 20 μm)
are varied. The variation of the stub’s signal trace width translates to a variation of its
characteristic impedance, that is, 50 Ω (11.5 μm), 75 Ω (3.5 μm), and 30 Ω (20 μm).
A comparison of the magnitude of S21 of measured open-circuit stub structures from
Fig. 5.32(a) with the respective simulated models is shown in Fig. 5.32(b). As already
discussed in Section 3.2, the open circuit is transformed to short circuit at a frequency
where the electrical length of the stub is equal to =4 or its odd-order multiples [123].
Therefore, a minimum in the S21 response of this type of structure is expected at these
frequencies. Moreover, a wider rejection bandwidth is anticipated for stubs with a lower
characteristic impedance, as has been described in Section 3.2 and illustrated in Fig. 3.14.
As can be seen in Fig. 5.32(b), there is a good agreement between the measured and
simulated locations of the S21 minima and a reasonable coherence between the measured
and simulated resonance depths. Besides evaluating the T-junction model, this experi-
ment verifies also the accuracy of the CPW transmission line model discussed before in
this section.
Analogously, the short circuit is transformed to open circuit at a frequency where the
electrical length of the stub is equal to =4 or its odd-order multiples [123]. Therefore, a
maximum in the S21 response of this type of structure is expected at these frequencies.
In this case, the minimum in the transmission coefficient is expected at 0 GHz, where
the “physical" short circuit exist, and at frequencies where the stub’s electrical length
corresponds to multiples of /2. As shown in Fig. 5.33(b), the agreement between the
measured and simulated responses can be considered as satisfactory, also at frequencies
approaching 200 GHz.
1.0
0.9
0.8
0.7
Stub W L (µm 2)
S21 (-)
0.6
11.5 300
0.5 11.5 350
11.5 400
0.4
3.5 300
0.3 3.5 350
0.2 3.5 400
Meas. 20 300
0.1 20 350
Sim.
0.0 20 400
0 20 40 60 80 100 120 140 160 180 200 220
Frequency (GHz)
(a) (b)
Fig. 5.33. Experimental verification of the 25-μm CPW T-junction with a short-circuit stub. (a) Micro-
graph of the test structures. From left to right: varying the center conductor width of the stub
- 11.5 μm (stub’s Z0 =50 Ω), 3.5 μm (75 Ω), and 20 μm (30 Ω). From top to bottom: varying
the length of the stub - 300 μm, 350 μm, and 400 μm. (b) Measured (solid) and simulated
(dashed) S21 response of the structures. The Z0 of all through lines is 50 Ω.
The accuracy and scalability of the parallel MIM capacitor model is evaluated by means
of the test structures shown in Fig. 5.34(a). In this case, both width (9.5 μm, 18 μm,
and 30 μm) and length (10 μm, 20 μm, and 40 μm) of the MIM capacitor are varied.
The comparison of the measured and simulated S21 parameter from Fig. 5.34(b) shows
a good agreement over the complete frequency range. The best agreement is noted
for the structures in which the width-to-length ratio is closer to unity, such as for the
9:5 10 μm2 , 30 20 μm2 , and 30 40 μm2 cases.
1.2 MIM W L (µm 2)

1.1 9.5 10 9.5 20 9.5 40
18 10 18 20 18 40
1.0 30 10 30 20 30 40
0.9
0.8
S21 (-)
0.7
0.6
0.5
0.4
0.3
0.2 Meas.
0.1 Sim.
0.0
0 20 40 60 80 100 120 140 160 180 200 220
Frequency (GHz)
(a) (b)
Fig. 5.34. Experimental verification of the 25-μm CPW parallel MIM capacitor. (a) Micrograph of the
test structures. From left to right: varying the MIM length - 10 μm, 20 μm, and 40 μm. From
top to bottom: varying the MIM width - 9.5 μm, 18 μm, and 30 μm. (b) Measured (solid) and
simulated (dashed) S21 response of the structures.
1.0
0.9
0.8
0.7
Meas.
S21 (-)
0.6
0.5 Sim.
0.4 MIM W L (µm 2)

9.5 10 9.5 20 9.5 40
0.3
14 10 14 20 14 40
0.2 18 10 18 20 18 40
0.1
0.0
0 20 40 60 80 100 120 140 160 180 200 220
Frequency (GHz)
(a) (b)
Fig. 5.35. Experimental verification of the 25-μm CPW series MIM capacitor. (a) Micrograph of the test
structures. From left to right: varying the MIM length - 10 μm, 20 μm, and 40 μm. From top
to bottom: varying the MIM width - 9.5 μm, 14 μm, and 18 μm. (b) Measured (solid) and
simulated (dashed) S21 response of the structures.
Finally, the series MIM capacitor model is validated with an alike test structure set,
shown in Fig. 5.35(a). Here, the MIM length is varied in the same manner as for the
parallel capacitor case (10 μm, 20 μm, and 40 μm), whereas the MIM width is swept as
9.5 μm, 14 μm, and 18 μm. The maximum width of the series MIM is constrained by the
design rules of the process, in particular by the minimum spacing between the MET1
structures of the capacitor’s bottom plate and the topside ground planes as well as the
enclosure rules regarding the process layers constituting the MIM capacitor. Again, the
agreement between the measured and simulated S21 responses shown in Fig. 5.35(b) is
good. One can note, that this agreement shows a slightly improving tendency with the
increasing overall area of the capacitor. This can indicate that the accuracy of the stray
field description is limiting the accurate modeling of small-area MIM capacitors.
5.2.3 Novel Compact Interstage Matching Network for Multi-Stage

High-Frequency GaN Amplifiers
The high-frequency gain of GaN HEMTs is still relatively modest, even though the re-
cent rapid technological progress [11–14]. Therefore, in order to realize practical GaN
amplifiers at higher mm-wave bands, the gain needs to be treated with a prioritized focus
by the designer.
In Section 4.1, employing different transistor topologies, such as the cascode configura-
tion, was proposed. Alternatively, the mm-wave gain of the common-source HEMT can
be improved by means of optimizing its layout geometry, as discussed in Section 5.1.
In order to obtain a further increase of the circuit-level gain, multiple stages implementing
the above-listed enhancements can be cascaded. However, as has been mentioned in
Section 5.2.1, including many stages can lead to a substantial expansion of the chip size,
VD
VG
(a) (b) (c)
Fig. 5.36. A novel compact interstage matching network for multi-stage high-frequency MMICs.
(a) Schematic. (b) Micrograph. (c) EM model view in CST Microwave Studio® .
which can prevent from applying the MMICs in phased-array systems or packaging them
in waveguide-based modules.
In amplifiers incorporating many gain stages, the interstage matching network (ISMN)
is the critical passive network. For any -stage amplifier, individual ISMNs are
necessary to be implemented. Therefore, the ISMN often defines the overall performance
of a multi-stage MMIC in terms of its bandwidth, gain, and size. The essential functions
of the ISMN can be summarized as follows:
• match the impedance seen at the drain of stage to the impedance seen at the
gate of stage ,
• provide the D bias to the drain of stage and the G bias to the gate of stage
, and
• provide a DC isolation between the D and G potentials.
On top of these functions, the ISMN should further provide enough matching band-
width for the required application, introduce as small insertion loss as possible to not
significantly hamper the circuit gain, and achieve an area which is as small as possible.
An interstage matching network example that fulfills the above-listed essential functions
is drawn schematically in Fig. 5.36(a). It uses a double-stub matching approach, which
should be able to provide enough bandwidth [33, 244, 245]. The stubs grant also injection
points for the drain and gate bias voltages, whereas the capacitor in between separates
the DC potentials.
In order to minimize the layout footprint of the amplifiers, the ISMN is implemented using
a compact approach that can be considered as an AC-coupled X-junction, as illustrated
in Fig. 5.36(b) and Fig. 5.36(c). The drain feeder is connected to the top plate of
an MIM capacitor and routed further upwards via the drain-bias stub. The gate feeder
and the gate-bias stub are connected via the bottom plate of the MIM capacitor. The
spacing between the drain feeder and the gate feeder of the following HEMT is only
45 μm, which allows for a relatively dense layout of MMICs comprising multiple stages.
The AC-coupled X-junction ISMN is modeled in a hybrid fashion. The core of this struc-
ture, that is, the MIM capacitor and short pieces of the transmission lines or airbridges,
are simulated entirely using the 3D EM solver in CST Microwave Studio® . The design
parameters, such as MIM width and length as well as the width of the stubs, are swept
during the simulation within the design rules’ constrains. In effect, an extensive look-up
table containing the 4-port S -parameter files is established, which can be afterwards
conveniently used for the circuit simulation. Nevertheless, the CPW transmission lines
representing the stubs and feeders as well as the parallel MIM capacitors are simulated
using the library elements described in Section 5.2.2. On the one hand, this approach
provides an accurate description of the AC-coupled X-junction’s core due to the 3D EM
simulation. On the other hand, this method simultaneously allows for a rapid prototyping
of the circuits, without the need of running a full EM simulation for each design iteration
once the mentioned look-up table is generated. The simulated insertion loss of the ISMN
is better than 1 dB within the G-band.
5.2.4 Examples of GaN Amplifiers Operating Beyond 200 GHz
The micrographs of the high-frequency amplifier MMICs are shown in Fig. 5.37(a)
(AMP1) and Fig. 5.37(b) (AMP2). These amplifiers consist of 10 reactively matched
common-source gain stages. All of the used HEMTs have asymmetric gate-source (LGS )
and gate-drain (LGD ) spacings. This transistor layout was experimentally verified in Sec-
tion 5.1.2 to show an improved RF performance over the symmetric spacing variant.
Each used transistor is a 4-finger device with an unit gate width of 20 μm for the AMP1
case and 18 μm for the AMP2 case. The unit gate width choice was based on the
high-frequency GaN HEMT sizing considerations provided in Section 5.1.3.
The matching networks are realized in a grounded CPW environment with a ground–
ground spacing of 25 μm, using the concepts and simulation models discussed in Sec-
tion 5.2.1 and Section 5.2.2, respectively. Due to a very high number of gain stages
used in the amplifiers, the ISMN is the critical part of the design with the highest im-
pact on the overall circuit’s performance as well as on the consumed chip area. In order
to minimize the layout footprint of the amplifiers, the ISMN is implemented using a
compact approach that can be considered as an AC-coupled X-junction, as illustrated in
Fig. 5.36(b) and described in Section 5.2.3.
(a) (b)
Fig. 5.37. Micrographs of the ten-stage amplifier MMICs. (a) AMP1 (1:55 0.8 mm2 ). (b) AMP2
(1:5 0.75 mm2 ).
Table 5.1. GaN technology variants used for the fabrication of the MMICs operating beyond 200 GHz.
Technology variant Heterostructure Gate length

Tech. A AlGaN/GaN with AlN interlayer 70 nm
Tech. B AlN/GaN 70 nm
Tech. C AlN/GaN 50 nm
Table 5.1 collects the technology variants used for the development of the 200-GHz
chips. These variants differ from each other in their heterostructure properties as well
as the gate length. The presented amplifiers were intended to be initially fabricated on a
wafer with an AlGaN barrier alloy and using a 70-nm gate length process variant (Tech.
A from Table 5.1). The small-signal HEMT model was extracted from a previously
processed wafer where a similar epitaxial stack was incorporated. The stability of the
circuits was simulated using the 4-Gamma method [131]. Examples of MMIC results
fabricated using the B and C variants are provided in the latter part of this section.
Measured Small-Signal Performance
The S -parameter measurements within the 130–225-GHz band were performed with an
Agilent N5254A PNA-X network analyzer and VDI WR5.1-VNAX extenders.
Figure 5.38(a) presents the S -parameter wafer mapping of the AMP1 MMIC, where
27 cells are considered. This amplifier can provide more than 15 dB of small-signal gain
over a 60-GHz band (from 145 GHz to 205 GHz) with a peak value of 30 dB at 155 GHz.
The homogeneity of the small-signal response over the wafer as well as the RF-yield
(73 %) of this circuit is excellent for such a high-frequency design, when considering
the high number of stages. The small-signal gain over the band of operation shows a
35 35
30 S11 S21 S22 30 S11 S21 S22
25 Meas. Sim. 25 Meas. Sim.
S-parameters (dB)
S-parameters (dB)
20 20
15 15
10 10
5 5
0 0
-5 -5
-10 -10
-15 -15
-20 -20
140 150 160 170 180 190 200 210 220 140 150 160 170 180 190 200 210 220
(a) (b)
Fig. 5.38. Measured (solid) and simulated (dashed) small-signal responses of the ten-stage amplifier
MMICs. (a) AMP1 (VDS = 11 V, ID = 200 mA/mm). Shown are 27 cells processed on the
wafer. (b) AMP2 (VDS = 12.5 V, ID = 200 mA/mm). Shown are 30 cells processed on the
wafer. Both circuits were fabricated using the Tech. A variant (Table 5.1).
20 4.0 20 4.0
Pin = 8 dBm
Pout (dBm), Gain (dB), DE (%)

195 GHz
18 3.6 18 3.6
16 3.2 16 3.2
14 2.8 14 2.8
PAE (%)
12 2.4
PAE (%)
12 2.4
10 2.0 10 2.0
8 1.6 8 1.6
6 1.2 6 1.2
4 0.8 4 0.8
P out
PAE
Pout PAE
2
Gain DE10
0.4 2 0.4
Gain DE10
0 0.0 0 0.0
-10 -8 -6 -4 -2 0 2 4 6 8 10 170 175 180 185 190 195 200 205
P in
(a) (b)
Fig. 5.39. Measured large-signal performance of the AMP1 circuit. (a) Input power CW sweep at
195 GHz. (b) Frequency CW response for a constant Pin = 8 dBm. The DE value is cal-
culated for the output stage only. Shown are 17 cells processed using the Tech. A variant
(Table 5.1). VDS = 11 V and ID = 200 mA/mm.
cell-to-cell variability of only about 1 dB over the complete wafer. This is equivalent to
an average HEMT-to-HEMT variability of approximately 0.3 dB across multiple sites
on the wafer (the variability of the HEMTs is assumed to follow a Gaussian distribution).
The agreement between the measurements and simulations is also considered as very
encouraging for the first design iteration, given the frequency of operation and complexity
of the circuit. This partially verifies the efficacy of the followed modeling approach of
the 25-μm CPW library and the compact interstage matching networks, discussed in
Section 5.2.2 and Section 5.2.3, respectively.
A similar wafer mapping of the AMP2 circuit is shown in Fig. 5.38(b). In this case,
the performance of 30 cells is displayed. This amplifier is able to deliver on average
10 dB of small-signal gain from 162 GHz to 217 GHz with still more than 7 dB up to
220 GHz, which is the upper boundary of the G-band. As before, the RF-yield (81 %)
and homogeneity (2 dB) of this amplifier are very encouraging, given the high frequency
of operation and the number of used stages. The kink in the measured S -parameters
at the higher end of the band seen in Fig. 5.38(a) and Fig. 5.38(b) origins from the
measurement setup.
Measured Large-Signal Performance
The on-wafer scalar continuous wave (CW) power measurements over the 170–220-GHz
band were performed with an Agilent N5254A PNA-X network analyzer cascaded with a
VDI WR4.3AMP module connected at the input side, and an ELVA G-band power sensor
connected to the output. Losses in the waveguides and probe tips were removed in a
calibration process in a similar manner as for the D-band large-signal characterization case
described in Section 4.1.4. Biasing the output stage separately allowed for evaluating
the drain efficiency (DE) of the used technology at the G-band.
Figure 5.39(a) depicts the measured large-signal performance of AMP1 for an input
power sweep at 195 GHz. As can be seen, this MMIC can provide up to 16.9 dBm of
20 4.0 20 4.0
Pin = 7 dBm

18 Pout PAE 205 GHz 3.6 18 Pout PAE 3.6
Gain DE10 Gain DE10
16 3.2 16 3.2
14 2.8 14 2.8
PAE (%)
12 2.4
PAE (%)
12 2.4
10 2.0 10 2.0
8 1.6 8 1.6
6 1.2 6 1.2
4 0.8 4 0.8
2 0.4 2 0.4
0 0.0 0 0.0
-10 -8 -6 -4 -2 0 2 4 6 8 10 170 175 180 185 190 195 200 205 210 215 220
P in
(a) (b)
Fig. 5.40. Measured large-signal performance of the AMP2 circuit. (a) Input power CW sweep at
205 GHz. (b) Frequency CW response for a constant Pin = 7 dBm. The DE value is cal-
culated for the output stage only. Shown are 30 cells processed using the Tech. A variant
(Table 5.1). VDS = 11 V and ID = 300 mA/mm.
output power, which corresponds to a power density of 613 mW/mm. The PAE of this
amplifier is 1.7 %, whereas the DE of the last stage alone (DE10 ) is 14 %. As shown in
Fig. 5.39(b), this PA can deliver more than 14 dBm of Pout from 185 GHz to 205 GHz
when driven with a constant input power of 8 dBm.
The large-signal performance of AMP2 is evaluated at 205 GHz, as plotted in
Fig. 5.40(a). At this frequency, this circuit can provide up to 15 dBm of output power or
439 mW/mm, with a corresponding PAE of 1.1 %. The DE of the last stage alone is in
this case around 10 %. Over a band from 170 GHz to 220 GHz, this power amplifier can
provide more than 12 dBm of output power when driven with a Pin = 7 dBm, as shown
in Fig. 5.40(b).
Enhancing the Large-Signal Performance at the G-Band with an AlN-Barrier

Epitaxy Variant
In an effort to further improve the large-signal performance at the G-band frequencies, a

wafer batch incorporating an AlN barrier has been grown and processed (Tech. B from
Table 5.1). As discussed in Section 2.4, a high aluminum content in the barrier alloy
amplifies the spontaneous polarization and piezoelectric effects in the GaN HEMT het-
erostructure, which results in a higher sheet carrier density of the 2DEG [71, 101–103].
Therefore, lower sheet resistances of the HEMT structure and thus greater output power
densities on transistor level can be expected [71, 103].
The large-signal data at 200 GHz of the AMP1 processed with an AlN barrier (Tech. B
from Table 5.1) is presented in Fig. 5.41(a). The saturated output power in this case is
reaching 18 dBm, which corresponds to an output power density of 788 mW/mm. Hence,
incorporating an AlN barrier allows for a 1.1-dB or 29 % improvement in this measure
when compared to the AlGaN variant (Tech. A from Table 5.1) performance shown in
Fig. 5.39(a). It is also worth noting that the output power at the 1-dB gain compression
point is about 16 dB. The measured maximum PAE and the output-stage-only DE of
20 2.0 20 2.0
Pin = 5 dBm
18 1.8 18 1.8
16 1.6

16 1.6
14 1.4 14 1.4
PAE (%)
PAE (%)
12 1.2 12 1.2
10 1.0 10 1.0
8 0.8 8 0.8
P out
6 0.6 6 0.6
Gain Pout
4 0.4 4 0.4
PAE Gain
2
200 GHz
0.2 2 0.2
DE10 PAE
0 0.0 0 0.0
-10 -8 -6 -4 -2 0 2 4 6 8 10 160 170 180 190 200 210 220
P in
(a) (b)
Fig. 5.41. Measured large-signal performance of the AMP1 circuit processed with an AlN barrier (Tech.
B variant from Table 5.1). (a) Input power CW sweep at 200 GHz. The DE value is calculated
for the output stage only. VDS = 12 V and ID = 400 mA/mm. (b) Frequency CW response for
a constant Pin = 5 dBm. VDS = 10 V and ID = 400 mA/mm.
this circuit at 200 GHz is 1.45 % and 11 %, respectively. Over a band from 170 GHz
to 205 GHz, this power amplifier can provide more than 14 dBm of output power when
driven with a constant input power of 5 dBm, as shown in Fig. 5.41(b).
Figure 5.42(a) depicts the large-signal performance of AMP2 at 210 GHz that was pro-
cessed with an AlN-barrier variant (Tech. B from Table 5.1). In this case, the maximum
Pout is 17 dBm, which corresponds to an output power density of 694 mW/mm. This
result indicates an improvement of the output power by 2 dB or 58 % when compared to
the AlGaN variant (Tech. A from Table 5.1) performance shown in Fig. 5.40(a). The
Pout at the 1-dB gain compression point for this MMIC is about 14 dBm. The measured
peak PAE and the output-stage-only DE of this circuit at 210 GHz is 1.5 % and 14 %,
20 2.0 20 2.0
18 1.8 18 Pin = 5 dBm 1.8

16 1.6
16 1.6
14 1.4 14 1.4
PAE (%)
PAE (%)
12 1.2 12 1.2
10 1.0 10 1.0
8 0.8 8 0.8
P out
6 0.6 6 0.6
Gain Pout
4 0.4 4 0.4
PAE Gain
2
210 GHz
0.2 2 0.2
DE10 PAE
0 0.0 0 0.0
-10 -8 -6 -4 -2 0 2 4 6 8 10 160 170 180 190 200 210 220
P in
(a) (b)
Fig. 5.42. Measured large-signal performance of the AMP2 circuit processed with an AlN barrier (Tech.
B variant from Table 5.1). (a) Input power CW sweep at 210 GHz. The DE value is calculated
for the output stage only. VDS = 12 V and ID = 300 mA/mm. (b) Frequency CW response for
a constant Pin = 5 dBm. VDS = 10 V and ID = 300 mA/mm.
(a) (b)
Fig. 5.43. H-band ten-stage amplifier GaN MMIC AMP3. (a) Micrograph of the fabricated chip using
the Tech. C variant from Table 5.1 ( 0.62 mm ). (b) Measured (solid) and simulated
(dashed) small-signal performance ( DS 10 V and D 400 mA/mm).
respectively. As demonstrated in Fig. 5.42(b), after applying a constant input power of

5 dBm, this PA can provide more than 12 dBm from 170 GHz to 215 GHz.
Scaling the Gate Length for Operation Towards 300 GHz
The ultimate and long-term goal of the development presented within this thesis is
to establish circuit design solutions that allow GaN-based power amplifier to dominate
the complete mm-wave spectrum, that is, from 30 GHz up to 300 GHz. In order to
address the H-band (220–325 GHz) spectrum with GaN, a ten-stage amplifier (AMP3)
was designed and its micrograph is shown in Fig. 5.43(a). It uses similar design concepts
as the two previous circuits presented in Fig. 5.37 and described before in this section.
The AMP3 circuit was intended to be fabricated using an experimental processing variant
with the gate length scaled down to 50 nm and on a wafer incorporating an AlN barrier
alloy (Tech. C variant from Table 5.1). Due to the experimental nature of this process
variant, no HEMT model was available at the time of design. Instead, a “best-guess"
approach has been followed to adjust the existing in-house GaN HEMT model in order
to predict the high-frequency performance of its scaled version. Each transistor used in
the AMP3 is a 4-finger device with an unit gate width of 12.5 μm.
The measured and simulated small-signal performance of the AMP3 within the H-band
is plotted in Fig. 5.43(b). The simulated peak small-signal is about 10 dB near 300 GHz.
However, the measured performance of this circuit shows a maximum gain of 4.2 dB at
265 GHz. This discrepancy comes from an inaccurate prediction of the scaled HEMT
devices, in particular its drain-source parameters, as can be concluded from comparing
the measured and simulated responses. Furthermore, the discrepancy on transistor
level is significantly amplified by the high number of cascaded stages on the measured
circuit level.
24 [246] [146]
23
[154]
22 IAF Teledyne
Output Power (dBm)
21
Sec. 4.1.3
HRL NGC
20 JPL IHP
19 [247] [156] [250]
18 [24]
17 [248]
Sec. 5.1.4
16 GaN HEMT
15 InP HEMT [249]
14 InP HBT Sec. 5.2.4
13 SiGe HBT [21]
12
140 150 160 170 180 190 200 210 220
Frequency (GHz)
Fig. 5.44. State-of-the-art G-band power amplifier MMICs.
Nevertheless, this result marks the first-ever demonstration of a GaN amplifier operating
at the H-band. The measured small-signal gain is better than 0 dB up to 277 GHz,
which is to date the highest-ever frequency of amplification achieved with a GaN-based
technology. Further efforts in maturing the scaled technology variant combined with
an accurate modeling description should also allow for GaN MMICs operating beyond
300 GHz in the foreseeable future.
Comparison with the State of the Art
The available data on G-band GaN amplifiers published in prior works are still limited and
are summarized in Table 5.2 and depicted in Fig. 5.44. HRL Laboratories showed a single
pre-matched common-source transistor operating up to 205 GHz with 4.5 dB of small-
signal gain [21]. This single-stage amplifier can provide 13.8 dBm (24 mW) of Pout at
180 GHz, with a corresponding PAE and output power density of 3.5 % and 300 mW/mm,
respectively [21]. Furthermore, a five-stage common-source amplifier was designed by
NASA JPL in the Raytheon’s 150-nm process [24]. It can deliver up to 8.7 dB of small-
signal gain at 149 GHz. When connecting two modules in series, 18.2 dBm (66 mW) of
output power can be achieved at 147 GHz, with a corresponding PAE and output power
density of 1.7 % and 660 mW/mm, respectively [24]. Therefore, the amplifiers presented
in this chapter show the highest gain and output power levels achieved with GaN-based
technology to date. This is also the first demonstration of multi-stage GaN circuits
which can provide gain beyond the 200-GHz mark.
Despite the continuous improvements in high-frequency GaN HEMT technology, the
performance gap at the G-band to other semiconductor technologies is still signifi-
Table 5.2. State-of-the-art G-band power amplifier MMICs.
Frequency jS21 j Pout, max PAEmax GT @Pmax

Reference MMIC Topology Technology§
(GHz) (dB) (dBm) (%) (dB)
this work
4-stage cascode 100-nm GaN HEMT 107–148 25–34 21yy 2.8yy 21yy
(Section 4.1.3)
this work 4-stage CS 162–192 7.5–10.5 – – –
100-nm GaN HEMT
(Section 5.1.4) 5-stage CS 150–189 10–13 15.8zz 2.4zz 11.8zz
this work 16.9y,a 1.7y,a 7.9y,a
10-stage CS (AMP1) 70-nm GaN HEMT 145–205 15–30
(Section 5.2.4) 18z,b 1.45z,b 9z,b
this work 15*,a 1.1*,a 7*,a
10-stage CS (AMP2) 70-nm GaN HEMT 162–217 7.5–15
(Section 5.2.4) 17#,b 1.5#,b 8#,b
this work
10-stage CS (AMP3) 50-nm GaN HEMTb 256–277 0–4.2 – – –
(Section 5.2.4)
[21] 1-stage CS 40-nm GaN HEMT 140–205 2.5–4.5 13.8zz 3.5zz 1.8zz
[23] 6-stage CS 40-nm GaN HEMT 110–170 25–30 12 (sim.) – –
5.2 Advancing GaN Amplifiers Beyond 200 GHz
[24] 5-stage CS 150-nm GaN HEMT 140–150 7–8.7 18.2$,M 1.7$,M 10$,M
[146] 3-stage cascode 250-nm InP HBT 185–255 14–28 24z 4.1z 9z
[154] 3-stage cascode 250-nm InP HBT 210–230 19–22 22.6+ – –
[246] 5-stage CE 250-nm InP HBT 160–183 18–21 23.9## 7.5## 13.9##
[156] 3-stage cascode 130-nm SiGe HBT 158–200 19.9–25.9 18.1** 3.5* 15**
[247] 3-stage cascode 130-nm SiGe HBT 168–195 20–23.6 18.7## 4.4## 15##
[248] 4-stage diff. cascode 130-nm SiGe HBT 155–180 27.2–30.2 18## 4.0## 22.5##
[249] 3-stage diff. cascode 130-nm SiGe HBT 140–220 18–20 15zz 3.5zz 9zz
[250] 4-stage CS sub-50-nm InP HEMT 205–225 15–18 18.8#,M 3.7#,M 10.4#,M
§
the technology node refers to the gate length (HEMTs) or emitter width (HBTs) of the used process
a b M yy zz y
CE: common emitter AlGaN-barrier AlN-barrier in fixture/module 140 GHz 180 GHz 195 GHz
z * # $ ## + **
200 GHz 205 GHz 210 GHz 147 GHz with two modules in series 170 GHz 214 GHz 185 GHz
141
cant. In [146], a state-of-the-art G-band PA developed in an InP HBT technology

was presented. Due to the sufficient gain offered by the 250-nm InP HBT technology
(fT > 400 GHz and fmax > 650 GHz), a large number of transistors could be combined
on-chip in the output stage. The three-stage power amplifier using 16-way power combin-
ing and cascode gain-cells can provide up to 24 dBm of output power at 200 GHz [146].
This impressive result is approximately 6-dB or 4 higher than the best G-band power
level shown in this thesis. However, in this work the maximum Pout near 200 GHz was
achieved using only a single transistor cell in the output stage of the circuit. Further-
more, the recent G-band results demonstrated with SiGe-based power amplifiers exhibit
a very promising performance [156, 247–249], with output power levels comparable to
the ones shown in this work. Nonetheless, similarly as for the InP PA cases, multiple
transistors need to be combined on-chip in order to reach these output power figures.
Despite offering very high power densities at mm-wave frequencies, GaN HEMTs show
still rather limited available gain levels above 100 GHz. Therefore, the transistor’s high-
frequency gain has to be considered as one of the most precious resources of the per-
formance budget. This chapter has discussed several design approaches for enabling
operation of GaN-based amplifiers at the G-band (140–220 GHz) and beyond. In partic-
ular, enhancing the high-frequency gain on transistor level by optimizing the geometrical
properties of an HEMT device, as well as coplanar network scaling for enabling multi-
stage amplifiers operating beyond 200 GHz have been investigated.
One of the possible layout-based modifications of a GaN HEMT with a pronounced effect
on its high-frequency performance is optimizing the gate-drain and gate-source spacings.
Such modification impacts the effective-intrinsic parameters of the transistor, which sig-
nificantly influence the high-frequency gain, as analyzed in Section 5.1.1. This approach
was also experimentally verified in Section 5.1.2, where a transistor with an asymmet-
ric spacing layout was found to show a better high-frequency small-signal performance
compared to a symmetric layout variant.
Another attainable alternative for improving the performance of high-frequency GaN
circuits is proper dimensioning of the transistors. Section 5.1.3 discussed GaN-specific
output impedance aspects arising from an increased operating voltage when compared
to other high-speed semiconductor technologies. This section provided also an analysis
on selecting an optimum GaN HEMT geometry for G-band applications.
Although implementing the design methods discussed in Section 5.1 can considerably
enhance the high-frequency gain of GaN devices on transistor level, many of such HEMT
stages need to be cascaded in oder to obtain a practical circuit-level gain. Therefore,
scaling the passive networks is a crucial effort to support GaN circuits operating at
higher mm-wave bands, as discussed in Section 5.2.1. In amplifiers incorporating many
gain stages, the interstage matching network is the critical passive network, which often
defines the overall performance of a multi-stage MMIC in terms of its bandwidth, gain,
and size. A novel compact interstage layout is proposed in Section 5.2.3, which allowed
to advance the performance of GaN-based circuits towards the terahertz frontier.
In order to demonstrate the attractiveness and feasibility of the aforementioned de-

sign approaches, various broadband GaN MMICs targeting G-band operation have been
showcased in Section 5.1.4 and Section 5.2.4. These amplifiers offer the highest gain
and output power among the reported GaN-based PAs to date. It is also the first-ever
demonstration of GaN circuits able to operate beyond the 200-GHz mark and showing
a promising outlook for reaching 300 GHz. The state-of-the-art performance achieved
with these circuits sets several new benchmarks for high-frequency GaN technology.
145
6 Conclusions
This thesis investigates several approaches to enhance the performance of GaN-based
circuits operating within the millimeter-wave spectrum. The main goal of this work is to
provide a set of design approaches and techniques in order to enable broadband operation
of mm-wave GaN power amplifier MMICs, with a particular focus on frequencies close
to and beyond the 100-GHz mark. These efforts are primarily driven by the emerging
and often bandwidth-craving applications that are projected to utilize these frequencies
in imaging, next-generation communication, and scientific instrumentation systems, as
discussed in Section 2.1.
6.1 Summary and Conclusions of the Thesis

Chapter 2 highlights the necessity of developing power amplifiers operating within the
millimeter-wave spectrum and discussed whether GaN can be the technology of choice
for supporting these efforts.
Due to its unique combination of high breakdown voltage and high electron velocity,
amplifiers based on GaN HEMTs have dominated the state-of-the-art tables up to ap-
proximately 100 GHz (see Section 2.3), where they are able to offer more than a twofold
output power advantage over the competing semiconductor technologies. However, de-
spite the continued improvement of GaN HEMT technology, the high-frequency gain of
the transistors appears still as the restraining factor in closing the performance gap to
other semiconductor processes above 100 GHz. Hence, employing GaN technology for
power amplifiers targeting higher mm-wave frequency bands leads to operating near or
already above the fT values provided by the transistors.
In Chapter 3, several aspects regarding the design of passive networks in application for
mm-wave GaN power amplifiers are discussed. In particular, the main focus is put on
optimizing the bandwidth performance of two key passive parts of any active MMIC,
namely the matching and DC-biasing networks.
Matching network design has, besides the capabilities of the active devices, a decisive
impact on the overall performance of the circuit. The optimal matching network design
by incorporating low-impedance transmission lines can push the circuit’s bandwidth per-
formance closer towards the theoretical limits set by the Bode-Fano criterion and the
often-necessary transformation of the real part of the impedance. Additionally, minimiz-
ing the loss of the networks is another critical requirement in order to allow for a desired
compression behavior of the driving stages of a PA, as well as enhancing its output
power and PAE. Both of the aforesaid demands can be fulfilled by using low-impedance
microstrip lines, however, at a cost of an increased chip area. Moreover, employing
wide microstrip lines can lead to several parasitic effects, such as triggering higher-order
146 6 Conclusions
propagation modes. Therefore, extensive EM-simulations accompanied by experimental

verifications of the used models is a crucial measure for achieving a first-pass design
success.
The amplifier’s bandwidth can be also enhanced by improving the performance of the
DC-bias networks. The radial stub has been identified as a key element of such networks
for mm-wave MMIC applications. In Section 3.2, a novel topology approach to the
radial stub with a superior bandwidth performance is introduced. By using two slightly
separated half-stubs, a second in-band resonance is created. As a result, this radial
stub can provide a nearly two-fold improvement over the conventional radial stub in the
rejection fractional bandwidth. As the performance improvement is achieved without
any substantial increase of area, the novel stub is a well-suited candidate for bandwidth
enhancement of the DC-bias paths of active circuits. Furthermore, the development of
the novel radial stub with an optimized input reflection response concept, described in
Section 3.2.7, is subject to a German patent application filing [P11].
Chapter 4 covers enhancing the performance of mm-wave GaN power amplifiers by em-
ploying different transistor topologies. In particular, the main focus is put on increasing
the high-frequency gain of the amplifier with cascode configuration and optimizing the
bandwidth performance with an fT -doubler pair.
The improved reverse isolation of the cascode results in a significantly higher MSG of
this topology when compared with the common-source configuration. Therefore, the
cascode topology appears as an appealing alternative for applications in GaN power
amplifiers operating at the higher mm-wave bands, where the available gain of GaN
HEMTs is limited. However, appropriate measures have to be taken in order to ensure
in-band stability of cascode-based amplifiers, since the cascode suffers from a typical
phenomenon where the magnitude of S22 is exceeding unity above a certain frequency,
resulting in a potentially instable device at higher frequencies.
Alternatively to the passive networks design considerations provided in Chapter 3, a wide-
band performance can be achieved also by employing more advanced transistor topolo-
gies, such as the Darlington pair or the fT -doubler, which both enhance the current gain
of transistors in the utilized semiconductor process. However, applying these topologies
at mm-wave frequencies is a challenging task due to the layout-induced parasitic effects
that degrade the high-frequency performance.
In Section 4.2.3, an fT -doubler topology employing a novel integrated layout based on
GaN HEMTs is described, together with an experimental evaluation of its performance
shown in Section 4.2.4. The compact approach described in this part of the thesis
allows for minimizing the layout-induced parasitic effects, which enables operation at
high frequencies. The development of the integrated fT -doubler layout concept described
there is subject to German and U.S. patent application filings [P8, P13].
Chapter 5 analyzes several design approaches for enabling operation of GaN-based am-
plifiers at the G-band (140–220 GHz) and beyond. In particular, enhancing the high-
frequency gain on transistor level by optimizing the geometrical properties of an HEMT
device, as well as coplanar network scaling for enabling multi-stage amplifiers operating
beyond 200 GHz is investigated.
One of the possible layout-based modifications of a GaN HEMT with a pronounced effect
on its high-frequency performance is optimizing the gate-drain and gate-source spacings.
6.1 Summary and Conclusions of the Thesis 147
Such modification impacts the effective parameters of the transistor, which significantly
influence the high-frequency gain, as analyzed in Section 5.1.1. This approach is also
experimentally verified in Section 5.1.2, where a transistor with an asymmetric spacing
layout was found to show a better high-frequency small-signal performance compared to
a symmetric layout variant.
Another attainable alternative for improving the performance of high-frequency GaN
circuits is proper dimensioning of the transistors. Section 5.1.3 discusses GaN-specific
output impedance aspects arising from an increased operating voltage when compared
to other high-speed semiconductor technologies. This section provides also an analysis
on selecting an optimum GaN HEMT geometry for G-band applications.
Although implementing the design methods investigated in Section 5.1 can considerably
enhance the high-frequency gain of GaN devices on transistor level, many of such HEMT
stages need to be cascaded in oder to obtain a practical circuit-level gain. This brings
scaling of the passive networks as a crucial effort to support GaN circuits operating at
higher mm-wave bands, as discussed in Section 5.2.1. In amplifiers incorporating many
gain stages, the interstage matching network is the critical passive network, which often
defines the overall performance of a multi-stage MMIC in terms of its bandwidth, gain,
and size. A novel compact interstage network layout is proposed in Section 5.2.3, which
allows to advance the performance of GaN-based circuits beyond the 200-GHz frontier.
From a millimeter-wave GaN power amplifier designer’s perspective, the essential con-
clusions and takeaways emerging from this dissertation can be summarized as follows.
• GaN-based transistors offer superior output power levels within the mm-wave spec-
trum, which is enabled by a unique combination of their material properties. How-
ever, at frequencies above approximately 100 GHz, the transistor’s gain becomes a
limiting factor in implementing high-performance power amplifiers.
• The high-frequency gain of GaN amplifiers can be enhanced on different design
levels. On the circuit level, the designer can improve the broadband and high-
frequency MMIC performance by means of optimizing the passive networks used
for impedance matching and bias distribution (see Chapter 3 and Section 5.2) as
well as by considering various circuit topologies (see Chapter 4). Furthermore,
the high-frequency gain enhancement can be attained also on transistor level by
appropriate layouting and dimensioning of the active devices (see Section 4.2 and
Section 5.1). In order to obtain optimum circuit performance, these concepts often
need to be implemented simultaneously.
• Employing low-impedance microstrip lines can aid in broadband and low-loss match-
ing network design (see Section 3.1), allowing for high-power full-waveguide-band
amplifiers. However, one needs to take special care after preventing higher-order
parasitic modes from propagating within the band of interest.
• In addition to the matching networks, the operating bandwidth of the power ampli-
fier can be increased also due to optimizing the DC-biasing networks. For instance,
a novel type of a radial stub can show a nearly two-fold improvement of the rejec-
tion bandwidth over its conventional counterpart, without any noticeable penalty
in terms of chip area consumption (see Section 3.2).
• The cascode topology is an attractive alternative for high-gain power amplifiers
operating above 100 GHz, even though this topology has been so far a rather
148 6 Conclusions
unorthodox choice within the designer’s community for GaN MMICs operating at
such high frequencies. The improved reverse isolation of the cascode results in a
significantly higher MSG of this topology when compared with the common-source
configuration. However, appropriate measures have to be taken in order to ensure
in-band stability of amplifiers utilizing the cascode configuration.
• A broadband performance of mm-wave power amplifiers covering several waveguide
bands can be achieved also by applying an fT -doubler topology, which enhances the
available current gain and presents more favorable input impedance levels, when
compared with the common-source configuration. A novel compact integrated lay-
out approach described in Section 4.2.3 allows for minimizing the parasitic effects,
which enables operation at frequencies approaching 100 GHz.
• Operation of GaN-based amplifiers can be pushed further up to the 200-GHz mark
due to geometry-based modifications of the active devices. In particular, optimizing
the gate-drain and gate-source spacings has been identified in Section 5.1 to show a
pronounced effect on the transistor’s high-frequency performance. An asymmetric
layout variant has been verified experimentally to provide an improved performance
over the symmetric variant.
• One of the critical aspects of designing high-frequency GaN circuits is proper di-
mensioning of the transistors, which is due to the GaN-specific output impedance
levels arising from an increased operating voltage when compared to other high-
speed semiconductor technologies. As discussed in Section 5.1.3, selecting too
small transistor geometry, which is usually desired for high-frequency operation,
can lead to impractical output impedances presented by the HEMT. Thus, a proper
trade-off analysis needs to be executed beforehand.
• Finally, GaN amplifiers operating beyond 100 GHz require cascading a high number
of stages to achieve practical circuit-level gain. In such multi-stage MMICs, the
interstage matching network is the critical passive network, which often defines
the overall circuit performance. A novel compact interstage approach utilizing
scaled CPW networks proposed in Section 5.2.3 allows to advance GaN amplifier
performance beyond the 200-GHz mark.
6.2 Impact of the Work on the State of the Art

The concepts developed within the scope of this thesis which are summarized in the
previous section provide a design framework for high-performance GaN power amplifiers
operating at upper millimeter-wave frequency bands. In order to demonstrate the at-
tractiveness and feasibility of the aforementioned design approaches, various broadband
GaN MMICs targeting operation from the Ka-band (26.5–40 GHz) up to the G-band
(140–220 GHz) have been showcased in the respective sections of this work.
An overlay of the measured small-signal gain of the amplifiers developed in this thesis
over the complete mm-wave frequency range is aggregated in Fig. 6.1, with the corre-
sponding references and chip micrographs provided. As can be noticed, the presented
amplifier set is able to tightly cover most of the mm-wave spectrum, providing more than
10 dB of gain from Ka-band through G-band. Figure 6.2 illustrates the output power
6.2 Impact of the Work on the State of the Art 149
35
30
25
Sec. 4.1.3
Gain (dB)
20 Sec. 4.2.5
Sec. 5.2.4
Sec. 3.3
15
10
Sec. 5.2.4
5
Sec. 5.2.4
0
25 50 75 100 125 150 175 200 225 250 275 300
Frequency (GHz)
Fig. 6.1. Small-signal gain performance over the entire mm-wave spectrum of selected amplifier MMICs
developed within this thesis.
levels obtainable from these amplifiers, which range from approximately 15 dBm beyond
200 GHz to nearly 30 dBm within the W-band. The design examples described in this
work validate the attractiveness of employing GaN-based amplifiers for supporting high-
demanding applications also at upper mm-wave bands, in particular beyond the 100-GHz
mark.
In Section 3.3, two full W-band GaN amplifiers are presented. The circuits utilize low-
impedance microstrip lines for reactive matching and the novel type of radial stub in the
DC-bias paths, i.e., the concepts that are discussed in Sections 3.1 and 3.2, respectively.
All together, these measures resulted in power amplifiers that can deliver on average
25.6 dBm (three-stage) and 27 dBm (four-stage) over a 70–110-GHz band. A peak
30
Sec. 3.3
25
Output Power (dBm)
Sec. 4.2.5 Sec. 4.1.3

20
Sec. 5.2.4
15
Sec. 5.2.4
10
0
25 50 75 100 125 150 175 200 225 250 275 300
Frequency (GHz)
Fig. 6.2. Output power performance over the entire mm-wave spectrum of selected amplifier MMICs
developed within this thesis.
150 6 Conclusions
output power of 28.6 dBm is obtained at 80 GHz, corresponding to a PAE of 8.6 %.

To date, no other reported single solid-state circuit can deliver such power levels over
the full W-band. Enabled by the used technology, the high RF-power density up to
2.6 W/mm allows for achieving much higher absolute power levels when more HEMTs
are combined, making wideband 1-W+ MMICs feasible for the foreseeable future. Such
devices could ease the design of high-resolution radar systems with exceptional properties
and high-data-rate communication links with unprecedented bandwidths.
Section 4.1 describes a power amplifier able to cover a significant part of the D-band
(110–170 GHz), which demonstrates the attractiveness of the cascode topology and its
feasibility in high-frequency GaN-based circuits. The four-stage cascode power amplifier
can cover the 107–148-GHz band with more than 25-dB of small-signal gain. Over the
120–145-GHz band, it can deliver on average 23.3 dBm of output power and 5.2 % of
PAE. The 120-GHz peak values of the output power and power-added efficiency are
26.4 dBm and 16.5 %, respectively, with transducer gain exceeding 26 dB at saturation.
The combination of the small- and large-signal parameters of this amplifier establishes
new benchmarks for solid-state power amplifiers operating at such high frequencies.
Section 4.2 introduces two amplifiers able to cover several mm-wave waveguide bands,
which demonstrate the potential of the fT -doubler topology using the novel integrated
layout approach for broadband MMIC applications. These circuits can provide a small-
signal gain better than 10 dB and output power ranging between 14.5 dBm to 20.6 dBm
from about 28 GHz up to 90 GHz. This corresponds to a fractional operating bandwidth
of 105 % or 1.68 octaves. These amplifiers are able to provide a full coverage of multiple
mm-wave waveguide bands, including the Ka-band (26.5–40 GHz), Q-band (33–50 GHz),
U-band (40–60 GHz), V-band (50–75 GHz), and the E-band (60–90 GHz). Furthermore,
none of the FET-based fT -doubler or Darlington amplifiers reported to date is able to
operate at such high frequencies.
Finally, various broadband GaN MMICs targeting G-band (140–220 GHz) operation are
showcased in Section 5.1.4 and Section 5.2.4. These amplifiers incorporate the afore-
mentioned design concepts regarding optimal dimensioning and layouting of GaN HEMTs
as well as CPW passive network scaling for high-frequency applications. The presented
G-band MMICs offer the highest gain and output power among the reported GaN-based
PAs to date. It is also the first-ever demonstration of GaN circuits able to operate be-
yond the 200-GHz mark and showing a promising outlook for reaching 300 GHz. The
state-of-the-art performance achieved with these circuits sets several new benchmarks
for high-frequency GaN technology.
The above-listed results achieved within this thesis are put into perspective of the state-
of-the-art mm-wave power amplifiers employing various high-speed semiconductor tech-
nologies in Fig. 6.3, where the reported output power values from prior works are based
on the data collected in [85]. Furthermore, a more detailed comparison with the state-
of-the-art results can be found in the respective sections describing the measured per-
formance of the particular circuits. Observing the absolute output power values as well
as the visible trends plotted in Fig. 6.3, the following conclusions can be drawn.
• Besides the results presented in this work, there are only a handful of GaN amplifier
examples operating beyond 100 GHz. This indicates that the research on high-
frequency GaN technology is still on a relatively early stage when compared with
some other competing technologies.
6.2 Impact of the Work on the State of the Art 151
45
GaN SiGe GaAs
40
InP CMOS This work
Output Power (dBm)

35
30
25
20
15
10
5
0
30 50 75 100 150 200 300
Frequency (GHz)
Fig. 6.3. State-of-the-art overview of mm-wave power amplifiers as of August 2021. Based on the data
collected in [85]. The indicative trend lines are based on data points of GaN amplifiers operating
below (dashed) and above (dotted) 100 GHz. InGaAs mHEMT amplifiers are categorized under
GaAs.
• The circuits developed within this thesis are able to set several new benchmarks for
high-frequency GaN technology, such as the highest gain and output power within
G-band or the highest reported frequency of operation of a GaN-based amplifier.
• The state-of-the-art tables for power amplifiers operating at the G-band are cur-
rently dominated by InP HBT and, to lesser extent, SiGe HBT technologies. The
transistors in these process variants provide enough high-frequency gain for devel-
oping more complex circuits, with multi-way on-chip power combining techniques
included. For instance, a state-of-the-art InP power amplifier can provide up to
24 dBm of output power at 200 GHz [146]. This MMIC combines 16 HBTs in
its output stage, which may be already approaching the limits of on-chip power
combining and circuit complexity at such high frequencies.
• The above-mentioned impressive result is approximately 6-dB or 4 higher than the
best G-band power level shown in this thesis. However, in this work the maximum
output power near 200 GHz was achieved using only a single transistor cell in the
output stage of the circuit.
• In addition, two trend lines are sketched for indicative purposes in Fig. 6.3. They
are based on the data points of GaN power amplifiers operating below (dashed line)
and above (dotted line) the 100-GHz mark. As can be seen, the “low” frequency
GaN HEMT technology is much more mature and able to better exploit the high-
power capabilities offered by GaN-based material systems. Therefore, it can be
believed that GaN still carries a significant potential for performance improvement
also at “high” mm-wave frequencies, both technology-wise as well as circuit-design-
wise. With the continued advancement of this technology, the dotted line should
converge towards the dashed one, and ultimately enable GaN MMICs to dominate
the complete mm-wave spectrum in terms of the output power.
153
A General Two-Port Formulation of

the fT-Doubler Configuration
This appendix provides a general two-port formulation of the fT -doubler configuration
discussed in Section 4.2.
The fT -doubler topology consists of a pair of two-port active devices that are arranged
as displayed in Fig. A.1. These two-port devices are described with their respective
admittance matrices, YA and YB , where the following relations hold:

I1 YA11 YA12 VA1
I3
= YA YA VA ; (A.1)
21 22 2
and
I4 YB11 YB12 VB1
I5
= YB YB VB : (A.2)
21 22 2
The supplementary DC path for device YA is represented in Fig. A.1 with the impedance
ZS , which can be, for instance, an RL-network as demonstrated in Fig. 4.11(b).
Using the relations listed in (A.1) and (A.2), the currents in the circuit from Fig. A.1 are
given as
I1 = YA11 VA1 + YA12 VA2 ; (A.3)
I3 = YA 21 VA1 + YA 22 VA2 ; (A.4)
VA1
I1
[Y ] A
I3
VA2
I2
I1 +I3
V1
I1 +I3-I4
I4
[Y ] B
I5
V2
VB1 VB2
ZS
Fig. A.1. Schematic illustration of an fT -doubler configuration with general two-port devices.
154 A General Two-Port Formulation of the fT -Doubler Configuration
I4 = YB 11 V 1 B + YB B
12 V 2 ; (A.5)
I5 = YB 21 V 1 B + YB B
22 V 2 : (A.6)
Moreover, one can note that
I2 = I3 + I5 ; (A.7)
VA1 = V1 VB1 ; (A.8)
VA2 = V2 VB1 ; (A.9)
VB1 = Z S (I 1 + I 3 I4 ; ) (A.10)
and
VB2 = V2 : (A.11)
After inserting (A.8) and (A.9) into (A.3) and (A.4), one gets
I1 = Y A (V 1
11 VB1 ) + Y A (V 2
12 VB1 ) = YA 11 V1 + YA 12 V2 (Y A + Y A )V B
11 12 1 (A.12)
and
I3 = Y A (V 1
21 VB1 ) + Y A (V 2
22 VB1 ) = YA 21 V1 + YA 22 V2 (Y A + Y A )V B ;
21 22 1 (A.13)
respectively. In order to evaluate I2 , (A.6) and (A.13) can be summed as defined by

(A.7):
I2 = I 3 + I 5 = Y A (V 1 V B ) + Y A (V 2 V B ) + Y B
21 1 22 1 B
21 V 1 + YB VB 22 2
= Y A V 1 + (Y A + Y B ) V 2 ( Y A + Y A
21 22 22 21 22 Y B )V B :
21 1
(A.14)
The value of VB1 can be resolved by inserting (A.5), (A.12), and (A.13) into (A.10):
VB1= Z S (I 1 + I 3 I 4 ) = Z S Y A V 1 + Y A V 2 (Y A + Y A )V B + : : :
11 12 11 12 1
(A.15)
: : : + YA V1 + YA V2
21 (Y A + Y A ) V B Y B V B Y B V B ;
22 21 22 1 11 1 12 2
or after rearranging (A.15) with ZS = 0, 6
VB =
( Y A + Y A ) V 1 + (Y A + Y A Y B ) V 2 :
11 21 12 22 12
1 + Y + Y + Y + +Y + Y
1
(A.16)
A A A A B 11 12 21 22 11
Z S
In order to obtain a general two-port formulation of the circuit from Fig. A.1, it is
necessary to develop an effective admittance matrix YE , where the following relation
holds:
I1
I2
= YE11 YE12
YE21 YE22
V1
V2
: (A.17)
155
The individual elements of YE can be derived by inserting (A.16) into (A.12) and (A.14),
which can be thereafter expressed as
YA11 + YA21
YE11 = YA11 (YA11 + YA12 )
1
;
(A.18)
+ YB11 + YA
ZS
YA12 + YA22 YB12

YE12 = YA12 (YA11 + YA12 ) ;
1 (A.19)
+ YB11 + YA
ZS
YA11 + YA21
YE21 = YA21 + (YB21 YA21 YA22 ) ;
1 (A.20)
+ YB11 + YA
ZS
and
YA12 + YA22 YB12
YE22 = YA22 + YB22 + (YB21 YA21 YA22 ) ;
1 (A.21)
+ YB11 + YA
ZS
where !
YA = YA11 + YA12 + YA21 + YA22 : (A.22)
Assuming that both active devices are identical (e.g., two transistors of the same size and
operating at the same bias point), that is YA = YB = Y , equations (A.18)–(A.21)
can be simplified to
Y11 + Y21
YE11 = Y11 (Y11 + Y12 ) ;
1 (A.23)
+ Y11 + Y
ZS
Y22
YE12 = Y12 (Y11 + Y12 ) ;
1 (A.24)
+ Y11 + Y
ZS
Y11 + Y21
YE21 = Y21 Y22 ;
1 (A.25)
+ Y11 + Y
ZS
and
2
Y22
YE22 = 2Y22 ;
1 (A.26)
+ Y11 + Y
ZS
where !
Y = Y11 + Y12 + Y21 + Y22 : (A.27)
157
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List of Personal Publications
[P1] M. Ćwikliński, C. Friesicke, P. Brückner, D. Schwantuschke, R. Lozar,

H. Maßler, S. Wagner, and R. Quay, “First Full W-Band GaN Power Ampli-
fier MMICs with Novel Broadband Radial Stubs and 50 GHz of Bandwidth,”
in IEEE MTT-S International Microwave Symposium (IMS), Philadelphia, PA,
USA, Jun. 2018, pp. 757–760.
[P2] R. Weber, M. Ćwikliński, S. Wagner, R. Lozar, H. Maßler, P. Brückner, and
R. Quay, “A Beyond 110 GHz GaN Cascode Low-Noise Amplifier with 20.3 dBm
Output Power,” in IEEE MTT-S International Microwave Symposium (IMS),
Philadelphia, PA, USA, Jun. 2018, pp. 1499–1502.
[P3] M. Ćwikliński, C. Friesicke, F. van Raay, H. Maßler, R. Quay, and O. Ambacher,
“A Novel Type of Broadband Radial Stub,” in European Microwave Conference
(EuMC), Madrid, Spain, Sep. 2018, pp. 1093–1096.
[P4] P. Brückner, S. Krause, M. Ćwikliński, M. Dammann, and R. Quay,
“IAF GaN-Technology Development Towards 100 GHz and Beyond,” in Inter-
national Workshop on Nitride Semiconductors (IWN), Kanazawa, Japan, Nov.
2018.
[P5] M. Ćwikliński, C. Friesicke, P. Brückner, D. Schwantuschke, S. Wagner,
R. Lozar, H. Maßler, R. Quay, and O. Ambacher, “Full W-Band GaN Power
Amplifier MMICs Using a Novel Type of Broadband Radial Stub,” IEEE Trans-
actions on Microwave Theory and Techniques, vol. 66, no. 12, pp. 5664–5675,
Dec. 2018.
[P6] M. Ćwikliński, P. Brückner, S. Leone, C. Friesicke, R. Lozar, H. Maßler,
R. Quay, and O. Ambacher, “190-GHz G-Band GaN Amplifier MMICs with 40
GHz of Bandwidth,” in IEEE MTT-S International Microwave Symposium (IMS),
Boston, MA, USA, Jun. 2019, pp. 1257–1260.
[P7] M. Ćwikliński, R. Quay, and P. Brückner, “Wideband Design Techniques for
mm-Wave Gallium Nitride MMICs,” in WME: Millimeter-Wave Power Amplifier
Design Innovations Workshop Notes of the 2019 IEEE MTT-S International
Microwave Symposium (IMS), Boston, MA, USA, Jun. 2019.
[P8] M. Ćwikliński, “Integrierter Schaltkreis,” German Patent No.
DE 10 2019 216 400, filed Oct. 24, 2019, issued Feb. 11, 2021.
[P9] M. Ćwikliński, P. Brückner, S. Leone, C. Friesicke, H. Maßler, R. Lozar, S. Wag-
ner, R. Quay, and O. Ambacher, “D-Band and G-Band High-Performance GaN
Power Amplifier MMICs,” IEEE Transactions on Microwave Theory and Tech-
niques, vol. 67, no. 12, pp. 5080–5089, Dec. 2019.
178 List of Personal Publications
[P10] R. Quay, M. Dammann, T. Kemmer, P. Brückner, M. Ćwikliński, D. Schwan-

tuschke, S. Krause, S. Leone, and M. Mikulla, “Deep Submicron III-N HEMTs –
Technological Development and Reliability,” in IEEE International Electron De-
vices Meeting (IEDM), San Francisco, CA, USA, Dec. 2019, pp. 17.1.1–17.1.4.
[P11] M. Ćwikliński, “Filterschaltung und deren Verwendung sowie
HF-Aktivschaltung,” German Patent Application No. DE 10 2020 208 612.5,
filed Jul. 9, 2020.
[P12] M. Ćwikliński, P. Brückner, S. Leone, S. Krause, C. Friesicke, H. Maßler,
R. Quay, and O. Ambacher, “First Demonstration of G-Band Broadband GaN
Power Amplifier MMICs Operating Beyond 200 GHz,” in IEEE MTT-S Inter-
national Microwave Symposium (IMS), Los Angeles, CA, USA, Aug. 2020, pp.
1117–1120.
[P13] M. Ćwikliński, “Integrated Circuit,” U.S. Patent Application No.
US 2021 0126 096, filed Oct. 22, 2020.
[P14] M. Ćwikliński, P. Brückner, S. Leone, C. Friesicke, F. van Raay, S. Wagner, and
R. Quay, “A 28–90-GHz GaN Power Amplifier MMIC Using an Integrated fT -
Doubler Topology,” in IEEE MTT-S International Microwave Symposium (IMS),
Atlanta, GA, USA, Jun. 2021, pp. 606–609.
179
List of Figures
2.1 Specific atmospheric attenuation within the millimeter-wave spectrum. . 7
2.2 Visual representation of the millimeter-wave waveguide bands. . . . . . 8
2.3 Example of a W-band airborne imaging system. . . . . . . . . . . . . . 9
2.4 Theoretical Friis’ free-space path loss for mm-wave wireless links. . . . 10
2.5 Comparison of selected material properties of semiconductors used in
millimeter-wave applications. . . . . . . . . . . . . . . . . . . . . . . . 12
2.6 State-of-the-art overview of millimeter-wave power amplifiers as of
September 2016. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7 State-of-the-art overview of millimeter-wave power amplifiers as of Au-
gust 2021. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.8 Fraunhofer IAF 100-nm AlGaN/GaN HEMT. . . . . . . . . . . . . . . 15
2.9 Technology cross-section of the Fraunhofer IAF 100-nm GaN-on-SiC pro-
cess. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10 Location of the simulated load impedances presented to the single-stage
test amplifiers’ transistors on a 50-Ω Smith chart with their corresponding
values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.11 Prematched test amplifier with the nominal ZL . . . . . . . . . . . . . . 17
2.12 Prematched RL -Low test amplifier with a decreased real part of the
nominal ZL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.13 Prematched RL -High test amplifier with an increased real part of the
nominal ZL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.14 Prematched XL -Low test amplifier with a decreased imaginary part of
the nominal ZL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.15 Prematched XL -High test amplifier with an increased imaginary part of
the nominal ZL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Matching scenario for a single-stage power amplifier with a unilateral

large-signal model of the input and output impedances of a HEMT in a
common-source configuration. . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Calculated Bode-Fano output and input matching limits for a
4 32:5-μm GaN HEMT as a function of the targeted return loss. . . . 25
3.3 Impact of the characteristic impedance of the =4-transformer on the
Q-factor and Bode-Fano limit of input matching of a 4 32:5-μm GaN
HEMT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Matching scenario representation for evaluation of the dissipative loss of
the input and output matching networks . . . . . . . . . . . . . . . . . 28
3.5 Cross-sectional view of the microstrip and grounded coplanar waveguide
transmission lines with an illustrative distribution of the electric and mag-
netic fields of the respective quasi-TEM modes. . . . . . . . . . . . . . 29
180 List of Figures
3.6 Calculated impact of the microstrip line width on its characteristic

impedance and conduction loss. . . . . . . . . . . . . . . . . . . . . . 30
3.7 Calculated threshold frequency for the transverse resonance in a mi-
crostrip line in the used GaN-on-SiC MMIC technology. . . . . . . . . . 32
3.8 Micrographs of the processed breakout structures for the W-band input
and output matching networks evaluation. . . . . . . . . . . . . . . . . 33
3.9 Loss evaluation of the W-band microstrip test structures. . . . . . . . . 33
3.10 Evaluation of the matching bandwidth performance of the W-band mi-
crostrip breakout structures. . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 EM-simulated loss of the MSL-to-CPW transition. . . . . . . . . . . . 35
3.12 EM-simulation of the field distribution at the MSL-to-CPW transition. . 36
3.13 Microstrip realizations of a shunt open-circuit quarter-wavelength stub. 37
3.14 Simulated S21 response of ideal shunt open-circuit quarter-wavelength
stubs for two different characteristic impedances. . . . . . . . . . . . . 38
3.15 Geometry of a conventional radial stub. . . . . . . . . . . . . . . . . . 38
3.16 Existing solutions to bandwidth enhancement of the radial stub. . . . . 39
3.17 Geometry of the novel separated radial stub. . . . . . . . . . . . . . . 40
3.18 Modeling approach to the novel separated radial stub. . . . . . . . . . 41
3.19 Model verification of the novel radial stub. . . . . . . . . . . . . . . . . 42
3.20 Comparison of the calculated S -parameters of the novel radial stub for
two vertex-coupling capacitance values. . . . . . . . . . . . . . . . . . 43
3.21 Impact of the vertex-coupling capacitance value on the performance of
the stub. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.22 Micrographs of the fabricated radial stub test structures. . . . . . . . . 44
3.23 Measured and simulated S -parameters of the three types of radial stubs
in single-sided configuration. . . . . . . . . . . . . . . . . . . . . . . . 45
3.24 Measured and simulated S -parameters of the three types of radial stubs
in double-sided configuration. . . . . . . . . . . . . . . . . . . . . . . . 46
3.25 Simplified lumped LC -model of the novel stub for analytical calculations. 47
3.26 Pole-zero map of the calculated S -parameters of the simplified LC -model
of the novel radial stub. . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.27 Layout-based optimization of the input reflection performance of the
novel radial stub. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.28 Model verification of the novel radial stub with an optimized input re-
flection response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.29 Simplified lumped LC -model of the optimized novel stub for analytical
calculations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.30 Pole-zero map of the calculated S -parameters of the simplified LC -model
of the optimized novel radial stub. . . . . . . . . . . . . . . . . . . . . 52
3.31 Micrographs of the fabricated test structures of the optimized novel stub
in single-sided and double-sided configurations. . . . . . . . . . . . . . 52
3.32 Measured and EM-simulated S -parameters of the optimized novel radial
stubs in single-sided and double-sided (butterfly) configurations. . . . . 53
3.33 Comparison of the measured S -parameters of the optimized and non-
optimized novel radial stub. . . . . . . . . . . . . . . . . . . . . . . . . 53
3.34 Micrographs of the fabricated full W-band GaN power amplifiers. . . . . 54
3.35 Simplified schematic of the four-stage power amplifier. . . . . . . . . . 55
List of Figures 181
3.36 Simulated S21 of the four-stage power amplifier within the W-band for
different radial stub configurations. . . . . . . . . . . . . . . . . . . . . 55
3.37 Measured and simulated small-signal responses of the W-band power
amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.38 Measured and re-simulated small-signal responses of the three-stage W-
band GaN power amplifiers using a re-tuned HEMT model. . . . . . . . 57
3.39 Measured and simulated CW frequency responses of the W-band GaN
power amplifiers for a constant Pin = 15 dBm. . . . . . . . . . . . . . . 57
3.40 Measured transducer gain and PAE versus output power for CW ope-
ration at different frequencies of the three-stage amplifier. . . . . . . . 58
ration at different frequencies of the four-stage amplifier. . . . . . . . . 58
3.42 State-of-the-art W-band GaN power amplifier MMICs. . . . . . . . . . 59
4.1 The cascode topology. . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.2 Small-signal performance comparison of a measured 4 20-μm GaN cas-
code cell with a simulated 4 20-μm GaN CS HEMT. . . . . . . . . . 66
4.3 Micrograph of the fabricated D-band power amplifier MMIC. . . . . . . 67
4.4 Circuit schematic of a single branch of the D-band power amplifier. . . 67
4.5 Comparison of the measured small-signal performance of the 4 20-μm
cascode cell used during the design phase and a mapping of the wafer on
which the D-band PA was processed. . . . . . . . . . . . . . . . . . . . 68
4.6 Simplified large-signal design analysis of a single branch of the D-band
power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.7 Measured and simulated small-signal response of the D-band power am-
plifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ration at different frequencies of the D-band power amplifier for a Pout -
optimized bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ration at different frequencies of the D-band power amplifier for an
efficiency-optimized bias. . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.10 Measured CW frequency response of the D-band power amplifier for a
constant Pin = 0 dBm, at an efficiency-optimized and a Pout -optimized
quiescent bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.11 Schematic illustration of the Darlington and fT -doubler configurations. . 74
4.12 Small-signal equivalent circuit representation of the fT -doubler configu-
ration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.13 Small-signal equivalent circuit representation of the fT -doubler in its com-
pound form with series and parallel rgs -Cgs configurations. . . . . . . . . 76
4.14 Comparison of the simulated S -parameters of the fT -doubler’s small-
signal equivalent circuit representation in its compound and effective
common-source-like forms. . . . . . . . . . . . . . . . . . . . . . . . . 78
4.15 Simulated gate-source voltage and drain current distributions for each
HEMT of the small-signal equivalent circuit of the fT -doubler for different
shunt RL-network configurations. . . . . . . . . . . . . . . . . . . . . 83
182 List of Figures
4.16 Influence of the phase imbalance between D1 and D2 on the high-

frequency performance of the fT -doubler. . . . . . . . . . . . . . . . . 84
4.17 Influence of the parasitic inductance in the S1 /G2 path on the high-
frequency performance of the fT -doubler. . . . . . . . . . . . . . . . . 85
4.18 Schematic and small-signal equivalent circuit of the AC-coupled fT -doubler. 86
4.19 Simulated small-signal performance comparison of an AC-coupled fT -
doubler and a DC-coupled fT -doubler for two gate-source voltages of
Q2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.20 Proposed integrated layout approach to an fT -doubler cell. . . . . . . . 88
4.21 Micrograph of the fabricated 2 2 45-μm integrated AC-coupled
fT-doubler test cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.22 Wafer mapping of the h21 and MSG/MAG of a fabricated 2 2 45-μm
integrated AC-coupled fT -doubler. . . . . . . . . . . . . . . . . . . . . 90
4.23 Integrated AC-coupled fT -doubler cell in two layout variants. . . . . . . 91
4.24 Wafer mapping of the h21 and MSG/MAG of a fabricated 2 2 45-μm
integrated AC-coupled fT -doubler in variants “A" and “B". . . . . . . . 91
4.25 Micrograph of the three-stage fT -doubler amplifier MMICs. . . . . . . . 92
4.26 Measurement results of 11 samples of the fT -doubler AMP1 amplifier. . 93
4.27 Measurement results of the fT -doubler AMP2 amplifier. . . . . . . . . . 93
5.1 Simplified cross-section overview of a GaN HEMT device. . . . . . . . 98

5.2 Small-signal equivalent circuit model for a common-source HEMT. . . . 99
5.3 Analytic investigation of the fT sensitivity of a HEMT. . . . . . . . . . 100
5.4 Analytic investigation of the fmax sensitivity of a HEMT. . . . . . . . . 102
5.5 Analytic investigation of the MSG sensitivity of a HEMT. . . . . . . . 103
5.6 Frequency dependency of the MSG sensitivity to the small-signal equiv-
alent circuit elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.7 Measured bias dependence of the normalized gm for a symmetric and
asymmetric gate-source and gate-drain spacing variant. . . . . . . . . . 106
5.8 Measured bias dependence of the normalized Cgs for a symmetric and
5.9 Measured bias dependence of the normalized rgs for a symmetric and
5.10 Measured bias dependence of the normalized Cgd for a symmetric and
5.11 Measured bias dependence of the normalized rgd for a symmetric and
5.12 Measured bias dependence of the normalized Cds for a symmetric and
5.13 Measured bias dependence of the normalized gds for a symmetric and
5.14 Measured bias dependence of fT for a symmetric and asymmetric gate-
source and gate-drain spacing variant. . . . . . . . . . . . . . . . . . . 111
5.15 Measured bias dependence of fmax for a symmetric and asymmetric gate-
source and gate-drain spacing variant. . . . . . . . . . . . . . . . . . . 111
5.16 Measured bias dependence of the MSG at 100 GHz for a symmetric and
List of Figures 183
5.17 Calculated dependency of the normalized on-state resistance of a 100-nm

GaN HEMT on its gate-drain spacing for a fixed gate-source distance. . 113
5.18 Simulated dependency of the output resistance and capacitance of a
GaN HEMT for a conjugate-complex matching scenario at 180 GHz on
the unit gate width and number of gate fingers . . . . . . . . . . . . . 115
5.19 Simulated dependency of the MAG and input reactance for a conjugate-
complex matching scenario of a GaN HEMT at 180 GHz on the unit gate
width and number of gate fingers. . . . . . . . . . . . . . . . . . . . . 116
5.20 Simulated available gain and power gain circles of a 4 23-μm HEMT
at 180 GHz on a 50-Ω Smith chart. . . . . . . . . . . . . . . . . . . . 117
5.21 Micrographs of the fabricated G-band GaN power amplifiers MMICs. . . 118
5.22 Measured and simulated small-signal responses of the G-band GaN am-
plifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.23 Measured large-signal CW response of the five-stage G-band amplifier. 119
5.24 Cross-sectional view of the grounded coplanar waveguide transmission
line with indication of its crucial dimension parameters and an illustrative
distribution of the electromagnetic field of the even propagation mode. 121
5.25 Cross-sectional view of the grounded coplanar waveguide transmission
line with an illustrative distribution of the electric field of the parasitic
slotline and parallel-plate propagation modes. . . . . . . . . . . . . . . 122
5.26 Calculated conduction, radiation, and total loss per unit length of a 50-Ω
grounded CPW transmission line for different values of the GG spacing. 124
5.27 Cross-sectional view of the actual and effective material stack of the
grounded coplanar waveguide transmission line in the used GaN-on-SiC
MMIC technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.28 EM simulations of the S -parameters and the line impedance of a CPW
line for different signal trace widths using the full and effective material
stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.29 Simulation model of the CPW T-junction. . . . . . . . . . . . . . . . . 127
5.30 Simulation model of the CPW series MIM capacitor. . . . . . . . . . . 128
5.31 Simulation model of the CPW parallel MIM capacitor. . . . . . . . . . 129
5.32 Experimental verification of the 25-μm CPW T-junction with an open-
circuit stub. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.33 Experimental verification of the 25-μm CPW T-junction with a short-
circuit stub. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.34 Experimental verification of the 25-μm CPW parallel MIM capacitor. . . 131
5.35 Experimental verification of the 25-μm CPW series MIM capacitor. . . 132
5.36 A novel compact interstage matching network for multi-stage high-
frequency MMICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.37 Micrographs of the ten-stage amplifier MMICs. . . . . . . . . . . . . . 134
5.38 Measured and simulated small-signal responses of the 10-stage amplifier
MMICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.39 Measured large-signal performance of the AMP1 circuit. . . . . . . . . 136
5.40 Measured large-signal performance of the AMP2 circuit. . . . . . . . . 137
5.41 Measured large-signal performance of the AMP1 circuit processed with
an AlN barrier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
184 List of Figures
5.42 Measured large-signal performance of the AMP2 circuit processed with

an AlN barrier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.43 H-band ten-stage amplifier GaN MMIC AMP3. . . . . . . . . . . . . . 139
5.44 State-of-the-art G-band power amplifier MMICs. . . . . . . . . . . . . 140
6.1 Small-signal gain performance over the entire mm-wave spectrum of se-
lected amplifier MMICs developed within this thesis. . . . . . . . . . . 149
6.2 Output power performance over the entire mm-wave spectrum of selected
amplifier MMICs developed within this thesis. . . . . . . . . . . . . . . 149
6.3 State-of-the-art overview of millimeter-wave power amplifiers as of Au-
gust 2021. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
A.1 Schematic illustration of an fT -doubler configuration with general two-

port devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
185
List of Tables
2.1 Millimeter-wave waveguide frequency bands. . . . . . . . . . . . . . . . 8
2.2 Selected material properties of semiconductors used in millimeter-wave
applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Large-signal measurement results of the single-stage test amplifiers at
94 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Comparison of simulated and measured absolute and fractional rejection

bandwidths of three types of stubs. . . . . . . . . . . . . . . . . . . . . 46
3.2 State-of-the-art W-band high-power MMICs. . . . . . . . . . . . . . . 60
4.1 State-of-the-art D-band power amplifier MMICs. . . . . . . . . . . . . 73

4.2 Simulated small-signal parameters of an fT -doubler composed of two
2 45-μm HEMTs with the analogous parameters of 2 45-μm and
4 45-μm CS devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3 State-of-the-art FET-based Darlington and fT -doubler amplifiers. . . . 94
5.1 GaN technology variants used for the fabrication of the MMICs operating
beyond 200 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.2 State-of-the-art G-band power amplifier MMICs. . . . . . . . . . . . . 141
187
Acknowledgments
This thesis summarizes my work at the Fraunhofer Institute for Applied Solid State
Physics (IAF) in Freiburg, Germany. Conducting this extensive research project would
not be possible without the excellent scientific contribution and support that I have
received during my time at the institute, which is a very special place with a great
density of highly talented people.
First and foremost, I would like to greatly thank Prof. Rüdiger Quay for giving me the
opportunity to start this exciting research adventure and be a part of the excellent team
at the Fraunhofer IAF, even without having any prior RF circuit design experience. He
had always provided me with the necessary support and guidance as well as encouraged
me to do brave designs and set my goals very high.
I would like to also express my gratitude for Prof. Dietmar Kissinger for acting as the
Second Examiner of this thesis.
I am also extremely thankful to Dr. Friedbert van Raay and Christian Friesicke, who
were closely mentoring me over the complete course of my work. Without their support,
many of the ideas would certainly still stay in my head. I am also eternally grateful for
the numerous hours they have invested in correcting and improving this thesis as well as
my scientific publications and patent applications.
I also wish to very warmly thank the members of the Technology and Epitaxy departments
at Fraunhofer IAF, with a particular acknowledgment of Dr. Peter Brückner and Dr.
Stefano Leone. If developing high-speed integrated circuits can be compared to racing
in Formula One, I am confident to say that you have always provided me with a top-class
car.
Furthermore, I would like to also acknowledge the High-Frequency Measurement Team
at Fraunhofer IAF, namely Hermann Maßler, Sandrine Wagner, Roger Lozar, Stephan
Ockenfuß, and Thomas Maier, for their great support in organizing my non-standard
characterization requests on multiple occasions and (usually) on a short notice before
the paper submission deadlines.
I thank also Prof. Rüdiger Quay, Dr. Jutta Kühn, Dr. Michael Mikulla, and Prof.
Oliver Ambacher for their outstanding leadership, which resulted in acquisition of many
interesting research projects, in which I had the privilege to participate in and contribute
to.
I also wish to send my special thanks to all of the colleagues that helped to make my time
at the institute such a pleasant experience by creating a great working atmosphere. In
particular, I would like to thank my office roommates, namely Birgit Wiessman-Thaden,
Markus Weiß, Dr. Ana Bélen Amado Rey, and Felix Heinz for filling up the office with
good energy and for helping me to significantly improve my German skills. Further-
more, I thank also Sebastian Krause, Dr. Fabian Thome, and Dr. Erdin Ture for many
inspirational discussions during both office hours as well as happy hours.
188 Acknowledgments
Finally, I would like to express my great gratitude to my loved ones. I want to thank my
dear and incredible wife Ania from the bottom of my heart for your enormous support,
tons of motivation, providing inspiration in naming the chips, and for showing a lot
of understanding for my long working hours before tapeouts. It would not be possible
without you! I would also like to thank to my parents and family for their support, for
helping me in making the right decisions, and for sparking an interest in science very
early in my life.
Gallium nitride (GaN) high-electron-mobility transistor (HEMT) technology appears
as an appealing candidate for supporting a variety of millimeter-wave (mm-wave)
applications with its unique combination of simultaneous high-voltage and high-
frequency operation. However, despite the rapid advance in GaN HEMT technology,
the reported available gain of the devices is still limited at higher mm-wave
frequencies in comparison to the competing high-speed semiconductor processes.
This work investigates several approaches to enhance the performance of GaN-

based circuits operating within the mm-wave spectrum. The main aim is to provide
a set of design approaches and techniques to enable broadband operation of
mm-wave GaN power amplifier monolithic microwave integrated circuits (MMICs),
with a particular focus on frequencies close to and beyond the 100-GHz mark. In
order to fulfill this goal, these approaches need to simultaneously target distinct
design levels. Furthermore, implementing the concepts investigated in this work on
circuit-level result in several MMICs providing state-of-the-art performance among
GaN-based power amplifiers.
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Science for Systems

Design of Millimeter-Wave Power

Science for Systems

Cover illustration: Fraunhofer IAF

Bibliographic information of the German National Library:

ISBN (print edition): 978-3-8396-1867-7

Zugl.: Freiburg, Univ., Diss. 2022

Print and finishing:

The book was printed with chlorine- and acid-free paper.

© Fraunhofer Verlag, 2022

is a constituent entity of the Fraunhofer-Gesellschaft, and as such has no separate legal

Fraunhofer-Gesellschaft zur Förderung

Freiburg im Breisgau, Germany

Date of the Examination

HEMTs führt im Vergleich zur Common-Source-Konﬁguration zu einer deutlich höheren

List of Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix

2 Fundamentals of Gallium Nitride Millimeter-Wave Power Ampliﬁers . . . . . 7

3 Passive Network Considerations for Broadband GaN Power Ampliﬁers . . 21

3.3.2 Impact of the Radial Stub Conﬁguration on the MMIC

4 Topology-Based Performance Enhancements of GaN Power Ampliﬁers . . 63

5 Layout Considerations for G-Band GaN Ampliﬁers . . . . . . . . . . . . . . 97

A General Two-Port Formulation of the fT -Doubler Conﬁguration . . . . . 153

List of Personal Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

2DEG Two-dimensional electron gas

FBW Fractional bandwidth

MSL Microstrip line

1.2 Objectives and Organization of the Thesis

GaN transistors have demonstrated so far output power levels up to about

2 Fundamentals of Gallium Nitride

2.1 Millimeter-Wave Frequencies

20 30 50 75 100 150 200 300

Band designation Frequency range Ampliﬁer examples in this work

(a) (b) (c)

Free-space path loss (dB)

2.2 Gallium Nitride for High-Frequency Applications

Material parameter GaN GaAs InP Si SiGe SiC

Breakdown field (MV/cm)

Fig. 2.5. Comparison of selected material properties of semiconductors used in mm-wave

Output Power (dBm)

2.3 Overview of State-of-the-Art Millimeter-Wave

Output Power (dBm)

2.4 Millimeter-Wave GaN HEMT Technology

METG HEMT NiCr Resistor

2.5 Experimental Veriﬁcation of the HEMT Model at

Pout (dBm), DE (%)

(a) (b) (c)

Pout (dBm), DE (%)

Circuit Gain at Pin = 0 dBm Pout, max DEmax

2.6 Conclusions on Chapter 2

3 Passive Network Considerations for

3.1 Broadband and Low-Loss Matching Networks

3.1.1 The Broadband Impedance Matching Problem

Cin Rin Rout Cout

Bode-Fano Limit for Output Matching

As can be seen from the unilateral large-signal model of a HEMT in a CS conﬁguration

BWmax,out = f< RoutCout

Alternatively, using the quality factor Q of the output load,

BWmax,out = f < Q f0 : ln

Bode-Fano Limit for Input Matching

! d! < !0 RC:

Bode-Fano Limit (GHz)

Bode-Fano Criterion and a Full-Waveguide-Band Power Ampliﬁer Design Case

BWmax,out = f < Q f0 : ln

! d! < !0 RC:

4Y02 LT CS CS2 jCs