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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
A 2–20-GHz 10-W High-Efficiency GaN Power
Amplifier Using Reactive Matching Technique
Qian Lin , Hai-Feng Wu , Yu-Nan Hua, Yi-Jun Chen, Liu-Lin Hu, Lin-Sheng Liu, and Shan-Ji Chen
Abstract— In this article, we present the analysis, design,
and implementation of a wideband 10-W monolithic microwave
integrated circuit power amplifier (PA), fabricated in a low-cost
0.1-µm gallium nitride (GaN) on Si technology. The design is
focused on the realization of a low-loss and wideband impedance
transformation networks across 2–20 GHz using a reactive
matching (RM) technique. The two-stage GaN PA achieves an
average output power of 40.1 dBm and a peak output power of
41.6 dBm at 13 GHz, in the CW-mode operation, with a small-
signal gain of S21 > 25.5 dB over the entire bandwidth. The
average power-added efficiency (PAE) is 21%, with a peak PAE
of 29% at 6 GHz. The PA chip occupies an area of 2.9×2.6 mm2 .
To the best of our knowledge, the PA presented in this work
demonstrates the highest broadband gain among the reported
GaN-based RMPAs with a corresponding output power of
about 10 W.
Index Terms— Gallium nitride (GaN) monolithic microwave
integrated circuit (MMIC) power amplifier (PA), high-efficiency
amplifier, reactive matching (RM).
I. I NTRODUCTION
W ITH the growth in applications of the millimeter-wave
spectrum for terrestrial wireless communication, satel-
lite radio, automotive radar, electronic warfare, and instru-
mentation systems, the demand for fully integrated broadband
high-power, high-efficiency power amplifiers (PAs) is grow-
ing [1]–[4]. To meet this demand, the III–V compound semi-
conductor monolithic microwave integrated circuit (MMIC)
is the preferred choice for such PAs [5]. In order to obtain
the high-power level for the abovementioned systems, it is a
common method to combine the output power (Pout ) of several
individual MMIC PA chips [6]. However, this combination
can cause an increased loss in the synthetic network. Thus,
Manuscript received December 17, 2019; revised March 7, 2020; accepted
April 4, 2020. This work was supported in part by the National Natural
Science Foundation under Grant 61841110, in part by the Applied Basic
Research Plan of Qinghai under Grant 2017-ZJ-753, and in part by the Tianjin
University–Qinghai University for Nationalities Joint Innovation Fund under
Grant 2020XJZ-0076. (Corresponding author: Hai-Feng Wu.)
Qian Lin and Shan-Ji Chen are with the College of Physics and Electronic
Information Engineer, Qinghai University for Nationalities, Xining 810007,
China.
Hai-Feng Wu, Yu-Nan Hua, Yi-Jun Chen, and Liu-Lin Hu are
with the Chengdu Ganide Technology, Chengdu 610073, China (e-mail:
abgott@126.com).
Lin-Sheng Liu is with the College of Information Science and Technology,
Chengdu University of Technology, Chengdu 610000, China.
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2020.2993579
0018-9480 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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1
to compensate for this loss, it is generally necessary to add a
driver amplifier chip appropriately. As a result, the increased
number of amplifier chips in the system leads to a higher
production cost. Meanwhile, in order to improve the interstage
stability, it is necessary to add isolators to guarantee the
multistage amplifier cascade work properly [7], [8], which
also can make the system more complex and expensive.
In conclusion, to simplify the system structure and to reduce
the cost, the high-gain and high-power MMIC PA is extremely
desired [9]–[11].
For the implementation of high-power MMIC PA, the gal-
lium nitride (GaN) process is particularly suitable due to the
characteristics of high power, wide-band capability, high per-
formance, and high efficiency. Due to these benefits, various
high-power GaN MMIC PAs have been proposed to cover the
frequency range of 6–18 and 2–18 GHz [12]–[17]. In 2018,
a 2–19-GHz 5-W GaN stacked distributed PA is proposed
within a small chip area [10]. In order to further enhance
the power and the gain, feedback stacked amplifier driven
a stacked nonuniform distributed PA has been proposed at
IEEE IMS2019, with about 10-W Pout and 30-dB gain [18].
However, these two chips have relatively poor thermal distri-
bution for the high-power transistors under the saturated con-
ditions [10]. Comparing with the distributed PA, the classical
reactive matching (RM) PA can obtain quite a uniform thermal
distribution among the transistors, but the limitation of the
RMPA design is the fundamental bandwidth (BW) according
to the Bode–Fano theory [1]. To overcome this limitation,
a 2–18-GHz driver RMPA chip and a power RMPA chip have
been proposed at IEEE IMS2017 [9]. However, they have
relatively low power gain. Therefore, it is still a great challenge
to realize the GaN RMPA at 2–18 GHz with low cost, high
gain, and high power.
In this article, the design procedure for a 2–20-GHz GaN
RMPA with an average Pout of 10 W is described. A new
output-matching circuit is proposed in this PA to archive a
low-loss and wideband impedance transformation using the
RM technique. Meanwhile, three-stacked-FET cells have been
adopted for the final and driver stages to maintain a high-power
and high-gain performance. Occupying a small chip area of
2.9 × 2.6 mm2 without extra off-chip matching components,
this RMPA delivers a high gain of more than 25.5 dB and high
average power-added efficiency (PAE) greater than 21%. Fur-
thermore, implemented in a 0.1-μm GaN on silicon (GaN/Si)
process, the production cost of this PA has been dramatically
reduced.
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2 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 1. Two-stage PA structure and its link budget analysis.
This article is organized as follows. Section II describes
the PA structure and its link budget analysis. In Section III,
the implemented stacked-FET has been analyzed, together
with the broadband design consideration and a proposed port
impedance model (PIM). Section IV specifies the proposed
output RM network and explains the key points of design.
In Sections V, the interstage and input matching networks
are presented in detail. Finally, the implementation results are
given in Section VI.
II. PA S TRUCTURE
The initial goal of this work is to achieve an ultrawideband
PA with an average power of 40 dBm, a small-signal gain
of 25 dB, and a power gain of 18 dB. Thus, the series
stacking of multiple devices based on the GaN process is
adopted to maintain high power and high gain. Particularly,
at 18 GHz, the small-signal gain of the three-stacked-FET
is about 19 dB. Assuming a total loss of 12 dB for the
matching networks, two-stage amplification can achieve the
design goal with a margin. Thus, the PA structure and its link
budget analysis are given in Fig. 1. Meanwhile, a three-stacked
GaN transistor reaches to the maximum efficiency point when
saturated with 4–6-dB gain compression at 18 GHz. Therefore,
considering the maximum gain compression of 8 dB when
deep saturated, the two-stage PA can still obtain a power gain
of more than 18 dB.
As seen from Fig. 1, and later in this article, the maximum
efficiency of the implemented three-stacked FET is about 50%
at 18 GHz. The estimated losses of the RM output network,
interstage network, and input network are about 3, 4, and
5 dB, respectively. The total efficiency of the PA is about
22%. Meanwhile, with an input power of 21 dBm, the final
Pout is about 42 dBm. Considering a margin of 1–2 dB, due
to the inaccuracy of the transistor model and the deterioration
in measurement, Pout is still larger than 40 dBm.
In this design, the power density of the GaN transistor is
about 3.3–5.7 W/mm [19]. Therefore, in order to achieve a
Pout of 43 dBm before the output-matching network (as shown
in Fig. 1), eight-channel 3×4×100 μm transistors are adopted
in the power-stage amplifier. Meanwhile, four-channel 3 × 4 ×
60 μm transistors are chosen for the driver-stage amplifier.
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Fig. 2. Layout and schematic of 3 × 0.4 mm three-stacked-FET cell.
The driving ratio of multistage wideband PA is about 1:2,
which can ensure a good interstage matching and a broadband
performance, avoiding the complexity or the asymmetry in the
ratio of 1:4 or 1:8.
III. T RANSISTOR -S TACKING PA D ESIGN
A. Transistor-Stacking Technique
The transistor-stacking technique, as shown in Fig. 2, which
is based on a set of common-source or common-emitter
transistors both connected dc and RF in series, can be used to
combine the output voltage swings and enhance the gain, Pout ,
and the optimum load impedance, simultaneously. In addition,
the gates of the stacked transistors are connected to the
specific capacitances Cgk , which can control the gate voltage
swing and adjust the optimum load impedance between the
interconnected transistors.
Based on previous works [2]–[5], operating at frequencies
much lower than the maximum transition frequency ( f T ),
the optimum load impedance of each transistor is purely
resistive. However, the parasitic cannot be negligible, and the
optimum load impedances of stacked-FET are complex at high
frequencies. As a result, the input admittance of the kth FET
stacked (as Yin2 and Yin3 in Fig. 2) is also decided by its load
termination (Yld2 and Yld3 ), as calculated in [20]
 
sCgsk +gmk Yldk − gmk /Ak
Yink = G ink − j Bink = + · sCdsk
Ak Yldk + sCdsk
(1)
where Cdsk , Cgsk , and gmk are the drain–source capacitance,
the gate–source capacitance, and the transconductance of the
kth transistor, respectively. To get the most power from the
(k-1)th FET stacked, Yink should be equal to Yoptk−1, which
is the optimum load admittance of the kth stacked-FET
determined by the load–pull simulation [20]. Cgk and
other parameters can be defined by the following coupled
equations:
G ink = Re[Yoptk-1] (2)
Bink = −Im[Yoptk-1]. (3)
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LIN et al.: 2–20-GHz 10-W HIGH-EFFICIENCY GaN PA USING RM TECHNIQUE
Fig. 3. Load–pull contours at 20 GHz and Cgk parameters analysis. (a) Cg2
extraction method from the load–pull simulation of a single FET. (b) Cg3
extraction method from the load–pull simulation of a two-stacked-FET.
TABLE I
L OAD –P ULL S IMULATION R ESULTS FOR THE O UTPUT T RANSISTORS
W ITH A T OTAL W IDTH OF 1200 μm
Limited by the capacitance Cdsk at high frequency, there
exists no Cgk that satisfies (2) and (3) simultaneously. Cgk
can be determined using a load–pull simulation on the
(k + 1)th-FET stacked to find the optimum load admittance
that provides the most power from the entire k-FET stacked.
As shown in Fig. 3(a), when Cg2 is varying from 10 to 400 fF,
Zld1 moves following the green line in the Smith chart. When
Cg2 = 194 fF, Z ld1 = 24.8 + j ∗ 19.6 , and this impedance
can obtain the highest PAE with a relatively high Pout for
the transistor M1 at 20 GHz. Similarly, as shown in Fig. 3(b),
when Cg3 = 104 fF, Z ld2 = 34+ j ∗42 , and the highest PAE
for the two-stacked-FET can be obtained by this impedance.
B. Broadband Design Consideration
The load–pull simulation result of the three-stacked-FET
for the power stage of this PA is given in Table I. These sets
of impedances are chosen to be approaching the maximum
PAE points while maintaining relatively high power. It is also
observed that the optimal load impedance of the device is not
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3
Fig. 4. Load–pull contours for Pout and PAE from 2 to 20 GHz and ideal
optimal load impedance.
constant for the whole frequency. Pout is greater than 34 dBm,
and PAE is greater than 50% at 2–20 GHz. Fig. 4 also gives
the load–pull contours for Pout and PAE at 2 and 20 GHz,
together with the ideal optimal load impedance.
As deduced from Table I, the gain of the two-stage amplifier
with the ideal impedance match at 2 GHz is about 12–16 dB
higher than that at 20 GHz. It is quite complex to apply
the classical negative feedback technology to improve this
gain flatness in the eight- or four-channel three-stacked FETs.
To solve this issue, the impedance mismatches at certain low
frequencies are deliberately implemented as a sacrifice to
reduce the gain. Furthermore, a passive equalization circuit is
adopted before the input matching circuit, which is helpful
to avoid the significant efficiency deterioration at the low
frequency.
C. Port Impedance Model
The broadband matching network is used to transform
the load impedance to the optimum impedances. In general,
to meet the demands, circuit parameters of the PA will be
adjusted and optimized through the harmonic-balance (HB)
simulations. However, there are 36 power transistors in this
four-channel three-stacked-FET driving eight-channel three-
stacked-FET amplifier, and it is extremely difficult to give
regarding computational speed and convergence stability in the
parameters optimization using HB simulations. Thus, a passive
approximation method is developed, which can greatly shorten
the simulation time to find the circuit parameters. More
detailed steps of this method are described as follows.
1) As shown in Fig. 5(a), a PIM with a load port (P1 )
connected an ideal n-level LC network is built to model
the frequency response of the optimal load impedance
Z opt in Table I at 2–20 GHz.
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4 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 5. Passive approximate method for this RMPA design. (a) PIM.
(b) Modeling results of the frequency response of the optimal load impedance
Z opt1 of the power stage at 2−20 GHz in Table I. (c) Modeling results of the
frequency response of the optimal load impedance Z opt2 of the driver stage
at 2−20 GHz. (d) Schematic of the impedance matching network using the
modeled PIM.
2) To guarantee that the frequency response characteristics
can fit the optimal load impedance for 2–20 GHz, PIM
can be adjusted by software, as shown in Fig. 5(b) and
(c).
3) Based on the modeled PIMs, the impedance matching
network is constructed. Since the ideal n-level LC net-
work in PIM is lossless, as shown in Fig. 5(d), if 1 ≈ 0,
then 2 ≈ 0. Thus, the insertion loss (IR) and return loss
from port P1 to port P2 can be employed to design the
output network through S-parameter simulations. Mean-
while, certain appropriate adjustment and optimization
can be made if needed.
With the increasing number of stacked transistors, the sim-
ulation speed is slower and less convergent. As a result,
this passive approximate method is suitable for the complex
amplifier. Unlike using the S-parameter data file (SnP), this
PIM is continuous at any frequency. As a result, the problem
of nonconvergence at certain individual frequency points can
be avoided. Moreover, it is inconvenient to use the SnP file as
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Fig. 6. Comparison of two types of RF chokes. (a) Schematic of one
microstrip line. (b) Schematic of dual-inductor. (c) IR (S21 ) and return loss
(S11 ), Z 0 = Z choke , are used for simulation.
a term to simulate the return loss and the IR. The simulation
results show that it needs about 2 min to do the HB simulation
at 2–20 GHz with a step of 1 GHz for this RMPA, while it
takes only a few seconds to do the equivalent S-parameter
simulation using the passive approximate method.
IV. O UTPUT-M ATCHING N ETWORK
There are four key points for the output-matching network
design in the 2–20-GHz ultrawideband applications.
1) The output-matching network must convert the 50 
to the optimal impedances required for output ports
of the stacked transistors at 2–20 GHz. Meanwhile,
the introduced IR must be minimized.
2) It is important to take the broadband characteristic
equalization into account for the output-matching net-
work design. Due to the truth that power and efficiency
at 20 GHz are usually the lowest, thus, the IR and
impedance matching at 20 GHz have to be guaranteed
at the cost of sacrificing the low-frequency performance.
3) The oscillation or phase inconsistency can be avoided
by keeping the suitable broadband gain flatness.
4) It is wise to integrate the biasing network and the bypass
network into the chip with the consideration of the
current through-flow capability.
In general, the RF grounding microstrip lines or spiral
inductors are used in the on-chip RF choke for the dc
supply. Especially, for the RMPA, it is common to use the
grounding microstrip line [9], which not only can realize
the dc feed but also can achieve the impedance matching.
However, the traditional microstrip line is unsuitable in the
10-W 2–20-GHz RMPA. This is because the width W of the
microstrip line needs to be expanded for high current-flow
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LIN et al.: 2–20-GHz 10-W HIGH-EFFICIENCY GaN PA USING RM TECHNIQUE 5

Fig. 7. Equivalent schematic of the output-matching network.

Fig. 8. Steps to transform the 50- load to Z L2opt at 2–20 GHz.

capacity. However, the parasitic capacitance Clin will increase

at the same time. Meanwhile, the length L of the microstrip
line should be long enough to meet the matching demand at
2 GHz. Thus, when W and L increase simultaneously, it will
cut down the resonant frequency, which leads to a resonance
in the 2–20-GHz frequency range. For example, in order to
satisfy the demand for high power and broadband, W and L
of the microstrip line are at least 60 and 2200 μm, respectively.
Using a set of bypass capacitances, as shown in Fig. 6(a), the
self-resonance frequency of the microstrip line is around 18
GHz, as shown in Fig. 6(c), which may greatly deteriorate
the IR. To solve this problem, a dual-inductor is adopted,
as shown in Fig. 6(b). The total width of the dual-inductor
is larger than 60 μm, and its equivalent inductance at 2 GHz
is large enough for the impedance matching. The resonant
frequency is higher than 22 GHz, which ensures low IRs at
2 and 20 GHz, simultaneously, as shown in Fig. 6(c). Here,
the terminal impedances are expressed as Z choke and Z choke ∗,
respectively, as shown in Fig. 7. Moreover, unlike the looser
microstrip line, this structure can greatly save the chip area.
Using this choke, the equivalent circuit topology of the
output-matching network is given in Fig. 7. The multistage
LC structure is utilized in the RMPA after the RF choke to
progressively increase the impedance level from Z ∗ L2,opt
toward 50 . Meanwhile, the gain flatness is improved based
on the LC structure, but the IR increases with the increasing
length of matching branches. Moreover, it will enhance the
complexity of the output network. Thus, in order to give
Fig. 9. Half layout of the output-matching network.
priority to the efficiency and reduce the output loss, a four-
stage LC is used, as shown in Fig. 7. Then, the component
values can be identified using the circuit optimization tools.
Based on the PIM, circuit optimization is easy and fast to be V. I NTERSTAGE AND I NPUT M ATCHING N ETWORK
accomplished. Thus, the predefined impedance matching goals A. Stabilization Consideration
can be satisfied. The equivalent circuit parameters are also
shown in Fig. 7. Meanwhile, the detailed steps for impedance The stability analysis is a critical step in this PA design. It is
transformation are shown in Fig. 8. worth mentioning that the most common method is to break
To verify the design, the output network is substituted the amplifier stages into two-port networks and compute the
into the PA schematic and then converted to the layout. The stability factor k for each stage [21]. If a potential problem is
output return loss and the IR are further optimized using the found, the stage must either be rendered unconditionally stable
S-parameter and HB simulation (if necessary). The half layout or the designer must show that the terminating impedances
of the output network is shown in Fig. 9. After comparing the will not allow the circuit to oscillate. Forcing the stage
electromagnetic (EM) simulation result with the schematic (as to be unconditionally stable normally involves introducing
shown in Fig. 10), the EM simulated IR is about 0.8 and 1 dB additional loss into the circuit, which usually sacrifices the
lower than that of the schematic at 2 and 20 GHz, respectively. performance.

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6 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 10. Output return loss and IR of the output-matching network.
Fig. 11. Oscillation loops for the elementary modes in the case of a
multicombined PA stage. (a) Mode1. (b) Mode2. (c) Mode3.
Fig. 12. Four-port network: S-probe pair for stability criterion.
Especially, for this RMPA, the oscillation problem is
extremely complex. The possible oscillation response loop is
shown in Fig. 11. Mode 1 is the working situation without
any oscillation. Once the circuit starts to oscillate, each odd
mode is associated with an equivalent signal loop (see Fig. 11).
Mode 2 is associated with one inner loop, while the mode
3 is associated with an outer loop involving transistors in
pairs. Therefore, the classical method is extremely tedious.
However, using an approximate method based on multiple
four-port S-probe pair is implemented in this design, as shown
in Fig. 12.
Using the S-probe pair, which is compatible with the
commercial microwave circuit simulations, the stability analy-
sis can be achieved. When the stability indices satisfy the
conditions (4) and (5), the network is unconditional stable
Stabindexi1 = real(Zil × Zi2 ) < 1
Stabindexi2 = real(Zi3 × Zi4 ) < 1
where i = 1, 2, . . . k (k = 36 for this design). Zij is the
reflection coefficients looking both directions at the input and
output planes of the i th transistor. These functions determine
whether the conditions for oscillation are satisfied at any
frequency. Thus, 36 S-probe pairs can be applied to analyze
and optimize the interstability for 36 transistors simultaneously
in the S-parameter simulation of the RMPA.
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Fig. 13. Equivalent schematic of the interstage matching network.
B. Interstage Matching
The interstage matching network design for the 2–20-GHz
applications must consider the following points.
1) The impedance transformation from the output
impedance of the driver stage to the input impedance
can cover the ultrawideband of 2–20 GHz. Meanwhile,
the introduced IR must be minimized.
2) Every two-stage PA is driven by the driver stage ampli-
fier. Therefore, the driving capability must be strong
enough and keep the phases consistent.
3) The drain biasing design for the interstage network
is also important for the driver stage. The current
through-flow capability of the microstrip line must meet
the design requirements. Meanwhile, it is significant to
satisfy the broadband matching.
4) To guarantee that the interstage stability between the
driver stage and the power stage is also of great
importance.
To meet the abovementioned interests, a matching structure
with a two-stage high-pass filter is chosen, as shown in Fig. 13.
It can be observed that a two-stage grounding inductor and LC
matching are employed here. The half layout of the interstage
matching circuit is given in Fig. 14.
As shown in Table I, the driving power is much higher at
20 GHz than that at 2 GHz. Thus, the IR has to be designed
as a curve with a positive slope versus frequency. At this
point, the efficiency at 20 GHz is particularly critical, and
the optimal impedance point at the frequency of 20 GHz must
be considered as a high-weight factor in this design. At the
same time, the interstage circuit is a symmetrical and concise
structure with a ratio of 4:8 and a consistent phase.
C. Input Matching
There are also four significant aspects of the input matching
(4) design of this RMPA.
(5) 1) The IR should be minimized for the input impedance
matching from 2 to 20 GHz to 50 .
2) The power division of equal power and equal phase is
crucial.
3) Stability must be guaranteed unconditionally.
4) The gain flatness has to be improved.
The equivalent schematic and layout of the input match-
ing circuit are shown in Figs. 15 and 16, respectively. For
stabilization, a revised RCL network (as the resistance R4 ,
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LIN et al.: 2–20-GHz 10-W HIGH-EFFICIENCY GaN PA USING RM TECHNIQUE
Fig. 14. Half layout of the interstage matching network.
Fig. 15. Equivalent schematic of the input matching network.
the capacitor C10 , and the microstrip line TL19 in Fig. 15)
is placed at the input stage. Besides, it also improves the
broadband input matching and lowers the intrinsic gain of
the transistor at low frequency where the transistor is prone
to oscillation. Thus, it compensates for the gain roll-off and
broadens the BW. Another RCL network (as the resistances
R5 and R6 , the bypass capacitor, and the microstrip line TL21
in Fig. 15) is placed in the dc bias path, which is a benefit for
preventing thermal runaway by limiting the gate current.
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7
Fig. 16. Layout of the equalizer and the input matching network.
Fig. 17. IR and return loss of the equalizer.
In order to achieve the gain suppression at low frequency,
a broadband equalizer is implemented in Fig. 15. The input
terminal inductance L 5 is connected to the upper plate metal
MET2 of capacitor C8 . Meanwhile, the inductance L 6 is
connected to the lower metal plate MET1 of capacitor C8 ,
as shown in Fig. 16. This layout can greatly save the area of
the equalizer and make full use of the layout of the grounding
hole. The simulation result of the equalizer is shown in Fig. 17.
With a return loss better than −15 dB, the gain at 2 GHz
is suppressed about 2.5 dB, while the gain at 20 GHz only
deteriorates about 0.5 dB. To improve the total gain flatness
of the RMPA, the input and interstage matching network
are finally designed with a total IR about 17 dB at 2 GHz,
as shown in Fig. 18.
VI. I MPLEMENTATION R ESULTS
This GaN RMPA is implemented in a 0.1-μm GaN on
Si process. Fig. 19 shows the photograph of the fabricated
chip with an area of 2.9 × 2.6 mm2 . The die is mounted
on the top of a copper heat sink in a test fixture for probe
launchers. RF input and output pads of the PA are bonded
to 50 microstrip lines on the RF board using two 18-μm-
diameter gold wires, as shown in Fig. 20. The bond wires are
modeled as a combination of two series inductors (80 pH)
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8 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 18. IR of the interstage and input matching networks.

Fig. 21. S-parameters of the RMPA.

Fig. 19. Die photograph of the GaN RMPA (2.9 × 2.6 mm2 ).

Fig. 22. Pout and PAE of the RMPA with the 21-dBm input power.

Fig. 20. Photograph of the test fixture for the GaN PA.

and a grounded capacitor (30 fF). Considering their impacts,

the bond wires should be used as short as possible. In order
to verify this design, this fabricated GaN PA is biased at the
VDS of 28 V and VGS of −1.2 V, resulting in 1.6 A of total
quiescent bias current.
The measured and simulated S-parameters are shown in
Fig. 21. It can be seen that more than 25.5-dB gain is achieved,
with S11 better than -10 dB over the 2–20-GHz BW. Moreover,
the measured and simulated Pout with corresponding PAE and
power gain are shown in Figs. 22 and 23. It can be observed
that the BW is partially larger comparing with the simulation
results due to the improvement of S22 in measurement. The
measurement results, nevertheless, indicate an average Pout of
Fig. 23. Power gain of the RMPA with the 21-dBm input power.
10.3 W from 2 to 20 GHz with a peak of 41.6 dBm (14.5 W) at
13 GHz. The power gain is about 18–20.5 dB for the frequency
range of 2–20 GHz. The associated average PAE is about 21%
with a peak of 29% at 6 GHz. Fig. 24 shows the measured
Pout and PAE with input power at a number of frequencies.
It is shown that the curves are well behaved, and there is no
evidence of odd-mode or parametric oscillations during the
tests.

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LIN et al.: 2–20-GHz 10-W HIGH-EFFICIENCY GaN PA USING RM TECHNIQUE 9

TABLE II
C OMPARISON W ITH L ATEST B ROADBAND G A N PA

Fig. 24. Measured Pout and PAE with input power at 2, 5, 8, 11, 14, 17,
and 20 GHz.
Fig. 25. IR image under Vds = 28 V and Ids = 1.6 A quiescent biasing
condition.

Noting that the infrared (IR) imaging can be used to

determine the maximum temperature (Tmax ) on the die under
different operating conditions. Thus, in order to learn the tem-
perature distribution for this PA, the die surface temperature
is observed using the IR imaging technique. The scanned
temperature image is shown in Fig. 25 under the base plate
temperature of 25 ◦ C, without RF excitation conditions of
Vds = 28 V and Ids = 1.6 A. The highest hot spot is 145 ◦ C,
and the thermal resistance of about θjc = 2.7 ◦ C/W is obtained.
As a result, this RMPA shows large operational temperature
margins from the maximum operations junction temperature
of 225 ◦ C.
In order to evaluate this RMPA, the performance compari-
son with the latest GaN wideband PAs is presented in Table II.
A figure-of-merit (FoM) is defined by the equation below
Table II. While BW/ fc is the fractional BW, Pout−watt(min)
is the minimum Pout in the form of Watt, PAE(min) is the
minimum PAE, S21(min) is the minimum of small-signal gain,
and the Size is the chip area. With the help of the FoM,
the proposed RMPA exhibits quite a superior performance
including small size, high gain, and wide BW in the GaN
MMIC PAs.
VII. C ONCLUSION
The analysis, design, and implementation of a wideband
10-W MMIC PA are presented in this article. Using the RM
technique, the low-loss and wideband impedance transforma-
tion networks across 2–20 GHz have been realized. Utilizing
a low-cost 0.1-μm GaN on Si technology, the RMPA achieves
a small-signal gain of greater than 25.5 dB and average
output power of 40.1 dBm over the 2–20-GHz band, with
an associated peak PAE of 29% at 13 GHz. The perfor-
mance of the RMPA validates the effectiveness of this design.

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10 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

The broadband gain response and the corresponding output
power are the highest among the reported wideband GaN
MMIC RMPAs.
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Qian Lin received the B.S. degree in electronic
information science and technology from Qinghai
Nationalities University, Xining, China, in 2004, the
M.S. degree in electronic information technology
from Qinghai Normal University, Xining, in 2010,
and the Ph.D. degree in circuits and systems from
Tianjin University, Tianjin, China, in 2017.
She is currently a Professor with Qinghai Nation-
alities University. Her research interests include the
RF circuit design, 3-D modeling, testing, simula-
tion of circuit reliability, and electronic technology
applications.
Hai-Feng Wu received the B.E. and M.E. degrees
in electronics from the University of Electronic
Science and Technology of China, Chengdu, China,
in 2007 and 2010, respectively, and the Ph.D. degree
in microelectronics and solid-state electronics with
Tianjin University, Tianjin, China, in 2016.
From 2010 to 2011, he was an Engineer with
Accelicon Technologies, Inc., Beijing, China, where
he was involved with the transistor model building.
Since 2016, he has been an Engineer with Chengdu
Ganide Technology, Chengdu, where he is involved
with the RFIC design. His research interests are RF transistors modeling and
the power amplifier design in MMIC.
Yu-Nan Hua received the B.E. degree in electronics
from the Guilin University of Electronic Technology,
Guilin, China, in 2008, and the M.E. degree from
Southeast University, Nanjing, China, in 2011.
Since 2011, she has been an Engineer with
Chengdu Ganide Technology, Chengdu, China. Her
research interest is the RFIC design.

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LIN et al.: 2–20-GHz 10-W HIGH-EFFICIENCY GaN PA USING RM TECHNIQUE 11

Yi-Jun Chen received the B.E. and M.E. degrees Lin-Sheng Liu received the B.S. degree in elec-
in electronics from Sichuan University, Chengdu, tronic engineering and the Ph.D. degree in circuits
China, in 2006 and 2009, respectively. and systems from the University of Electronic Sci-
Since 2006, he has been a Senior Engineer with ence and Technology of China, Chengdu, China,
Chengdu Ganide Technology, Chengdu. His research in 2005 and 2010, respectively.
interests include RFIC and SiP design. Since 2018, he has been a Professor with the
College of Information Science and Technology,
Chengdu University of Technology, Chengdu. His
research interests include nonlinear device char-
acterizations/modeling, RFIC design, and wireless
communications.

Liu-Lin Hu received the B.S. degree in applied

physics from the Changchun University of Science
and Technology, Changchun, China, in 2004, and the
M.E. degree from the Harbin Institute of Technol-
ogy, Harbin, China, in 2006.
Since 2006, he has been a Senior Engineer with
Chengdu Ganide Technology, Chengdu, China. His
research interests include RFIC and MMIC design.
Shan-Ji Chen, photograph and biography not available at the time of
publication.

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