35 dBm, 35 GHz Power Amplifier MMICs using 6-inch GaAs

pHEMT Commercial Technology

S.J. Mahon, A. Dadello, A.P. Fattorini, A. Bessemoulin, and J.T. Harvey
Mimix Asia
Level 13, 80 Mount Street, North Sydney, NSW 2060, Australia
email: smahon@mimixbroadband.com

Abstract — A 3.5 watt, 35 GHz power amplifier MMIC

has been developed. The amplifier exhibits high
performance at low processing cost, through the use of a
commercially available 6-inch, 0.15-µm pHEMT process
with 100 µm thick substrate. The single-ended four stage
amplifier MMIC has 22 dB of gain at 35 GHz, 3.5 watts
saturated output power (35.5 dBm), and power added
efficiency of more than 25%, within a chip size of
12.75 mm2. In terms of power density, this is
740 mW/mm, which is to the authors’ knowledge the best
reported for fully matched GaAs pHEMT MMICs on
100-µm substrates at millimetre-wave frequencies.

Index Terms — MMIC power amplifiers.

I. INTRODUCTION
There is an ongoing demand for cost effective high
power amplifier (HPA) MMICs at Ku-, Ka- and Q-
bands [1]-[6]. The power amplifier MMIC reported in
this paper was designed to meet this challenge. A
standard commercially available 6-inch GaAs pHEMT
technology with 100-µm substrate was used in
preference to thinner substrates. This not only reduces
cost; but it also provides higher wafer robustness,
easier die handling compared to thinner chips and
higher overall yield. Reasonable die area and broad
bandwidth were achieved with conventional
technology by utilising novel matching network
topologies incorporating lumped elements, designed
with extensive use of electromagnetic simulations.
Fig. 1. Output transistor thermal image. Peak channel
temperature is 148 ºC for 80 ºC stage temperature and
nominal operating power level and bias.
Infra-red thermal imaging was used to measure the
peak channel temperature of the different transistor
layouts as a function of bias and RF drive. The thermal
resistance was found to vary by 15% between test
pHEMTs with the same gate width and transistor area.
Fig. 1 shows the channel temperature of one of these
layouts. This technique was also used to predict the
amplifier’s reliability, which exceeds one million hours
MTTF CW (continuous wave) operation at 75 °C
backplate.

II. MMIC DESIGN AND MEASURED PERFORMANCE

The MMIC was fabricated in the WIN
Semiconductor (Taiwan) standard 0.15-µm power
pHEMT process on 6-inch wafers with 100 µm
thickness [7]. Rigorous design and layout methods
were used in the optimisation of stability, gain, power
transfer and lifetime. Layout parameters such as gate
width, gate-to-gate spacing and the number of gate
fingers between source vias influence the RF power
available from a transistor, its RF stability, channel
temperature (hence reliability and lifetime) and the size
(cost) of the resulting amplifier. Load-pull
measurements of test pHEMTs with on-wafer pre- and
post-device matching quantify the effect of these
layout parameters on the available RF power which
varies from 600 to 800 mW/mm while keeping gate
currents within a conservative range for reliable Fig. 2. Photograph of the 3.5 watt amplifier MMIC (3.75
operation [8]. mm × 3.40 mm = 12.75 mm2).

978-1-4244-1780-3/08/$25.00 © 2008 IEEE 855

 The design of the output stage transistor is a trade-
off between available RF power, thermal behaviour,
physical size and specified output match. The load-pull
and thermal imaging analysis is required for
optimisation of the output stage and combining
manifold. For the input and interstage designs the load-
pull data was augmented by a new non-linear device
model [9] and extraction methodology [10] to ensure
optimal trade off between power match for each stage
and source impedance for the following stage. This
new model and careful EM simulations ensure phase
and amplitude balance between the amplifier’s inner
and outer devices. RF ports and bias feeds were
designed for ESD robustness.
The output of the four-stage, 3.5-watt PA MMIC
(Fig. 2) consists of eight 600-µm transistors with
optimised device geometry, driven by three stages with
a 1:2:4:8 periphery ratio, in a chip size of 12.75 mm2.
The amplifier was tested in CW mode at reduced-bias
for small signal S-parameters on-wafer (without any
heat sink) yielding a 20 dB gain and input and output
matches of 10 and 8 dB, respectively.
For power measurements the device was mounted on
a copper block and a pulsed measurement was made
with an 8 µs pulse and 500 Hz repetition rate. A
voltage sense pad on the MMIC was used to maintain
the correct drain voltage in the presence of IR drops in
the probes and associated cables. The power data was
taken from an average value over a window from 3 to 5
µs and the drain current was measured in the middle of
that window at 4 µs. Fig. 3 shows the pulsed gain
exceeding 20 dB (typically 22 dB) over the 33 to 37
GHz band.
24
22
Gain (dBm)
20
18
16
14
33 34 35 36 37
Frequency (GHz)
Fig. 3. Measured pulsed gain of the 35 GHz amplifier
MMIC on a copper block.
The effect of bond wires and off-MMIC structures
on available output power has also been explored. The
RF out (and input) pads on the MMIC are designed to
offer the possibility of using a low-pass filter (created
by the bondpad capacitance, bondwire inductance and
the capacitance of the off-MMIC matching structure
for the bondwires) to minimise the bondwire insertion
loss. We used an off-MMIC structure also fabricated
on GaAs because of the convenience and precision
offered by using on-GaAs TRL calibration. Fig. 4(a)
978-1-4244-1780-3/08/$25.00 © 2008 IEEE
shows the on-MMIC calibration plane and Fig. 4(b)
shows a pair of bondwires connecting to an off-MMIC
GaAs structure where the second set of measurements
are referenced. The die spacing used here is
approximately 75 µm. This is smaller than that used in
some applications but it is countered by the use of ball
bonds which give a longer bond wire than the wedge
bonds that would be used in high performance
applications.
(a) (b)
Fig. 4. Calibrated reference plane for pulsed power
measurements: (a) on-MMIC inside the RF output pads; and
(b) off-MMIC beyond the bond wires on an external
structure.
36
34
Pout
PAE (%) and Pout (dBm)
32
30
28
26 PAE
24
22
20
34 34.5 35 35.5 36
Frequency (GHz)
Fig. 5. Measured pulsed output power of the amplifier at
Pin=+16 dBm inside the MMIC pad (solid) and outside the
output bond wires (dashed) as per Fig. 4.
Fig. 5 shows the pulsed output power and power-
added efficiency (PAE) as function of the frequency at
an input power level of 16 dBm for measurement plane
on and off the MMIC (i.e. Fig. 4(a) and 4(b)). The
values, at 35 GHz, of 35.5 dBm and 25% PAE show
that the output bondwire loses have been reduced to 0.3
dB with similar losses at adjacent frequencies. Fig. 6
shows the pulsed output power, gain and PAE as
function of the input power at 35 GHz. The measured
output power level of 35.5 dBm corresponds to a
power density of 740 mW/mm in the final stage. This
demonstrates effective use of the available device
power seen in the transistor load-pull measurements.
A pulsed measurement was made with the amplifier
connected to a load-pull tuner to check the output
power as a function of the presented impedance. In
Fig. 7, the well centred contours of output power and
PAE after the matched bond wires (i.e. Fig. 4(b)),
indicate that optimum performance has been achieved.
856
 Thickness Lg Freq. Gain (dB) / Psat Power density PAE Die area
Ref. Technology
(um) (nm) (GHz) No. stages (dBm) (mW/mm) (%) (mm2)
[1] GaAs pHEMT 50 250 27-31 24 / 3 35.3 268 25 12.88
[2] GaAs pHEMT 100 250 27-32 20 / 3 33.1 395 25 6.16
[11] GaAs pHEMT 50 200 28-31 22 / 3 36.3 500 28 12.4
[12] GaAs pHEMT 50 200 42-46 15 / 3 36 521 20 15.9
[13] AlGaN/GaN HEMT 100 180 26-36 12 / 2 36 3200 23 NA
[14] GaAs pHEMT 635 150 35 9/ 2 30.1 260 15 7.25
This work GaAs pHEMT 100 150 34-36 22 / 3 35.5 740 25 12.75

Table 1. Benchmark of Ka-band HPAs using GaAs and GaN HEMTs.

36
PAE (%), Gain (dB) & Pout (dBm)

32
Pout
28
24
Gain
20 III. CONCLUSION
16
12 The performance of a 3.5-watt, 35-GHz power
8 PAE amplifier MMIC has been presented. The circuit
4 achieves a pulsed output power of 35.5 dBm at 25%
0 PAE with a gain of 22 dB. The output power represents
2 4 6 8 10 12 14 16 18 a power density of 740 mW/mm. To the authors’
Input Power (dBm) knowledge this is the best reported power density for
fully matched GaAs pHEMT MMICs on 100-µm
Fig. 6. Measured pulsed output power, gain and PAE
versus input power at 35 GHz measured to the reference substrates at millimetre-wave frequencies.
plane in Fig. 4(a). Load-pull measurements demonstrate that the output
match has been successfully optimised over a useful
bandwidth and that the bondwire transition losses have
p1: PAE =Swp
18 Max been reduced to about 0.3 dB through the use of
1.0
0.8

p2: PAE = 22 149 compensating structures. Infra-red imaging has been

6
0.

used to optimise the transistor layout. The predicted

2.

p3: PAE = 26
lifetime exceeds 1 million hours at 75° C backplate
4
0.
0
p4: Pout =3. 33 dBm
.0 temperature under CW operation.
p5: Pout = 34
4
dBm
p2 p5
0
2 5.
p6: Pout = 35 dBm
0.

p6 10.0
ACKNOWLEDGEMENT
p3
10.0
0.2

0.4

0.6

0.8

1.0

2.0

3.0

4.0
5.0

The authors would like to acknowledge the

0

p4 contribution of M.G. McCulloch, R.G. Mould and S.

p1 -10.0
Hwang for assistance with measurements and
-0.
2
-5.
0 assembly, A.E. Parker (Macquarie University) and P.V.
-4
.0
Vun for associated non-linear modelling supported by
.4
-3
.0
the Australian Research Council.
-0
.0
-2
.6

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-0

Swp Min
-0.8

-1.0

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