Proceedings of the 3rd European Microwave Integrated Circuits Conference

GaN MMIC based T/R-Module Front-End for

X-Band Applications
P. Schuh∗ , H. Sledzik∗ , R. Reber∗ , A. Fleckenstein∗, R. Leberer∗ , M. Oppermann∗,
R. Quay† , F. van Raay† , M. Seelmann-Eggebert†, R. Kiefer† and M. Mikulla†
∗ EADS Deutschland GmbH, Defence Electronics, Wörthstr. 85, 89077 Ulm, Germany
† Fraunhofer Institute of Applied Solid-State Physics, Tullastr. 72, 79108 Freiburg, Germany
patrick.schuh@ieee.org

Abstract— Amplifiers for a next generation of T/R-modules

in future active array antennas are realized as monolithically
integrated circuits (MMIC) on the bases of novel AlGaN/GaN
HEMT structures. Both, low noise and power amplifiers are
designed for X-band frequencies.
The MMICs are designed, simulated and fabricated using
a novel via-hole microstrip technology. Output power levels of
6.8 W (38 dBm) for the driver amplifier (DA) and 20 W (43 dBm)
for the high power amplifier (HPA) are measured. The measured
noise figure of the low noise amplifier (LNA) is in the range of
1.5 dB.
A T/R-module front-end with mounted GaN MMICs is de- Fig. 1. Photo of a GaN DA MMIC chip. Chip size : 3 mm ×2 mm
signed based on a multi-layer LTCC technology.

I. I NTRODUCTION In this paper the design and the achieved performance of

Active electronically scanned array (AESA) radars are in-
creasingly being favoured over conventional mechanically-
scanned systems. The achievable radar range of such an AESA
radar is mainly determined by the output power and the
noise figure of the antenna. T/R-modules are key elements in
active phased array antennas for radar and electronic warfare
applications [1]. Inside these T/R-modules two main building
blocks are the amplifier chain in the transmit path and the low
noise amplifier in the receive path.
In most of today’s T/R-Modules GaAs MMIC amplifiers are
used with typical output power levels in the range of 5 W to
10 W [2], [3]. Higher output power levels, broader bandwidth,
increased power added efficiency (PAE) values, and higher
operating voltages are advantages for performance improve-
ment to meet future requirements. For these applications the
use of amplifiers based on AlGaN/GaN is a very promising
approach [4]–[7]. Another important parameter is the PAE of
the amplifier. Due to the higher breakdown voltage of the GaN
device compared to a GaAs device, the supply voltage can be
significantly increased. This leads to an additional increase
in efficiency on system level, because of lower losses in the
power supply.
Besides the noise figure performance also the robustness
against high input power overdrive is a key issue for the receive
path in a T/R-module. The AlGaN/GaN technology with its
high breakdown voltage is very good suited for robust low
noise applications [8].
To satisfy these future needs, a T/R-module front-end
composed of novel GaN MMICs and multi-layer packaging
technology [9] is designed.
single GaN MMIC amplifiers and of a whole T/R-module
front-end based on these GaN MMICs are presented.
The MMIC and front-end design, simulation and measure-
ments are done at EADS Defense Electronics, Ulm. The wafer
and MMIC fabrication is done at the Fraunhofer Institute of
Applied Solid-State Physics, Freiburg.
II. G A N MMIC T ECHNOLOGY AND M ODELING
The AlGaN/GaN HEMT MMIC technology is based on
multi-wafer growth of single heterojunction devices on 3-inch
s.i. SiC substrates by MOCVD. The 3-inch HEMT technology
uses electron-beam-defined gates with 0.25 µm gate-length
including fieldplates for high-power operation.
The two-terminal breakdown voltages of the power HEMTs
are BV > 100 V. Typical output power densities are beyond
W
5 mm at 10 GHz with an associated drain efficiency η > 50%
at VDS = 28 V for high efficiency operation. For low-noise
operation, the AlGaN/GaN HEMTs yield a minimum noise
figure of NF < 0.8 dB at 10 GHz at VDS = 10 V.
After the frontside processing the full 3-inch SiC wafer is
thinned to 100 µm thickness and a via-hole backside process
is applied.
For the design a library of passive microstrip components is
available, including all technology specific elements like MIM
capacitors, resistors, and inductances. The large-signal GaN
HEMT modeling is based on an in-house two-dimensional
voltage-lag model to appropriately describe thermal effects and
low-frequency dispersion, and their impact on gain and PAE
[10].

978-2-87487-007-1 © 2008 EuMA 274 October 2008, Amsterdam, The Netherlands

 40
Psat
P1dB

38
Output power [dBm]

36

34

32

Fig. 3. Photo of a GaN HPA MMIC chip. Chip size : 4 mm ×3 mm

30
8 9 10 11 12 13 14
Frequency [GHz] 40 46
PAE
Gain
Fig. 2. Measured output power versus frequency of the GaN MMIC DA at 35 Output Power 43
1 dB gain compression and at saturation with VDS = 30V and VGS = −4.9V .
30 40

Output power [dBm]

Gain [dB] PAE [%]
25 37
III. D RIVER A MPLIFIER MMIC
The MMIC driver amplifier is designed as a two stage 20 34

amplifier with one transistor 8 × 60 µm gate-finger width in

15 31
the first stage and one transistor 8 × 125 µm gate-finger width
in the second stage (see Fig. 1). The amplifier is designed for 10 28
50 Ω impedance at the input and output port and for operation
in linear mode, not using the whole available output power of 5 25

the transistor. One design objective was to provide enough

input power for two HPAs in parallel configuration in the
frequency band from 8 GHz to 12 GHz. Although this amplifier
will be used for operation in linear mode, the output matching
is designed using harmonic balance simulation.
The maximum measured output power is higher than
38 dBm while operating in saturation mode with up to 5 dB
gain compression. This output power leads to a power density
of 7.4 mmW
at transistor level. The achieved output power is
sufficient for driving one or two high power amplifiers in the
frequency range between 8.5 GHz and 14 GHz (Fig. 2), while
operating the driver amplifier below the 1 dB compression
point.
IV. H IGH P OWER A MPLIFIER MMIC
The MMIC high power amplifier is designed as a two stage
amplifier based on 4 transistors with 8 × 125 µm gate-finger
width in the second stage and 2 transistors with the same
size in the first stage (see Fig. 3). The amplifier is designed
for 50 Ω impedance at the input and output port. The output
combiner is optimized for maximum output power in the
frequency range from 8.5 GHz to 11 GHz. Previous intensive
load-pull simulations have been performed to find the optimum
load impedance for maximum output power.
For electrical stabilization of the second stage RC-networks
close to all transistor inputs are used. Odd mode stability
analysis has been performed for the parallel transistor struc-
ture. The first stage transistors are stabilized by the gate
bias circuits. The interstage network and the output combiner
0
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
Input power [dBm]
Fig. 4. Measured power performance of the GaN MMIC HPA at 11 GHz
with VDS = 30V and VGS = −5V . Pmax = 43 dBm PAEmax = 31%
are optimized by electromagnetic simulations of distributed
elements. An improved PAE performance is obtained by
application of second harmonic short-networks at all gates of
the second stage transistors.
The output power, gain and PAE measurement results in
pulsed mode are shown in Fig. 4. The maximum measured
output power is 20W, when biased for class-AB operation.
This output power leads to a power density of 5.7 mm W
at
transistor level. In this case the small signal gain is about
18 dB and the associated PAE value is 31%. The small signal
gain is higher than 15 dB over the whole frequency range
from 8.5 GHz to 11 GHz (see Fig. 5). More then 14 W output
power is measured over a frequency range from 8.75 GHz to
11.5 GHz.
V. L OW NOISE AMPLIFIER MMIC
For the designed MMIC low noise amplifier the same
transistor size of 8 × 30 µm is used for the first and second
stage (see Fig. 6). For this first iteration design the transistor
layout wasn’t optimized for low noise operation. It is similar
to the power transistor layout. The transistor size of the first
stage is a tradeoff between low noise performance and large

275
 50
Psat
Gain
45

40
Gain [dB]

35
Output power [dBm]

30

25

20 Fig. 6. Photo of a GaN LNA MMIC chip. Chip size : 3 mm ×2 mm

15
18 2
Gain
NF
10
8.5 9 9.5 10 10.5 11 11.5
Frequency [GHz] 16 1.9

Fig. 5. Measured saturated output power and small signal gain versus 14 1.8
frequency of the GaN MMIC HPA. Bias Point: VDS = 30V and VGS = −5.0V

Noise Figure [dB]

Gain [dB]
12 1.7

signal robustness.
To allow a simultaneous noise match and input match over
a sufficiently broad bandwidth an additional source inductance
is used. The design model is based on small signal and
noise parameter measurements of the transistor, without any
inductive feedback.
For decoupling purpose, but also to increase the robustness
[11], a resistor is used in the gate bias network.
In the frequency range from 8 GHz to 12 GHz a gain
between 15 dB and 17 dB is simulated. The expected noise
figure is about 1.75 dB to 1.8 dB.
In Fig. 7 the measured small signal gain and the noise figure
of the GaN MMIC LNA is shown. The gain is a little bit lower
than simulated, especially around 12 GHz a distinct slope is
measured. The obtained noise figure is better than expected
over the whole frequency band. The minimum noise figure is
only about 1.45 dB. For frequencies up to 11 GHz the noise
figure of this GaN LNA is only 0.5 dB worse than the normally
used GaAs LNA [12].
Besides the good noise performance the behavior of the
LNA with large input power signals is very important for this
type of LNA. The saturated output power of the LNA is about
24 dBm (see Fig. 8). First robustness tests have been performed
up to 4 W input power. At this input power level the LNA is
about 35 dB in compression. The output power is decreasing,
because the bias of the first stage transistor is shifted toward
deep pinch-off.
VI. T/R-M ODULE F RONT-E ND
For the front-end a multi-layer low temperature cofired
ceramic (LTCC) substrate is used. After obtaining first ex-
perience with an amplifier chain on LTCC with GaN MMICs
[13] some modifications are realized.
One big challenge is the thermal situation with these GaN
MMICs having a very high power density compared to today’s
state-of-the-art GaAs MMICs. A first approach was to use AlN
10 1.6
8 1.5
8 8.5 9 9.5 10 10.5 11 11.5 12
Frequency [GHz]
Fig. 7. Measured gain and noise figure versus frequency of the GaN MMIC
LNA with VDS = 15V and VGS = −3.5V . NFmin = 1.45 dBm
high temperature cofired ceramic (HTCC) instead of LTCC
because of its significantly higher thermal conductivity. In this
case the DA and the two HPAs were mounted directly on the
HTCC substrate in cavities. The thermal situation for the DA
was improved but the situation for the HPAs were dramatically
declined.
The favored solution today is using the mature and proven
LTCC technology for T/R-Modules used in series production
and soldering the DA similar to the HPAs on a CuMo heatsink.
The T/R-Module front-end consists of a whole transmit path
with one DA and two HPAs in parallel, a circulator, an receive
path with LNA and limiter and a GaAs switch combining both
pathes. It can be used as front-end for a software defined radar
or can be combined with any core chip using CMOS, SiGe or
GaAs technology.
Besides the RF relevant components, like power splitter and
combiner, also the whole DC control electronics is integrated
on the substrate. The control electronics provides the pulsed
30V drain voltage for the GaN high power MMICs, the
LNA bias voltages and the T/R-switch control. In Fig. 9 the
completely assembled front-end is shown.
For the transmit operation mode the output power, gain and
PAE measurement results in pulsed mode are shown in Fig. 10.
The maximum measured output power is 32W.

276
 25
Pout
Igate
20
Gate Current [mA]
15
10
Output power [dBm]
5 10
0
-5
-4 0 4 8 12 16 20
Input power [dBm]
Fig. 8. Measured output power and gate current versus input power of the
GaN MMIC LNA. Bias Point: VDS = 15V and VGS = −3.5V
Fig. 9. Photo of a T/R-Module front-end with GaN MMIC chips.
In this case the small signal gain is about 31 dB and the asso-
ciated front-end PAE value is 24%, also taking the disipation
power of the control electronics into account. More then 20 W
output power is measured over a bandwidth of 1.6 GHz.
In the receive operation mode a small signal gain in the
range of 13 dB is measured. The associated noise figure is
about 2.2 dB at room temperature.
VII. C ONCLUSION
A whole GaN MMIC amplifier chip set for a X-band T/R-
module front-end were designed, simulated, fabricated and
measured. Output power levels up to 20 W for the transmit
path HPA and a noise figure of 1.45 dB for the receive path
LNA are achieved. A T/R-module front-end with three types
of amplifiers (DA, HPA and LNA) integrated on multi-layer
LTCC substrates is successfully demonstrated. With such a
front-end, T/R-Modules with more then 20 W transmit output
power and a receive noise figure below 3 dB can be realized.
ACKNOWLEDGMENT
This work was partly funded by the German ”Bundeswehr
Technical Center for Information Technology and Electron-
ics” (WTD81), Greding and the German Federal Ministry of
Defense (BMVg), Bonn. This financial support is gratefully
acknowledged.
40 46
PAE
Gain
35 43
Output Power
30 40
PAE [%]
Output power [dBm]
25 37
20 34
Gain [dB]
15 31
28
5 25
0
0 2 4 6 8 10 12 14 16 18 20
Input power [dBm]
24 28 32 36
Fig. 10. Measured power performance of the GaN T/R-Module front-end at
11 GHz with VDS = 30V and VGS = −5V . Pmax = 45 dBm PAEmax = 24%
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