186
3, 2020
A Cryo-CMOS Voltage Reference in 28-nm FDSOI
Yuanyuan Yang , Kushal Das, Alireza Moini, Member, IEEE, and David. J. Reilly
Abstract—The control interface of a large-scale quantum computer
will likely require electronic subsystems that operate in close proximity
to the qubits, at deep cryogenic temperatures. In this letter, we report
low-temperature performance of a custom cryo-CMOS voltage refer-
ence circuit fabricated in a 28-nm fully depleted silicon on insulator
(FDSOI) CMOS process, dissipating about 15 µW. This MOS-only refer-
ence circuit is functional from room temperature down to liquid helium
temperature (4 K), showing a temperature coefficient of 0.6 mV/K. The
measured supply sensitivity of our reference circuit is better than −50 dB
at 4 K temperature. Beyond the specific application as low-power refer-
ence, this circuit is an ideal test-vehicle for developing design approaches
that mitigate the adverse effects of cryogenic temperatures on circuit
performance.
Index Terms—Cryogenic ASIC, cryogenic CMOS, cryogenic electron-
ics, fully depleted silicon on insulator (FDSOI), quantum computer,
voltage reference.
I. I NTRODUCTION
Voltage reference circuits are ubiquitous circuit blocks spanning
a large range of applications, including stand-alone voltage regu-
lators, complex mixed-signal integrated circuits (ICs), and system
on chips (SoCs). However, the basic semiconductor physics under-
pinning the functionality of the transistors themselves can limit the
circuit to applications operating near room temperature. When it
comes to deep cryogenic temperatures, silicon-based bipolar junc-
tion transistors (BJTs), which rely on thermally ionized dopants,
typically freeze-out to the extent that conventional voltage refer-
ence circuits are rendered nonoperational. This presents challenges
for emerging technologies such as quantum computers which require
their qubit control and read-out interface working at deep cryogenic
temperatures [1]–[4].
MOS devices are known to be functional at cryogenic tempera-
tures [5], [6], as the channel formation is based on inversion and does
not require thermally activated carriers. Using silicon germanium
(SiGe) heterojunction bipolar transistor (HBT) to replace silicon-
based BJT device in a BiCMOS process, Najafizadeh et al. [7]
demonstrated 700 mK to 300 K wide temperature range operation
with a 3.3-V power supply. However, the SiGe devices cannot be
tightly integrated with advanced-node CMOS devices to achieve high
system integration and low power. Our focus on cryogenic reference
circuits is motivated primarily by the need for stable, low-power volt-
age and current sources on-chip, dynamically configurable and tightly
Manuscript received May 15, 2020; revised June 24, 2020; accepted
July 10, 2020. Date of publication July 20, 2020; date of current ver-
sion August 7, 2020. This article was approved by Associate Editor
Sorin Voinigescu. This research was supported in part by Microsoft
Corporation and in part by the ARC Centre of Excellence for Engineered
Quantum Systems (EQUS) under Grant CE170100009. (Corresponding
author: Yuanyuan Yang.)
Yuanyuan Yang is with the ARC Centre of Excellence for Engineered
Quantum Systems, School of Physics, University of Sydney, Sydney, NSW
2006, Australia (e-mail: yuanyuan.yang@sydney.edu.au).
Kushal Das and Alireza Moini are with the Microsoft Quantum Sydney,
University of Sydney, Sydney, NSW 2006, Australia.
David. J. Reilly is with the ARC Centre of Excellence for Engineered
Quantum Systems, School of Physics, University of Sydney, Sydney, NSW
2006, Australia, and also with the Microsoft Quantum Sydney, University of
Sydney, Sydney, NSW 2006, Australia.
Digital Object Identifier 10.1109/LSSC.2020.3010234
2573-9603 
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IEEE SOLID-STATE CIRCUITS LETTERS, VOL.
integrated with auxiliary qubit devices in a scaled-up control system,
which could be ideally implemented in advanced CMOS technologies
and operates at deep cryogenic temperatures.
One type of MOS-only reference circuit uses diode connected
transistors [8], [9] and for cryogenic temperature operations, the
major challenge is the significant threshold voltage VTH increase
that occurs as MOS devices are cooled from room to cryogenic tem-
peratures [10], [11]. Another type of MOS-only voltage reference
implementation is to replace BJTs with MOS transistors operating in
subthreshold region [12]. Using dynamic threshold MOS (DTMOS)
devices, [13] and [14] extend the operation range from room tem-
perature down to 4 K with a 3-V power supply in a 40-nm CMOS
process. However, the power consumption of this reference circuit is
132 μW at 4 K, reducing the power budget for other blocks in a cryo-
genic system. Meanwhile, the power supply rejection ratio (PSRR)
may also need to be improved before it can be used as a practical
voltage reference.
In this letter, we present a MOS-only design that addresses several
issues encountered in cryogenic designs and has low power dissipa-
tion. Having a low temperature coefficient over the entire temperature
range from 300 K to 4 K is not a requirement, as the cryogenic oper-
ation of the circuit for quantum application will restrict the operating
temperature to be around 4 K. The voltage reference has been fabri-
cated in a 28-nm fully depleted silicon on insulator (FDSOI) CMOS
process and we demonstrate its cryogenic measurement results. This
letter is organized as follows: Section II presents our design choice
and circuit topologies; Section III presents the experimental results
of our reference circuits measured in a dilution refrigerator over a
wide temperature range; and Section IV is the conclusion.
II. C IRCUIT D ESIGN
Bulk CMOS processes suffer from two major challenges for cryo-
genic applications. The first challenge is the “kink effect” that was
prominent in older CMOS geometries [15], [16] and has been reduced
or eliminated in finer fabrication nodes. This effect increases the
uncertainty of a node voltage, reduces the gain of a control cir-
cuit, and can alter the stability margin of a feedback loop. The
second challenge is the significant threshold voltage VTH increase that
occurs as MOS devices are cooled from room to cryogenic tempera-
tures [10], [11], [15]. FDSOI processes address these challenges by
reducing the kink effect [17] and providing back-gate control nodes,
for both pMOS and nMOS transistors [18], enabling in situ control
of threshold voltage at cryogenic temperature.
The MOS-only voltage reference shown in Fig. 1 is based on
a modified form described in [19]. We have augmented the static
bias circuit with a dynamic start-up mechanism and also added an
additional dynamic start-up circuit. The primary reason is that at
cryogenic temperatures leakage currents that may assist the start-up
are almost completely absent. The start-up circuit comprised of MS3 ,
MS4 , and CS2 ensures that an initial current is injected to nodes X and
Y to kick start the circuit. For room temperature operation, there is a
small leakage current flowing through M6 and M7 current mirror and
the voltage at node Y will be around the voltage of diode-connected
transistors MX1 –MX4 , operating in weak inversion region. M2 will
YANG et al.: CRYO-CMOS VOLTAGE REFERENCE IN 28-nm FDSOI 187

Fig. 1. MOS-only voltage reference implemented using 1.8 V I/O transistors in 28-nm FDSOI CMOS process. R1 and R2a are implemented as 6-bit trimmable
resistors.

TABLE I
be turned on to pull down the gate voltage of M6 and M7 and the P ERFORMANCES S UMMARY OF MOS-O NLY VOLTAGE
circuit starts to function as designed. At cryogenic temperature, this R EFERENCE C IRCUIT
leakage current does not exist (or becomes extremely small). During
start-up, MS4 will pull the gate voltage of M6 and M7 down and
bring up voltages on node X and Y to turn on the differential pair
M1 and M2 .
Notice that at low current, the Y node has a higher impedance
than the X node, as the Y branch would not conduct current until
the node voltage at Y reaches around the threshold voltage of MX1 –
MX4 . The X node sees a constant impedance of R1 . Then at high
current, the Y node must see a lower impedance than the X node to
maintain stability at DC. As described in [19], the transistors MX1 –
MX4 operate at the edge of linear and saturation region to achieve zero
temperature coefficient (ZTC) current as well as ZTC drain voltage.
The output voltage can be derived as [19]
⎛ ⎞
 β
R2a ⎝ αηT0 T α ⎠
Vref = (1 − ) VTH0 − ηT + (1)
R1 β T0

where T0 is the temperature where dVgs /dT = 0, VTH0 is the extrap-

olated threshold voltage at T = 0 K, η is the temperature coefficient
of VTH , α is the velocity saturation factor, and β is the tempera-
ture exponent of mobility μ. The ZTC point occurs where α = β,
which occurs at the boundary between saturation and linear region
of MX1 –MX4 .
Considering that transistors MX1 –MX4 are effectively one long
transistor MX , we first assume MX works in the saturation region.
Due to the negative feedback, the node voltage at X and Y will be
the same as they are connected to the input of differential amplifier
formed by M1 –M5 . Thus, we reach the following expressions for of the two coupled loops is performed by adding zeros in the form of
saturation and linear regions: additional equivalent series resistance (ESR). The zeros from CC1 ,
RC1 and CC2 , RC2 cancels the internal pole at the gate of M6 and
2 VTH 1 V + 2VTH
R1 = + = + DS (2) M7 for individual loops. The compensation load capacitors CC1 and
gm,sat ID gm,lin 2ID the impedance seen at node X create an output pole pO1 at this node.
where gm,sat and gm,lin are the transconductance of MX in satura- Similarly, another output pole pO2 can be identified at node Y. It is
tion and linear regions, respectively, and VDS is the drain to source obvious that pO2 frequency is lower than that of pO1 , which main-
voltage of MX . It can be seen that for both operating conditions, the tains stability of the entire circuit. Table I summarizes the simulated
impedance of Y branch, which is 1/gm , is always smaller than the performance of our MOS-only voltage reference. The cryogenic tem-
impedance of X branch, R1 . Therefore, the Y and X branches form perature simulations are based on our set of extracted device models
the positive and negative feedback loops, respectively. at 77 K and 4 K.
For stable operations, we would like to ensure the negative feed-
back loop is always “stronger” than the positive feedback loop. That III. C RYOGENIC M EASUREMENTS
is to say, at all frequencies, the impedance at node Y should be The MOS-only voltage reference has been fabricated in a 28-nm
smaller that the impedance seen at node X. Frequency compensation FDSOI CMOS process and the chip photograph is presented in Fig. 2,

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188
TABLE II
P ERFORMANCE S UMMARY OF C RYOGENIC VOLTAGE R EFERENCE C IRCUIT
Fig. 2. Chip photograph of voltage reference circuit in 28-nm FDSOI CMOS
process. The blue-colored areas are power decoupling capacitors.
in which, we have also displayed the layout of the circuits as the
chip is fully covered by density fills. Cryogenic performance of the
reference circuit is measured in a BlueFors XLD dilution refrigerator.
In this setup, we first acquire data at room temperature, then we cool
down the sample in the fridge and perform measurements whenever
a predetermined temperature is reached.
The back-gate control has a strong effect on the output voltage of
this reference circuit as it directly modulates the threshold voltage
of MX1 –MX4 and this is also indicated in [18]. As can be seen in
Fig. 3, the output is very sensitive to the back-gate voltage. In our
design, this voltage is provided through a pad by a stable source. In
a self-supporting design, this should be provided from a low noise
and stable source. The default or zero back-gate bias in this process
is the ground potential for both of the pMOS and nMOS transistors.
When we refer to back-gate control voltage in our measurement,
unless particularly pointed out, we use a positive bias voltage for
the nMOS and a negative (with respect to ground) voltage for the
pMOS transistors. The measured reference voltage output for differ-
ent back-gate control voltages is presented in Fig. 3. It can be seen
that at 4 K, applying 1-V back-gate voltage can bring the output
voltage of this circuit to its room temperature value. We can also
observe from Fig. 3 that the output voltage in 4 K–20 K temperature
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IEEE SOLID-STATE CIRCUITS LETTERS, VOL. 3, 2020
Fig. 3. Measurement results on long channel MOS-only voltage reference
circuit for different back-gate control voltages along with the temperature
sweep. The back-gate control voltage is noted as “Vbg” in the figure.
range shows a relative low TC (the voltage curve is “flatter”). This
is important for our application for CMOS-based control systems
that can generate significant heat relative to the available cooling
power at cryogenic temperatures. The use of temperature-stable inte-
grated reference circuits can help mitigate the adverse effects arising
from on-chip temperature variations. At temperatures below 100 K,
we find that there is an increasing difference between the simulated
value of 500 mV and the measured value. The output voltage flat-
tens at temperatures below 20K, with a difference around 150 mV.
We attribute this to the presence of kink effect in the long MX tran-
sistors [17], which may have not been adequately represented in
our models.
In Table II, we have summarized our FDSOI voltage reference
with existing cryogenic reference circuits [7], [14], [20]. The power
consumption and noise performance are not directly measurable as
this circuit is sharing its supply with other blocks on the chip and
the output is connected to an on-chip buffer. The power sensitivity of
the reference circuit is measured by sweeping power supply voltage
from 1.5 to 2.1 V. The measured supply sensitivity differs from the
simulated ones. This is due to the lower supply rejection of the on-
chip buffer (for driving measurement instruments) which shares the
same power supply as the voltage reference circuit. The simulated
low-frequency PSRR performance of this buffer is about 51 dB at
300 K and 44 dB at 4 K.
YANG et al.: CRYO-CMOS VOLTAGE REFERENCE IN 28-nm FDSOI
IV. C ONCLUSION
We have presented the cryogenic operation of an MOS-only voltage
reference circuit in 28-nm FDSOI CMOS process. The circuit demon-
strates low-power operation across a wide-range of temperatures from
room temperature down to 4 K and a temperature coefficient of
195 ppm/◦ C at our desired operating temperature. This circuit also
achieves low supply sensitivity (−51 dB) at 4 K temperature. The
results and design challenges highlighted can guide the design of
voltage references, and in general provide some insight into issues
that can arise at cryogenic temperatures.
ACKNOWLEDGMENT
The authors would like to thank R. Rouse for many useful
discussions and help with managing tape-out of their 28 nm circuits.
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