Design of a Full SiC Voltage Source Inverter for

Electric Vehicle Applications

Alexander Bucher1, Ralf Schmidt1, Ronny Werner1, Michael Leipenat1, Christian Hasenohr1,
Timur Werner1, Stefan Schmitz2, Axel Heitmann2
1 2
Siemens AG, eCar Powertrain Systems Porsche AG
Frauenauracher Str. 85 Porschestraße 911
91056 Erlangen, Germany 71287 Weissach, Germany
Tel.: +49 9131 18 5175 Tel.: +49 711 911 85616
E-Mail: alexander.bucher@siemens.com E-Mail: stefan.schmitz2@porsche.de

Keywords
«Silicon Carbide (SiC)», «Automotive electronics», «Power converters for EV», «Voltage Source
Inverters (VSI)», «Switching losses»

Abstract
Taking into account typical power and temperature requirements of electric vehicle applications, sili-
con carbide based semiconductor devices seem to be the most promising candidates for future high
power density traction inverter applications. Therefore, the design of a three-phase DC-AC inverter
based on SiC MOSFETs under automotive constraints is discussed in this paper. In order to fully uti-
lize the performance offered by these superior power semiconductors, the electrical design of a high
power module in combination with a low inductance DC-link design is presented. The switching be-
havior of this prototype module is presented, emphasizing the significant improvements SiC power
devices offer in terms of performance over state-of-the art silicon IGBTs. For EV applications, the
obtained low switching losses in combination with the purely Ohmic output characteristics of these
devices result in substantial efficiency improvements which are determined by means of drive cycle
simulations. First test bench measurements are presented with the full SiC inverter operating at a
switching frequency of 40 kHz. Overall, SiC MOSFETs offer the possibility to significantly increase
the performance, power density and efficiency of the electric drive system.

Introduction
In order to meet present and especially future restrictions on carbon-dioxide emissions, car manufac-
turers seek technical solutions in order to increase the efficiency of power trains for their vehicle fleet
[1]. An increasing electrification of the drive train of passenger cars can be seen as a result of this de-
velopment, with micro and mild hybrids becoming a more and more common sight in today’s traffic.
However, for systems with a higher degree of electrification, a proper design of the power electronic
subsystems gains importance due to restrictions on efficiency and available volume. At the same time,
the obtainable performance of state-of-the-art power converters is often limited due to the limitations
(especially switching losses) of
the power semiconductors avail-
able at the moment. With novel
HV battery

SiC and GaN power semiconduc-

EMI vdc motor
tors becoming available on a
Cdc
broader basis, these limitations
could be overcome as discussed
by several authors, see for exam-
Fig. 1: Schematic of a 3-phase voltage source inverter sup-
ple [2], [3]. For automotive ap-
plying the traction motor with electrical energy from the
plications however, the benefits
high voltage board net

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 of these novel semiconductors can only be Table I: Drive train specification
exploited if the design of the inverter is taking
into account several critical aspects. Thus, this Vin = 450 … 850 Vdc fPWM,max = 40 kHz
paper focuses on the design of a 3-phase bidi- Pmech,max = 140 kW Iph,cont = 150 Arms
rectional DC-AC traction inverter as shown in
Fig. 1 under automotive constraints with a Tcoolant,max = 85 °C Iph,10s = 300 Arms
switching cell design optimized for SiC
MOSFETs. The obtainable switching perfor- nmax = 12000 rpm Mmax = 260 Nm
mance with a higher number of paralleled
chips per power module is one of the main
topics. In order to fully utilize the superior switching behavior of wide-bandgap devices, the designer
has to take care of low inductance bus-bar designs. Additionally, the increase in terms of inverter effi-
ciency compared to a state-of-the art Si-IGBT solution is discussed for an exemplary drive cycle.
The application covered by this paper is summarized in Table I. The battery voltage range at the input
is assumed to cover a comparably broad range, addressing future HV board net designs with a nominal
battery system voltage of 800 V. The maximum motor output power specified for the drive train is
fixed to Pmech,max = 140 kW in order to fully deliver this power under all state of charge conditions of
the HV battery system. Regarding motor currents to be supported, a continuous current of 150 Arms has
to be supplied with a peak value of 300 Arms for a duration of 10 s.

Module design
Due to the die size of commercially available SiC MOSFETs, several chips have to be paralleled with-
in the power module in order to cover the inverter specification given in Table I. Thermal loss calcula-
tion showed that 6 SiC MOSFET chips with RDS,on = 25 m: per die (@TJ = 25 °C) can fulfill the re-
quirements shown in Table I when incorporated in a pin-fin-cooler module with high thermal perfor-
mance. In addition, former measurements had proven a sufficient switching performance of the
MOSFET-intrinsic body diode, so that external Schottky barrier diodes could be omitted. The devel-
oped half bridge module therefore consisted in total of 12 SiC-MOSFET dies. Several direct copper
bonded (DBC) substrate layouts were evaluated, simulated and optimized in terms of thermal and
electrical aspects.
To fully take advantage of the fast switching SiC-MOSFET a very low inductive commutation cell
was in focus during module development. In this context several alternative concepts for connecting
the DC-link capacitor to the power module were evaluated. The resulting prototype module is shown
in Fig. 2.
Besides the electrical performance, additional focus was placed on designing a highly reliable power
module. For meeting the elevated automotive requirements, especially in the field of absolute tempera-
ture, active and passive temperature cycles, advanced packaging technologies had to be used to contact
the SiC dies. Thus, the back-
side of the MOSFETs was
attached to the DBC deploy-
ing Ag-sinter technology
which provides a superior
joint compared to standard
solder contacts [4], [5]. The
chip top side was connected
with Al-clad copper wire
bonds. This material can
offer an up to 10 times higher
power cycle capability and
50 % higher current capabil-
ity than standard aluminum
wires [6], [7]. To achieve a
low thermal resistance the
DBC was soldered with a Fig. 2: Housing and set-up of prototype module.

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 high reliable solder material directly onto an
aluminum pin-fin cooler, see Fig. 2. The
resulting thermal impedances of the final
layout for the top and bottom switch are in
very good agreement with a predicted value
of Rth,j-w | 150 mK/W and are shown in
Fig. 3.
To meet the elevated temperature require-
ments (calculated chip temperatures exceed-
ing 175°C for worst-case operation condi-
tions) a high temperature resistant silicone
gel was used for the insulation and appropri- Fig. 3: Thermal impedances
ate materials were selected for the module
housing and glue.
To get more flexibility for testing different DBC layouts, a spring contact adaptor board (PCB) was
implemented, which provides external contact pins at fixed positions, connecting to the control unit of
the inverter. So for testing the impact of alternative module layouts in the inverter just the PCB has to
be adapted. Additionally, all gate-resistors were attached to the PCB to be electrically more flexible
and save space for the power dies on the DBC.
During design phase several layouts were evaluated by simulating electrical and thermal behavior. In
the next step evaluation samples for the most promising designs were built up for switching behavior
measurements and reliability testing.

Inverter Design
In order to ensure reliable operation of the different subsystems connected to the HV power supply,
the voltage ripple generated by the inverter has to be limited. Thus, for increasing the power density
the PWM switching frequency is a key factor in order to minimize the required capacitance value for a
voltage source inverter. In case of a two-stage approach utilizing a DC-DC converter for stabilizing
the inverter’s input voltage, a further increase in power density can be obtained for higher switching
frequencies since also inductive components can be reduced in size [8–11]. By increasing the invert-
er’s switching frequency the generated ripple at the DC-link is reduced as illustrated in Fig. 4.
For a given limit of the admissible voltage ripple to be generated, the capacitance value can be reduced
accordingly. However, for motor loads, the ripple amplitude is influenced by the modulation index of
the inverter as well as the power factor of the load with analytical expressions for the capacitor voltage
ripple given in [12], [13]. Thus, for EV applications the motor characteristics have to be taken into
account in order to stay within the admissible ripple voltage limits even under worst-case conditions.
Additional restrictions on the minimum capacitance value can arise from requirements regarding spe-
cial conditions of operations such as load dumps. The results of time-discrete simulations taking into
account the motor characteristics of an au-
tomotive IPM designed for the investigated
800 V board net architecture under steady-
state operation are shown in Fig. 6.
In order to be able to reach higher switching
frequencies compared to state-of-the-art Si
IGBTs, special attention has to be paid to
the electrical design of the DC-link connec-
tion between power module and DC-link
capacitor. In case of wide-bandgap power
semiconductors, a low-inductance bus-bar
design is crucial in order to fully benefit
from the low switching losses these new Fig. 4: DC-link voltage ripple obtained by time dis-
devices can offer. An exemplary compari- crete simulations for a fixed point of operation
son of two bus-bar layouts is shown in (Vdc = 450 V, Vphase(1) = 150 Vrms, Iphase = 300 Arms,
Fig. 6. As known from literature [14], lami- cos(M) = 0,75) for different PWM frequencies.

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 nated conductors offer severe advantages
in terms of parasitic inductances over par-
allel split conductor set-ups. Thus, the
right-hand bus bar design shown in Fig. 6
was adapted for the DC-link connection
between the foil capacitor and the power
module. Screw connections were explicit-
ly avoided in order to minimize stray in-
ductance. For this goal, pressure contacts
have been developed for the commutation
cell in order to keep the bus bars laminated
all the way between the DC-link capacitor Fig. 5: DC-link voltage ripple obtained by time dis-
and the power module. crete simulations taking into account worst-case
The importance of a low-inductance points of operation for the motor with Vdc = 450 V,
commutation cell design is emphasized in Iphase = 300 Arms.
Fig. 7. All three displayed switching
waveforms have been synchronized to
bus bar 1 bus bar 2
t = 0 when the gate-source voltage has
fallen to 90 % of its initial value. For all
three commutation cells the turn-off speed
has been maximized to the point where the
drain-source voltage reaches its admissible
maximum value of 1200 V. The three
equivalent stray inductances resonating
with the output capacitance (Coss | 1,26 nF
at high blocking voltages) of the power
module correspond to LV1 = 35.5 nH,
LV2 = 16.6 nH and LV3 = 8.9 nH in the high
frequency domain. For the final bus bar
design an oscillation frequency of 48 MHz
was observed. The reduction of stray in- Fig. 6: Influence of bus bar geometry on DC-link
ductance results in a more than linear re- stray inductance. 2D simulations of two different bus
duction of turn-off losses with bar designs.
Eoff1 = 32.9 mJ, Eoff2 = 13.8 mJ and
Eoff3 = 6.0 mJ.
Typical turn-on and turn-off switching transients obtained by the final bus bar design are shown in
Fig. 8 for electrical worst-case nominal conditions. For valid measurement results regarding the
switching energy, the resulting time delay between the current and voltage sensor has to be compen-
sated [15–17]. For this purpose, the linear LC
oscillation following the turn-off event is
investigated. Under the assumption that all
components show linear behaviour for the
duration of this oscillation, the sensor delay
is adjusted in order to correct the phase delay
LV between the voltage and the reactive current
across the switch. The corresponding zero-
crossings are highlighted in Fig. 8 (b).
The switching losses obtained when
maximizing turn-off speed in terms of keep-
ing the switch within its safe operating area
at worst-case nominal conditions is shown in
Fig. 7: Comparison of turn-off drain-source voltage Fig. 8. The MOSFETs are driven with a
vDS(t) and source current iS(t) waveforms for dif- standard automotive-qualified driver IC.
ferent DC-link stray inductances under identical However, a careful choice of the driver IC
switching situations. and a suitable design of the gate driver circuit

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 (a) (b)

Fig. 8: Switching waveforms for Vin = 850 V, IL = 450 A, TJ = 25 °C, measured with a passive volt-
age probe and a coaxial shunt. (a) Turn-on (b) Turn-off

is crucial in order to handle the high switching speed, see [18]. In general, a linear relationship be-
tween the turn-on losses and the inductive load current was observed, see Fig. 8 (a). For the turn-off
losses shown in Fig. 8 (b), a slightly steeper increase was observed due to the dv/dt induced current
feedback via the Miller capacitance [19]. Regarding junction temperature, only a very minor influence
was observed in terms of switching losses (similar to the results published in [20]), even though no
external free-wheeling Schottky diode was used. A comparison of the turn-on waveforms for two dif-
ferent temperatures is shown in Fig. 10 (a). With increasing temperature an increase in reverse recov-
ery peak currents was observed, see Fig. 10 (b).
However, striving for lower switching losses inevitably leads to higher switching gradients and more
pronounced ringing with corresponding negative consequences regarding EMI noise [21]. In this con-
text, the measured di/dt and dv/dt values of the prototype are shown in Fig. 11. Compared to the gradi-

Vdc = 450 V Vdc = 850 V {{{ TJ = 150 °C y y y TJ = 25 °C

(a) (b)

Fig. 9: Switching losses for different junction temperatures TJ. (a) Turn-on (b) Turn-off

TJ = 150 °C

'Irr TJ = 150 °C

TJ = 25 °C

TJ = 25 °C

(a) (b)

Fig. 10: Comparison of reverse recovery peak currents for different junction temperatures TJ.
(a) Switching waveforms for Vdc = 800 V, IL = 720 A (b) 'Irr vs. IL

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 ents observed in silicon based Table II: Calculated losses per switch based on measured
IGBT power modules, these switching energies and output characteristics @
values are significantly high- Vdc = 850 V, fPWM = 40 kHz, Tcoolant = 60°C (80 °C),
er. Regarding the connection Rth,j-w = 160 mK/W. Temperature variations of switch-
to the motor, proper counter- ing losses have been neglected.
measures have to be taken in
case that the switching speed Iphase [Arms] 50 100 150 200 250 300
obtainable by these devices Pcond. [W] 7 29 68 129 219 357
shall be fully utilized and (8) (32) (75) (143) (245) (409)
negative aspects such as volt- Pswitch. [W] 21 34 47 61 75 93
age wave reflections and
bearing currents are to be
mitigated [22–24].
Resulting losses of the switching cell (neglecting losses in the DC-link capacitor, DC-link and ac bus
bars as well as losses in auxiliary power supplies) are given in Table II. Due to the temperature de-
pendent increase of conduction losses, high coolant temperature levels lead to a significant increase in
the total inverter losses. Due to their different temperature characteristics, this increase is more pro-
nounced for SiC-based inverters than for Si-based ones.

Vdc = 450 V Vdc = 850 V

(a) (b)

Fig. 11: Switching slew rates for different DC-link voltages (a) Turn-on (b) Turn-off

Drive Train Design

189 °C
Based on the characterization of the power Ipk,10s
module, the dynamic loss behaviour of the
inverter embedded in the drive system can be
113 °C
analysed. With respect to the thermal design 106 °C
of the power module, the temperature transi-
ents for repetitive peak current events under
Icont. 0,8Icont
worst-case conditions are shown in Fig. 12.
The overall power module design, i.e the
packaging technology, the DBC layout and
the right number of paralleled dies allows for
keeping the temp the maximum junction be- Fig. 12: Thermal response of junction temperature
low a temperature of TJ = 200 °C. For more vs. time for repetitive peak current events with
moderate coolant temperatures and current fPWM = 40 kHz, Tcoolant = 85 °C
levels, the SiC MOSFETs stay at lower tem-
perature levels with corresponding lower losses.
For a fair comparison with existing Si based traction inverters in terms of efficiency, the thermal be-
haviour of the power module during a drive cycle has to be investigated. In order to evaluate the ad-
vantages that SiC MOSFETs can offer, several drive cycle simulations were performed for two differ-
ent drive train systems. For this purpose, a state-of-the-art Si-IGBT based inverter for a nominal board

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 net voltage of 400 V was compared to the in-
vestigated full SiC system according to Table
I. Both sys tems are capable of generating the
same mechanical output torque and power,
however at different DC input current levels.
As an example, the analysis of a urban drive
cycle is shown in Fig. 13. Even though the
maximum inverter current is required several (a)
times during the drive cycle, see Fig. 13 (a),
the inverter is in part load operation for most
of the time. According to the load distribution
shown in Fig. 13 (b), the inverter has to deliver
output currents in the range below 0.2˜Iph,10s for
46 % of the duration of the drive cycle. Due to
minor deviations in the motor design, the rela-
tive current stress in the Si-based system is a (b) < 20 20 50 > 80 (c) < 20 20 50 > 80

…
little bit higher than in the SiC system. How- 50 80 50 80
ever, points of operation with currents of above Iph/Iph,10s [%] Iph/Iph,10s [%]
80 % of the peak current capability only accu- Fig. 13: Drive cycle analysis of a 400 V inverter
mulate to 4 % of the total mission time investi- based Si IGBT system (fPWM = 10 kHz) vs. a
gated in this drive cycle. A comparison of the 800 V inverter based on SiC MOSFETs
inverter power loss is shown in Fig. 13 (c) for (fPWM = 20 kHz) for a fixed coolant tempera-
the clustered current ranges (the transient loss- ture of Tcoolant = 70 °C.
es are averaged over time for time steps within (a) Current consumption in relation to Iph,10s
the corresponding current range). Despite the (b) Distribution of operation points
significantly higher PWM switching frequency (c) comparison of inverter losses
in the SiC system (fPWM = 20 kHz for the SiC
system instead of fPWM = 10 kHz for the Si
system), inverter losses are roughly halved. The same general behavior was observed for several dif-
ferent drive cycle simulations also containing more aggressive driving scenarios.

Drive Train Measurements

The SiC-based inverter has been tested within an 800 V powertrain system as outlined in Fig. 14. In
order to benchmark the new inverter with respect to a conventional 400 V Si-based inverter a 400 V
IPM motor has been taken as reference. A second motor has been rewound to meet the requirements of
the 800 V nominal board net voltage according to Table I. Even though the achievable copper fill fac-
tor was slightly reduced due to the increased insulation requirements, no significant negative effects
on motor performance were observed on the motor test bench. Without any further optimizations in
the system architecture the SiC-based powertrain could provide 3% more peak power than the compa-
rable Si-based system.
In order to emphasize the impact of replacing standard Si IGBT by SiC MOSFETs the SiC DUT was
implemented in the same inverter form factor and housing as it has been used for the Si-based one but
with a significantly reduced DC-link capacitor because of the higher PWM-frequency. The effect of

i1

i2

250 i3

Fig. 14: Test bench set-up used for drive train measurements.

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 (a) (b)

Fig. 15: Test bench measurements of inverter supplying Iph = 300 Arms to an automotive motor de-
signed for 800 V HV board-net voltage systems at n = 5000 rpm, M = 270 Nm, Pmech = 141 kW
(a) fPWM = 20 kHz (b) fPWM = 40 kHz

the vdc-ripple reduction due the increased PWM switching frequency is illustrated in Fig. 15. It has to
be noted that the DC-link voltage waveforms shown in Fig. 15 still contain switching noise to a certain
degree as no filtering for the measurement signal has been applied during the measurement. Addition-
ally, an interaction between the DC source of the test bench and the inverter dc-link capacitor was
observed for fPWM = 40 kHz, with the stiffness of the voltage source as possible explanation of this
effect. Furthermore, the DC-side EMI filter stage has not yet been optimized with respect to the
switching behavior and PWM frequency of the SiC inverter. A detailed EMI characterization and filter
optimization taking into account the power density impact of replacing Si with SiC devices will be the
topic of a future paper.
Regarding the measurement set-up, higher dv/dt stress at the inverter output results in significantly
higher requirements on proper EMI-solutions for the power-train and for the test bench side. Addition-
ally, the very high efficiency of the inverter requires measurement equipment with small measurement
errors in order to end up with meaningful readings [25], [26]. These aspects increase the complexity
and expenses on the measurement equipment drastically.
Furthermore, the high dv/dt capability causes additional oscillations on the AC-cables if they are too
long [22], [23]. Therefore, the distance between the inverter and the motor cannot be set as freely as
with a conventional Si-based inverter without having to artificially slow down the switching speed of
the SiC devices (generating higher switching losses) or reducing the obtainable PWM frequency (in
order to cope with increased switching losses, additionally requiring higher DC-link capacitance val-
ues). Therefore, implementing SiC power devices in the drive train of an electric vehicle requires a
comprehensive optimization of the complete system.

Conclusion
SiC MOSFETs as normally-off unipolar devices offer several advantages over Si IGBTs. Main per-
formance improvements arise from the massive reduction of switching losses and improved part load
efficiency due to their purely Ohmic output characteristics. On the one hand, these devices offer the
possibility to significantly increase the switching frequency of switched-mode power converters, de-
creasing the volume necessary for passive components. On the other hand, depending on the applica-
tion’s mission profile, a significant reduction of inverter losses can be obtained.
The SiC MOSFETs investigated in this paper show very good switching behavior even though a high-
er number of dies was paralleled. In terms of module design, attention has to be paid to materials and
interconnection technologies for the power module if high temperature operation has to be enabled
under automotive life-time and reliability constraints.
From a power electronics point of view, the commutation cell has to be designed with parasitic induct-
ances in mind in order to be able to fully utilize the switching performance offered by these devices.
As successfully demonstrated, an increase of the inverter PWM switching frequency of a factor of 4
from 10 kHz to 40 kHz is feasible in case of a low inductance design of the switching cell. The mas-

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 sive increase in switching speed compared to Si IGBTs requires a proper mechanical and electrical
design in order to cope with the corresponding switching slew rates.
Regarding automotive applications, it was confirmed by drive cycle simulations that the inverter losses
can be roughly halved even if the PWM frequency is doubled compared to a state-of the art Si IGBT
solution due to the low switching and part load conduction losses of the investigated SiC MOSFETs.
In addition to DC-link capacitor size reductions, further benefits can be exploited with regard to motor
design. For this however, modifications of the control strategy, the motor design and the entire system
architecture are necessary. Strong need of further investigations regarding the most favorable PWM-
frequency range, dv/dt switching slew rates and motor designs have been identified for the improve-
ment of future traction powertrains.

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