4252 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO.
4, JULY/AUGUST 2023
A Single-Stage Charger for LEV Based on Quadratic
Buck-Boost AC-DC Converter Topology
Aswin Dilip Kumar , Jitendra Gupta , Member, IEEE, and Bhim Singh , Fellow, IEEE
Abstract—A single-stage AC-DC converter, which uses a
quadratic buck-boost voltage gain, for LEVs’ (Light Electric Vehi-
cles) battery charging is presented in this work. Unlike conventional
BCs (Battery Chargers), which employ transformer (low or high
frequency) based approaches to charge low voltages LEVs’ bat-
teries, the presented charger utilizes transformerless single-stage
power architecture. In order to realize desired charging of LEVs
and to maintain proper transformerless voltage gain, the presented
quadratic buck-boost AC-DC converter ensures high step-down
gain characteristics between AC mains and low voltage battery
packs. Besides realizing desired battery charging profile, the pre-
sented single-stage BC ensures high PQ (Power Quality) indices
(low input current distortions and unity power factor operation) at
the supply side. Notably, the presented quadratic buck-boost AC-
DC converter exhibits an intrinsic power factor correction (PFC)
feature at the AC input mains under discontinuous inductor cur-
rent mode (DICM) operation, thereby, incurring minimum com-
plexities during the control implementation, which further reduces
the cost of the charger. The DICM operation facilitates negligible
switch turn-on and diode reverse recovery losses, and therefore,
ensures an improved conversion efficiency of the BC. Even if, the
presented AC-DC converter employs two switching devices, the
simultaneous switching of both switches shrinks the cost and com-
plexity of driving circuitry even further. Finally, a comprehensive
operational analysis, component selection criteria, and modelling of
the presented quadratic buck-boost AC-DC converter-based LEVs
BC are carried out and its performance is validated through a
test bench set-up in a laboratory environment. Relevant results
are presented to validate the efficacy of the presented quadratic
buck-boost AC-DC converter for LEVs charging applications.
Index Terms—Battery charger, battery packs, discontinuous
inductor current mode, electric vehicles, light electric vehicles,
power quality, quadratic buck-boost AC-DC converter.
I. INTRODUCTION
HE applications of electric vehicles (EVs) even after the
T significant advantages they have over conventional internal
Manuscript received 6 September 2022; revised 30 November 2022 and 13
February 2023; accepted 7 March 2023. Date of publication 21 March 2023; date
of current version 19 July 2023. Paper 2022-IPCC-0849.R2, presented at the
2022 IEEE IAS Global Conference on Emerging Technologies, Arad, Romania,
May 20–22, and approved for publication in the IEEE TRANSACTIONS ON INDUS-
TRY APPLICATIONS by the Industrial Power Converter Committee of the IEEE In-
dustry Applications Society [DOI: 10.1109/GlobConET53749.2022.9872394].
The work was supported by SERB National Science Chair Fellowship. (Corre-
sponding author: Aswin Dilip Kumar.)
Aswin Dilip Kumar and Jitendra Gupta are with the Electrical Engineer-
ing, Indian Institute of Technology Delhi, New Delhi 110016, India (e-mail:
aswindilip98@gmail.com; jitendra.gupta2210@gmail.com).
Bhim Singh is with the Department of Electrical Engineering, Indian Institute
of Technology Delhi, New Delhi 110016, India (e-mail: bsingh@ee.iitd.ac.in).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TIA.2023.3259944.
Digital Object Identifier 10.1109/TIA.2023.3259944
0093-9994 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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combustion (IC) engines, are very limited in most countries.
The EV industry’s barriers are the lack of proper charging
infrastructure and the poor grid side performance pertaining
to most existing technologies. Battery electric vehicles (BEVs)
are the most popular ones in the EV industry due to their sole
dependency on electricity. A dominant section of the BEVs is
led by the electric two and three-wheelers, namely, light electric
vehicles (LEVs), which include, E-cart, E-rickshaws, E-bikes,
and E-scooters, and constitute a major part of the global EV
market [1]. One of the major issues, the chargers of LEVs face,
is the highly distorted and low power factor current being drawn
from the supply side, which causes other losses and issues at
the grid side [2], [3]. Even though the EV industry has seen
considerable developments with regard to high-performance
battery chargers, there is scarce development for the chargers
in the LEV spectrum and needs further emphasis.
In the literature, many power factor correction (PFC) tech-
niques both active and passive techniques, have been discussed
to improve the power factor and the reduction of current dis-
tortion at AC mains, caused due to harmonics produced as a
result of the non-linearity in the charger configuration [4]. Active
PFCs (APFCs) are more reliable with respect to the passive PFC
(PPFCs) techniques because of the large size, poor operational
ranges, and the losses PPFCs have as compared to the former.
Notably, based on APFCs, the battery chargers can be imple-
mented both in single-stage and two-stage configurations. A
two-stage battery charger employs an APFC AC-DC converter at
the front end stage and a DC-DC converter at its back end stage.
Such charger configurations certainly have the advantages of
ripple-free charging current to the battery, lower electrical stress
across semiconductor devices and fast dynamic performance at
the output end [3], [5], [6], [7]. The converter in [3], for exam-
ple, has excellent input side performance, owing to the current
sharing feature due the interleaved structure at the front-end, and
further the control of such PFC circuits at the frontend remains
complex. Thus, these two-stage chargers have disadvantages in
terms of rigorous control, increased number of component count
and high implementation cost, as compared to the single-stage
topologies. In an attempt to counter the aforesaid disadvantages,
several single-stage APFCs AC-DC converter topologies have
been developed [8], [9], [10], [11], [12], to provide an eco-
nomic solution, especially for low-cost battery charging such
as LEVs charging. In a single-stage approach, both the PFC at
the input side as well as the charging current regulation at the
battery side are carried out through the APFC AC-DC converter.
Consequently, the single-stage approach helps in developing
cost-effective, simple, and compact battery charging circuits.
In previous attempts, several APFC AC-DC converters
based on buck, boost, and buck-boost derived topologies, are
presented for various applications, including but not limited
KUMAR et al.: SINGLE-STAGE CHARGER FOR LEV BASED ON QUADRATIC BUCK-BOOST AC-DC CONVERTER TOPOLOGY
to charging applications. However, the problem of inherent
AC line current distortion at zero-crossover of the buck and
buck-emanated APFC AC-DC topologies, enforces a limit on
the achievable THD and power factor of these converters. Even
if, the boost-derived APFC AC-DC topologies can achieve good
input side performance with respect to the PQ indices, such
converters unavoidably require a second stage to step down
the voltage for the LEVs battery charging applications, and
hence, result in limited applicability for LEV BCs involving
only a single-stage. Therefore, APFC AC-DC converters derived
from conventional buck-boost topologies, seem best suited for
single-stage LEVs BCs applications. However, conventional
buck-boost based APFC topologies [13], [14], [15], demon-
strate limited gain capability and therefore, cannot be employed
directly in a single-stage LEVs charger’s application. As their
limited gain capability forces the converter to operate at very
low duty ratios, especially during wide AC mains conditions.
For example, the converter in [13], has numerous advantages in
terms of being single-stage, having bridgeless structure, lower
component count, and low control complexity. However, the
limited voltage gain of this converter, limits its applicability
to wide voltage range operations. Moreover, increasing the
frequency of operation of these topologies would mean that
the duty ratio goes even shorter, thus derating the efficiency of
the overall charging circuitry [16]. Therefore, the single-stage
chargers based on buck-boost derived APFC AC-DC converter,
inevitably require low/high-frequency step-down transformers
to carry out effective charging of low voltage battery packs of
LEVs. The converter in [2], which is a single-stage charger,
uses a high-frequency isolation transformer, for achieving the
positive output voltage polarity as well as for obtaining a higher
step-down. This means that even though this converter has the
advantages of single-stage, higher step-down gain and require-
ment of low sensing devices, the presence of the isolation trans-
former further increases the complexity of the converter. In such
cases, the transformers primarily maintain the desired voltage
gain between AC mains and low voltage battery packs and
secondly isolate battery packs from the grid [17]. Considering
the isolated single-stage charger of [18], the bridgeless design at
the input, with reduced conduction losses, and reduced overall
device count certainly provide great advantages. However, the
transformers add size, cost and complexity to the chargers,
and also impact the electrical stress across switching devices,
if not designed accurately. The aforesaid disadvantages have
motivated researchers to look for alternative methods to achieve
transformerless voltage gain regulation between high voltage
and low voltage sources. Based on this, various transformerless
high gain APFC AC-DC converters emanated from switched
capacitor, coupled inductor, switched inductor, and multiplier
circuits have recently been explored in the literature [19], [20],
[21], [22], [23]. Out of these, some offer extended step-down
gain whereas, others offer extended step-up gain capability, how-
ever, the limitations related to buck and boost-derived topologies
still persist in such topologies, which further limit their appli-
cability in single-stage LEVs charging applications. Therefore,
high gain converters with buck-boost capability are presented in
[19], [20], [21] and could be applied for developing transformer-
less single-stage LEVs charging applications. Based on this,
few authors have explored transformerless BCs in [13], [16],
[22], [23]. However, complex control, limited battery voltage
range capability due to non-quadratic gain characteristics of
APFC AC-DC converter, and high component count, are the
major drawbacks. Here, it is mentionable that, the applicability
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4253
of quadratic gain converters based APFC AC-DC conversion
system for the charging application of LEVs, is still disregarded
and therefore, explored in [24], [25].
Apart from the selection of power converter topology, the
implementation of control is also having great importance, as it
can add cost-effectiveness, simplicity, and compactness to the
overall charging circuity. Among various control approaches,
two design and control methods, i.e., continuous inductor current
mode (CICM) or discontinuous inductor current mode (DICM)
controls are frequently applied in APFC AC-DC converters.
Even though, the CICM design and control ensure lower cur-
rent stress through components, it significantly adds control
complexity and associated cost of implementation, and there-
fore, does not justify its applicability in low to medium power
applications. Conventional converters based on a CICM boost
converter for PFC at the frontend, followed by a full-bridge
DC-DC converter at the backend, use large inductors as well as
complex control. The control strategy for the frontend PFC has
to maintain a regulated output voltage as well as a sinusoidal
template at the input current. Added to this, the CICM inner
current controller loop for the boost stage requires a higher band-
width and correspondingly an increased sampling frequency to
adjust to the inductor current dynamics. This means that two
digital signal processors (DSPs) or a combination of digital and
analog controllers have to be used, for the control of both the
frontend and backend circuits, which increases the cost and
complexity [26]. Moreover, the control of CICM converters
require phase-locked loop (PLL), which achieves the grid syn-
chronization. The control implementation further requires input
voltage and input current sensors, along with output voltage and
output current sensors, which increases the cost of the charger,
and makes it unreliable [27]. Besides, the DICM design and
control not only decrease the volume of magnetic components
but also add simplicity and cost-effectiveness during controller
implementation [20], [28], [29], [30], [31].
Based on the above discussion, a transformerless single-stage
battery charger based on a quadratic buck-boost APFC AC-DC
charger is demonstrated in this work for LEVs applications. The
following points describe the salient features of the presented
work.
r The presented battery charger based on a quadratic buck-
boost APFC AC-DC converter ensures considerable im-
provement in the power quality indices at the supply AC
mains and delivers the required battery charging current
profile while operating over an extended span of AC input
mains voltage and battery voltage conditions.
r Further, the transformerless voltage gain adjustment ap-
proach improves the complexity, cost and efficiency of
conversion of the combined charging system.
r Furthermore, the presented APFC AC-DC converter topol-
ogy facilitates intrinsic power factor correction at AC
mains while operating under DICM mode operation, which
further optimizes the cost and complexities of control
implementation of the overall charging system.
r Besides, the DICM operation reduces the size of magnetic
components, and guarantees zero current switching of the
semiconductor components.
r The operational analysis, design guidelines, and controller
design through a small signal modelling method, of the
proposed APFC AC-DC converter-derived LEV charger,
are discussed comprehensively.
r Finally, the complete performance of presented charger is
validated through proof-of-concept test bench prototyping,
4254
Fig. 1. Single-stage quadratic buck-boost gain charger topology.
and test results for various operating conditions are show-
cased to validate the efficiency and proposed advantages
of presented APFC AC-DC converter in LEVs charging
applications.
The remaining part of the article includes the structure of
the charger in Section II, operational principle and steady-state
analysis in Section III, design of the charger configuration in
Section IV, control strategy in Section V, performance analysis
in Section VI, and conclusions in Section VII.
II. STRUCTURE OF CHARGER
The presented single-stage AC-DC converter based on a
quadratic buck-boost gain for LEV charging application, is
shown in Fig. 1, where, VS refers to the supply AC single-
phase input voltage, VC1 refers to the average voltage across
the intermediate capacitor C1 , I1 and I2 refer to the reference
current direction taken for the inductors L1 and L2 , respectively.
The diode bridge rectifier (DBR) at the frontend provides a
rectified output, from a single-phase AC supply. The EMI filter
comprising of the filter inductance Lf and the filter capacitance
Cf together provides an improved power quality performance
at AC mains, by absorbing switching harmonic ripples at the
input end. Lf and Cf are designed at a cut-off frequency much
lower than the switching frequency, such that the harmonics
at the switching frequency are eliminated at the input. Further,
the rectified output at the frontend structure is fed to a circuit
consisting of two IGBTs, S1 and S2 , high-frequency diodes, Da
and Db , inductors, L1 and L2, intermediate capacitor, C1 , and
output capacitor, CDC . Notably, both L1 and L2 are operated
in discontinuous inductor current mode (DICM) operation and
the switching of both S1 and S2 is carried out simultaneously to
simplify the charger circuitry.
The capacitor CDC at the output acts by preventing and
absorbing the second harmonic component of charging current,
from flowing to the battery. Finally, after CDC , the battery is
connected as load to the charger, which is rated for 450 W, 48 V
nominal voltage. It is noteworthy that, from hereon, throughout
this work, the voltage and current polarity reference of each
component in the presented charger configuration is followed as
shown in Fig. 1. Besides power circuitry, the control strategy and
architecture of the presented charger are explained in Section V.
III. PRINCIPLE OF OPERATION AND STEADY-STATE ANALYSIS
OF PRESENTED CHARGER
In this section, a comprehensive analysis of the operating
principle of the charger configuration is presented. The operation
of the charger is comprehensively explored, for the operation
within a switching cycle, corresponding to the positive half cycle
of supply voltage, and is explained with the appropriate circuits
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO. 4, JULY/AUGUST 2023
in Fig. 2. and waveforms in Fig. 3. The operation during the
negative half cycle of supply voltage is exactly the same as its
operation during the positive half cycle, and is therefore, avoided
during the operational analysis.
Mode-I (t0 -t1 ): During this mode, both switches S1 and S2
are turned ON, whereas, the high-frequency diodes Da and Db
are in blocked states. The inductors L1 and L2 get energized,
and their currents increase linearly with a positive slope, as
shown in Fig. 3. The voltage across intermediate capacitor C1
drops during this mode. The output capacitor, CDC feeds the
battery during this mode. The inductor voltages and capacitor
currents during this mode are expressed as;
L1 (di1 /dt) = Vin + VC1 (1)
L2 (di2 /dt) = VC1 (2)
C1 (dvC1 /dt) = iC1 = −(i1 + i2 ) (3)
CDC (dvDC /dt) = − ibatt (4)
The turn-off of switches S1 and S2 , marks the end of Mode-I,
and the start of Mode-II. The equivalent circuit consisting current
flow path during this mode is shown in Fig. 2(a).
Mode-II (t1 -t2 ): During this mode, diodes Da and Db get
forward biased, with capacitor C1 starting to store energy, and
hence the voltage rises across it. A negative voltage drops across
the inductors L1 and L2 during this mode, and hence the currents
through these inductors drop. This mode continues up to the
point where the inductor current ceases to zero, which marks the
end of Mode-II. The inductor voltages and capacitor C1 current
during this mode are expressed as;
L1 (di1 /dt) = − VC1 − Vbatt (5)
L2 (di2 /dt) = − Vbatt (6)
C1 (dvC1 /dt) = i1 (7)
CDC (dvDC /dt) = (i1 + i2 ) − ibatt (8)
The equivalent circuit consisting of the current flow path
during this mode is shown in Fig. 2(b).
Mode-III (t1 -t2 ): The equivalent circuit consisting current
flow path during this mode is shown in Fig. 2(c). This mode
begins with the inductor currents ceasing to zero at the end of
Mode-II and continues up to the turning on of the S1 /S2 in the
next switching cycle. This mode denotes the DICM operation of
L1 and L2 , with the currents remaining zero during this interval.
The voltages across both inductors are zero, and the capacitor
voltage remains constant, with its charging current being zero.
The detailed operation of the charger, with the inductor currents
in DICM, is explained further in the upcoming subsections. It is
to be noted that, from hereon, the duty ratios corresponding to
switches S1 , S2 and diodes Da , Db are denoted by D1 and D2 ,
respectively.
By applying the volt-balance principle to the inductor voltages
during all three modes of operation, from (1), (2), (5) and (6),
the voltage gain, ‘M’ of the charger is expressed as;

M = Vbatt /Vin = D12 D22 (9)
The voltage across Lf during all the three modes is same, and
is given as,
Lf (dif /dt) = VS − Vcf (10)
Therefore, by applying volt-second balance across Lf for all
the three switching modes,
⎫
VLf TS = (VS − Vcf ) .D1 + (VS − Vcf ) .D2 ⎬
+ (VS − Vcf ) .(1 − D1 − D2 ) (11)
= VS − Vcf = 0 ⎭
KUMAR et al.: SINGLE-STAGE CHARGER FOR LEV BASED ON QUADRATIC BUCK-BOOST AC-DC CONVERTER TOPOLOGY 4255

Fig. 2. Current flow path and equivalent circuit during (a) Mode-I, (b) Mode-II and (c) Mode-III.

Fig. 4. Switch S2 and diode Db currents within a switching interval.

Notably, the D1 should be selected lower than the value given

in (14), to ensure the DICM operation of the charger under a
wide range of input and output voltage conditions.

A. Design Guidelines for L1 and L2 in DICM

This section provides a comprehensive mathematical analysis
to mark out the design guidelines for the charger’s components
as per their working principle. It is noteworthy that, the relation
between the voltage gain ‘M’ and the conduction parameter ‘ξ’
of the charger under DICM operation is to be derived, in order
to create a direct relationship between the equivalent inductance
of the charger with the required voltage gain. This relationship
simplifies the design of L1 and L2 .
Initially, the S2 and Db currents within a switching cycle are
inspected and redrawn here in Fig. 4.
Evidently, the peak of IS2 and IDb is identical, and given as;
iS2(peak) = iDb(peak) = i1(peak) + i2(peak) (15)
Where, i1(pk) and i2(pk) , are the peak currents through L1 and
L2 , respectively, and expressed as;
i1(peak) = (Vin + VC1 )D1 TS /L1 and i2(peak) = VC1 D1 TS /L2
(16)
Further, the average voltage across C1 is obtained by volt-sec
balance, and is expressed as,
VC1 = Vin (D1 /D2 ) (17)
Since the average current through Db remains equal to the
Fig. 3. Current and voltage waveforms in one switching cycle. charging current, both can be expressed as,
iDb(avg) = ibatt = Vbatt /R = (1/2)iDb(peak) D2 (18)
Theoretically, the magnitudes of VS and Vcf remain the same Using (15)–(18), the relationship between Vin and Vbatt in
in a switching cycle, thus, the voltage gain remains unaffected, terms of circuit parameters, is obtained as,
and hence;
 Vbatt /R = (Vin D1 D2 TS )/(2Leq ) (19)
M = Vbatt /Vin = Vbatt /VS = D12 D22 (12)
Where, Leq is the equivalent inductance of the charger, and
For the inductors to operate in DICM, the following constraint R is the assumed equivalent load resistance. Further, Leq is
must be satisfied; represented as,

D1 + D 2 < 1 (13) 1 D1 1 1 1
+ + = (20)
L1 D 2 L1 L2 Leq
Solving (9) and (13), the maximum value of D1 , so that the
inductor currents show DICM operation, is obtained as; Rearranging (19), the desired expression relating to conduc-
√  √  tion parameter (ξ) and M, is obtained as,
D1 < M 1 + M (14) M = (RD1 D2 TS ) /2Leq = (D1 D2 ) /2ξ (21)
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4256 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO. 4, JULY/AUGUST 2023

Where, the ξ is represented as ξ = Leq /(RTS ). Based on TABLE I

VOLTAGE AND CURRENT EXPRESSIONS FOR EACH COMPONENT OF PRESENTED
(19)–(21), the DICM design of L1 and L2 is carried out to ensure CHARGER TOPOLOGY
satisfactory operation of the charger over a wide operating range.

B. Intrinsic Power Factor Correction Capability at AC-Mains

Under DICM Operation of Inductors
Since, the presented quadratic buck-boost AC-DC converter
facilitates intrinsic power factor correction capability at the AC
mains under DICM, this feature is mathematically validated in
this subsection. Referring to (16) and (17), the average rectified
current and voltage that appear at the output of the DBR are
expressed as,
iin = (Vin TS Ka )/2L1 , where Ka = [(D1 + D2 )D1 ]2 /D2
(22)
Using (22), the constant Ka is related to voltage gain M as;
 √ 2 √
Ka = D13 1 + M / M (23)
By maintaining Ka constant, a control law is implemented,
such that the average rectified input voltage and current is held
proportional.
Rearranging (23),
√  √ 2
D13 = Ka M / 1 + M (24)
Since Vin varies from 0 to Vin(max) , the maximum value of
D1 is obtained as;
 2
3
D1(max) = Ka Mmax / 1 + Mmin (25)
Rearranging (25),
 2
Ka = D1(max)
3
1+ Mmin / Mmax (26)
Which is treated as a constant, considering maximum and
minimum values of Vin and Vbatt are fixed. Therefore, (22) is LEV charging applications. Further, a switching frequency of
rewritten as; 20 kHz is chosen for the control of the charger.
iin = Vin /Remulated , where Remulated = 2L1 /(Ka TS ) Firstly, the Vin is calculated as,
 √ 
(27) Vin = 2 2VS /π (28)
is the emulated resistance as seen from the input side.
From (27), it is clearly evident that by implementing a control Where, Vs is the RMS value of supply voltage. Considering,
that keeps Ka constant, inherent power factor correction is easily the given battery voltage and input voltage range, the maximum
achieved, without having to sense the supply voltage profile for D1(max) and minimum D1(min) values of D1 are obtained from
input current shaping. This means that there is no requirement for (14), and given as 0.411 and 0.285, respectively.
additional sensing circuitry, and reduces the control complexity
of the charger. A. Design of L1 and L2 in DICM
The minimum critical value of L1 for it to operate at the
C. Voltage and Current Expressions for Charger’s boundary of CICM and DICM, is given as,
Components
L1(crit,min)
The voltage and current expressions for each component of  
the presented charger are derived to ensure and to demonstrate = VS2 max D1(min)
2
2Prated (1 − D1(min) )fS
the safety and reliability of the charger and to analyse the
corresponding theoretical losses of the charger. The derived 2502 × 0.2852
expressions are summarized in tabular form in Table I. = = 396 μH (29)
2 × 450 × (1 − 0.285) × 20 × 103
The inductance L1 is chosen at a much smaller value of 150
IV. DESIGN OF CHARGER CONFIGURATION μH, to ensure that inductor current operates in DICM.
The charger configuration is supplied from a single-phase AC For the design of L2 , a switch duty ratio, lower than the mini-
supply mains (VS ), which has a nominal supply voltage RMS mum switch duty ratio (D1(min) ), which is obtained previously
of 220 V, with supply voltage fluctuations from 160 V to 250V is used. This ensures that the inductor L2 operates in DICM
(RMS). Further, the charger is rated for 450 W (Prated ), and the during all the supply and battery pack voltage ranges. Therefore,
battery pack has a nominal voltage (Vbatt ) of 48 V, along with for accomplishing such a design of L2 , a switch duty ratio of 0.2
the battery voltage range from 36 V (Vbmin ) -72 V (Vbmax ), in is chosen, which is quite lower than the minimum switch duty
order to cater the needs of different battery packs for various ratio (D1(min) ) that is obtained earlier as 0.285. Recalling (9),
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KUMAR et al.: SINGLE-STAGE CHARGER FOR LEV BASED ON QUADRATIC BUCK-BOOST AC-DC CONVERTER TOPOLOGY 4257

the voltage gain M is related to the switch and diode duty ratios
(D1 and D2 ) as,
M = D12 /D22 (30)
From (30), D2 is obtained as;
√
D2 = D1 / M (31)
With the obtained D1 and D2 , the Leq of the charger is
determined from (21) and found equal to 46 μH. Rearranging
(20), and solving for L2 using the previously obtained values of
D1 , D2 , L1 and Leq , Fig. 5. Digital implementation of charger controller circuitry.
D1 L1 Leq
L2 =
D2 L1 − (D1 + D2 )Leq frequency, but not less than the fline . The expression for Lf is
−6 −6 given as [32],
0.2×150×10 ×46×10
= = 40 μH
0.417×150×10−6 −(0.2+0.417)×46×10−6 Lf =
1
(32) (2πfCf )2 (Cf )
Finally, the L2 is selected equal to 40 μH. 1
= = 2.3 mH (38)
(2π × 5000) × 0.44 × 10−6
2
B. Design of C1
Finally, the Lf is selected as 2.5 mH.
In order to reduce the effect of resonance at the switching
frequency of the charger, C1 is designed considering a cut-off
frequency (fc ) lower than the switching frequency (fS ), but not V. CONTROL OF CHARGER
going below the line frequency fline [32]. Considering the above- The control strategy of the presented charger uses a dual
mentioned limits, the expression for the design of capacitance loop control, with the outer loop controlling the battery voltage
C1 is given as, and the inner loop controlling the battery current correspond-
C1 = 1 (2πfC )2 (L1 + L2 ) (33) ing to the CV-CC charging modes as required by the battery
charging profile (Fig. 5). The battery voltage (Vbatt ) is sensed
where from the output and compared with a reference voltage (V∗ batt ),
fline < fC < fS (34) and produces an error voltage (Verr ), which when fed to a PI
controller generates the reference battery current (I∗ batt ). The
Therefore, selecting fC equal to 4 kHz, the C1 is calculated
mathematical equations corresponding to the operation of the
as,
  outer loop control for the jth sampling instant are expressed as;
C1 = 1 (2π × 4000)2 (40 + 150) × 10−6 = 8.33 μF ∗
Verr (j) = Vbatt (j) − Vbatt (j) (39)
(35) ∗ ∗
Finally, the C1 is selected as 8 μF. Ibatt (j) = Ibatt (j − 1) + σpv {Verr (j) − Verr (j − 1)}
+ σiv Verr (j) (40)
C. Design of CDC
The design of CDC ensures the reduction of second harmonic Where σ pv and σ iv correspond to the proportional controller
current that flows into the battery. Considering, 5% voltage gain and integral controller gain for the outer voltage control
ripples, the CDC is designed as [32], loop, respectively. This reference current in comparison with the
Prated actual battery current, generates an error signal, which when fed
CDC = 2 to the inner PI controller, generates a signal ‘me ’, corresponding
4πfline ϕVbatt(max)
to the duty ratio D1 .
450 The comparison of me with a saw-tooth carrier waveform
= = 5.52 mF (36) produces the required gating pulses for the S1 and S2 . The
4π × 50 × 0.025 × 722
simultaneous switching of S1 and S2 is proved advantageous
Finally, the CDC is chosen as 6.6 mF. from driving circuit simplicity point of view. The equations
corresponding to the inner loop control are given by;
D. Design of Lf and Cf ∗
Ierr (j) = Ibatt (j) − Ibatt (j) (41)
The undesirable high-frequency switching harmonics are at-
tenuated by using a low-pass LC filter at the output of the DBR. me (j) = me (j − 1) + σpi {Ierr (j) − Ierr (j − 1)}
The maximum value of Cf is obtained as [32], + σii Ierr (j) (42)
Prated tan θ 450 × tan(1)
Cf = = = 0.47 μF (37) Where σ pi and σ ii correspond to the proportional controller
2πfline VS2 2π × 50 × 2302 gain and integral controller gain for the inner current control
Where θ refers to the displacement angle between the funda- loop, respectively. Further, to obtain desired gain parameters for
mental value of input voltage and current. A lower value of Cf , both inner current loop and outer voltage loop controllers, the
equal to 0.45 μF, is chosen. The filter inductor Lf , is designed small signal modelling of the presented charger is carried out
selecting a filter cut-off frequency (fcf ) lower than the switching and presented as follows.

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4258 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO. 4, JULY/AUGUST 2023

Further, the average rate of change of voltage across CDC , is

obtained as,

dvCDC (t)TS −vbatt vC1 d21 TS i1 1
= − +1 + (i1 +i2 )
dt RC2 2L2 C2 i2 C2
(51)
Fig. 6. Control block diagram for small signal analysis. Likewise, the rate of change of inductor currents averaged
over a cycle is also derived, and given as,
di1 (t)T
 ⎫
vbatt ⎬
dt
S
= L1 + L1 + L1 − L1 d1 TS 1+ vC1
vin d1 2vC1 d1 vbatt d1 2L2 i2

= vC1 d1 + vbatt d1 − 2vbatt i2 ⎭

di2 (t)T
S
dt L2 L2 vC1 d1 TS
(52)
After deriving averaged equations during each switching cy-
cle, the state variables, i.e., i1 , i2 , vC1 , vCDC , d1 and vin , are
perturbed as given in (53), and substituted in (50)–(52), and
Fig. 7. Inductor L1 voltage (VL1 ) and current (I1 ) waveforms.
then linearized.
⎫
i1 = I1 + ĩi (t)⎪
A. Full-Order Small Signal Modelling of Presented Quadratic ⎬
i2 = I2 + ĩ2 (t) (53)
Buck-Boost AC-DC Converter Under DICM vC1 = VC1 + ṽC1 (t)⎪ ⎭
Initially, the derivation of plant transfer functions G1 (s) and vCDC = VCDC + ṽCDC (t)
G2 (s) (as shown in Fig. 6) under DICM operation is carried out The input control variables are also expressed in the same
and presented as follows. way, as in (53).
Notably, the full order modelling approach first considers 
the KVL and KCL equations within each switching cycle for vin = Vin + ṽin (t)
(54)
each energy storage device of the charger circuitry. Further, the d1 = D1 + d˜1 (t)
obtained state equations for each component in all the three In order to linearize the equations, the small-signal approxi-
modes are averaged, perturbed, and linearized. For example, in mation is applied by neglecting products of time-varying pertur-
case of C1, the total charge that flows into it in each interval of a bations. Finally, the AC part of the perturbed system of equations
switching cycle is determined and averaged, to obtain the total is represented by state equations as;
charging current. This is expressed as, ⎡ ⎤ ⎡ ⎤⎡ ⎤
  (d1 +d2 )TS  ĩi (t) A11 A12 A13 A14 ĩi (t)
1 d1 TS d ⎢ ĩ2 (t) ⎥ ⎢A21 A22 A23 A24 ⎥ ⎢ ĩ2 (t) ⎥
iC1 TS = [i1 (t) + i2 (t)] + [−i1 (t)] dt ⎣ ⎦ = ⎣A ⎦⎣ ⎦
TS 0 d1 TS
dt ṽC1 (t) 31 A32 A33 A34 ṽC1 (t)
ṽCDC (t) A41 A42 A43 A44 ṽ (t)
(43)   !   !  CDC  !
which in terms of the inductor peak currents i1(pk) and i2(pk) , is ẋ A x
expressed as, ⎡ ⎤ ⎡ ⎤
  B11 C11
1 1 1 ⎢B21 ⎥ ˜ ⎢C21 ⎥
iC1 TS = i1(pk) d1 + i2(pk) d1 − i1(pk) d2 +⎣ d (t) + ⎣ ⎦ ṽin (t)
B ⎦ 1
(55)
2 2 2 31 C 31
B41 C41
dvC1 (t)TS   !   !
= C1 (44) B C
dt
The peak and average values of i1 are shown in Fig. 7, and Where,

expressed as, −2L2 Vbatt
A11 = 0, A12 = 1+ ,
i1(pk) = (vin + vC1 )d1 TS /L1 (45) L1 T S D 1 VC1
i1(avg) = (1/2)(d1 + d2 )i1(pk) TS (46) 2D1 2L2 I2 Vbatt
A13 = + 2
In similar terms, peak and average values of i2 are expressed L1 L1 TS D1 VC1
as, D1 2L2 I2 −2Vbatt
A14 = − , A21 = 0, A22 = ,
i2(pk) = vC1 d1 TS /L2 (47) L1 L1 TS D1 VC1 VC1 D1 TS
i2(avg) = (1/2) (D1 + D2 )i2(pk) TS (48) A23 =
2Vbatt I2
+
D1
,
2 D T
VC1 L2
By rearranging the average inductor current i2(avg) obtained 1 S
after substitution of (47) in (48), the d2 is expressed as, D1 2I2 1 VC1 D12 TS
2i2 L2 A24 = − , A31 = − ,
d2 = − d1 (49) L2 VC1 D1 TS C1 C 1 L2 I 2
vC1 d1 TS
VC1 D12 I1 TS
Substitution of (45)–(48) in (44), the average expression for A32 = ,
(dvC1 (t)/dt) over a switching cycle is obtained as, C1 L2 I22

dvC1 (t)TS vC1 i1 d21 TS i1 vC1 d21 TS −D12 TS 1 I1
=− + − (50) A33 = + , A34 = 0,
dt i2 C 1 L 2 C1 2L2 C1 L2 C 1 2 I2

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KUMAR et al.: SINGLE-STAGE CHARGER FOR LEV BASED ON QUADRATIC BUCK-BOOST AC-DC CONVERTER TOPOLOGY 4259

The design and the selection of all components are done as per
Section IV. The battery voltage and charging current are sensed
using LEM’s voltage and current transducers, respectively. The
control of the charger is digitalized using TI’s TMS320F28377S
launchpad development kit. Finally, the performance of the
charger is validated under steady state and various dynamic
conditions, and the relevant test results are recorded using
Keysight’s’ 4-channel DSO and Fluke’s 1-φ PQ analyzer, and
discussed as follows.

A. Performance Analysis Under Steady State Condition

Under nominal operating conditions, i.e., Vs = 220V/50Hz,
Fig. 8. Test bench set-up for presented charger circuitry. and Vbatt = 48V, the performance characteristics of the charger
are verified, and shown in Fig. 9(a)–(c). As seen in Fig. 9(a), the
charger ensures unity power factor and low harmonic distortions
1 VC1 D12 TS
A41 = − , at AC mains while the average battery current (Ibatt ) is controlled
CDC 2L2 CDC I2 and maintained at 8 A. Even if, the charging current contains
 slow varying ripples due to the single-stage configuration of
1 VC1 D12 I1 TS −D12 TS I1
A42 = + , A43 = +1 , presented charger, these current ripples remain complied with
CDC 2L2 CDC I22 2L2 CDC I2
the NEMA PE5 standard, which demands a set boundary of 5 A
−1 current peak to peak ripple that is tolerable for a battery having
A44 = , 100Ah capacity, to ensure better battery life [33]. Moreover, the
RCDC
 voltage stress across the switching devices, i.e., S1 and S2 , which
Vin + 2VC1 + Vbatt 2L2 I2 Vbatt are operated simultaneously, are shown in Fig. 9(b), and across
B11 = + 1+ ,
L1 L1 TS D12 VC1 diodes, Da and Db are shown in Fig. 9(c). The voltage stresses
are found satisfactory, with the conduction of the devices inde-
VC1 + Vbatt 2Vbatt I2 −2D1 VC1 I1 TS
B21 = + 2 , B31 = pendent of the input voltage polarity. In addition, the continuous
L2 D1 VC1 TS C 1 L2 I 2 voltage conduction mode (CVCM) design of C1 is validated and
VC1 D1 TS shown in Fig. 9(b). Further, L1 and L2 , show the discontinuous
− , current behavior as designed, and it is seen that both inductor
L2 C 1
 currents cease to zero before the end of the switching period, as
−D1 VC1 TS I1 D1 shown in the zoomed-in waveforms of Fig. 9(c). It is noteworthy,
B41 = +1 , C11 = , C21 = 0, that the functioning of the charger presented in this work at
CDC L2 I2 L1
nominal conditions of operation is on par with the design, and
C31 = 0, C41 = 0 (56) satisfies the input side and load battery side demands, while
Based on this, the G1 (s) is obtained as; ensuring safe and reliable operation of the switches and devices.
 
˜ = [0 1 0 0] (sI − A)−1 B
G1 (s) = ĩ2 (s) d(s) (57)
B. Validation of RMS Current and Peak Voltage Expressions
Using the parameter values obtained earlier as, Vin = 207.07
The validity of the expressions given in Table I are analyzed
V, VC1 = 99.69 V, D1 = 0.2, Vbatt = 48 V, TS = 50 μs C1 = 8
theoretically and experimentally under different loading condi-
μF, C2 = 6.6 mF, L1 = 150 μH, L2 = 40 μH, I1 = 5.7 A, I2
tions and the results are summarized in Table II and Fig. 10(a)–
= 6.2 A. For a 450 W charger, the output resistance R, is taken
(c). The expressions derived in Table I, are analyzed at two
as 5.12 Ω. With these values, the transfer function of G1 (s) is
charging current conditions, i.e., at 9 A and 7.5 A, and at Vs =
obtained as,
220V(RMS), and nominal Vbatt = 48V and the results obtained
8.78×106 s3 +4.47×1013 s2 +2.28×1018 s+1.9×1022
G1 (s) = s4 +1.03×105 s3 +3.7×1011 s2 +2.45×1016 s+1.1×1020
(58) are tabulated in Table II. Notably, the actual value of different
voltages and currents is closely match with the theoretical value,
Further, the G2 (s) is obtained as effective output impedance
and thus, confirms the validity of the expressions given in Table I.
of the charger.
Although, the theoretical value of S1 and Da voltage stresses
G2 (s) = R(s + 1/RC)/s = (5.12s + 100)/s (59) are same, their actual value differs, because, during theoretical
Finally, by considering G1 (s) and G2 (s), the controller gains analysis the input voltage to the converter is assumed as constant
for the inner current and outer voltage loop are derived and the (Vin ). However, in actual condition, the input voltage to the
control of the entire charging circuitry is digitalized to imple- converter, i.e, the voltage across Cf , varies between its peak and
ment the efficacious battery pack charging, over an extended lower value within a switching cycle (as shown in Fig. 10(a)).
range of operating conditions. Therefore, the component of Vcf that adds to the voltage stress
across S1 and Da , i.e., at t = (D1 +D2 )TS for S1 and t = 0 for
Da , have wide difference. The difference in Vcf at two instances,
VI. RESULTS AND DISCUSSION causes the difference in actual value of voltage stress across
A proof-of-concept test bench prototyping of presented AC- S1 and Da and the same is reflected in Table II. Further, the
DC converter, which is based on single-stage quadratic voltage experimental results pertaining to the validity of the expressions
gain buck-boost topology, is realized in the laboratory environ- given in Table I, are analyzed at Ibatt = 7.5A and showcased in
ment. The photograph of the test bench set-up is shown in Fig. 8. Fig. 10(b) and (c). It is noteworthy that the experimental value (as
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4260
Fig. 9. Performance of presented single-stage charger under nominal operating conditions (a) VS, IS , Vbatt , Ibatt (b) VS , VS1 , VS2 , VC1 in line frequency range
and zoomed-in waveforms in switching frequency range. (c) VDa , VDb , I1 , I2 in line frequency range and zoomed-in waveforms in switching frequency range.
Fig. 10. (a) Vcf , VC1 , VS1 and VDa waveforms and their peak values, experimental results of (a) IS1 , IDa , IDb and IS2 (b) IL1 , IL2 and IC1 obtained for 7.5 A
battery charging current.
TABLE II
VOLTAGE/CURRENT AVERAGE/RMS VALUES FOR EACH COMPONENT OF
CHARGER CONFIGURATION
shown in Fig. 10(b) and (c)) closely matches with the calculated
value and have slight difference due to the difference in the
actual Vbatt , and Vs conditions, which causes variations in the
duty ratio in the actual hardware, and causes the difference.
C. Performance Analysis Under Dynamic Conditions
Performances of the charger under dynamic conditions of in-
creased and decreased supply voltage (Vs ) fluctuations, and also
for increased and decreased Ibatt variation (from half of rated
charging current to rated value and vice-versa) are validated
and discussed in this section. Further, the relevant results are
depicted in Fig. 11(a)–(d). As shown in Fig. 11(a), the Vs is made
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO. 4, JULY/AUGUST 2023
to fluctuate suddenly from 220 V to 265 V (RMS), and corre-
spondingly it is seen that the Is decreases in order to maintain the
input power constant, while keeping Ibatt undisturbed. Similar
effects are also seen for decreased Vs variations, when the Vs
is decreased from 220 V to 160 V (RMS) (refer to Fig. 11(b)),
with the Is increasing in this case, keeping the power delivered
to the battery at a constant level. Test results demonstrating
performance of presented charger under increased and decreased
Ibatt variations, are shown in Fig. 11(c) and (d), respectively. It is
seen that the increase in Ibatt from half rated current to the rated
value causes the supply current IS to correspondingly increase,
in order to provide for the power balance as seen from Fig. 11(c).
In similar terms, it is also seen that, the Is decreases for a decrease
in Ibatt from rated current to half the rated current, without any
overshoot or undershoot, in both cases.
Here it is noticeable that, even if, the presented charger is sub-
jected to various dynamic conditions, it holds unity power factor
and limited harmonics distortions at AC mains and excellently
regulates Ibatt at the desired level. Thus, the performance of the
charger was found satisfactory.
D. Power Quality (PQ) Analysis at Supply Side
The PQ aspects of the presented charger at the input side, are
analyzed in this section, for nominal, increased and decreased
Vs levels, and the results obtained are shown in Fig. 12(a)–(i).
It is evident from these results that in all the three cases, the
displacement angle between the Is and Vs is maintained at
almost zero, and the harmonic distortions in Is are held at
3% (refer to Fig. 12(c)), 2.4% (refer to Fig. 12(f)) and 1.7%
(refer to Fig. 12(i)) for 217 V, 254 V and 163 V AC mains
conditions, respectively, which is well below the benchmarks
set by IEEE-519 and IEC 61000-3-2 standards [34]. Further,
curve of efficiency with respect to different loading, is shown in
Fig. 13. It is seen that, the efficiency attains peak at Vs = 255
V(RMS), whereas, the conversion losses are maximum at Vs =
KUMAR et al.: SINGLE-STAGE CHARGER FOR LEV BASED ON QUADRATIC BUCK-BOOST AC-DC CONVERTER TOPOLOGY
Fig. 11. Performance of the charger, (a)–(b) under Vs dynamics (a) increased, and (b) decreased Vs fluctuations, (c)–(d) with charging current varying from
(c) 50–100% (d) 100%-50%.
Fig. 12. PQ indices, i.e.,VS , IS , power factor, THD, displacement power factor,
active and reactive powers at AC mains of the presented charger topology during
RMS voltages (i) 216 V (a-c) (ii) 253.8 V (d-f) (iii) 163 V (g-i).
Fig. 13. Efficiency v/s load power at different supply voltage levels.
160 V(RMS) condition. Notably, the presented system exhibits
satisfactory efficiency over wide range of operating conditions,
and thus, seems suited for LEVs BCs.
E. Loss Breakdown of Presented Charger
The power loss breakdown and efficiency of the presented
charging system at its peak efficiency operating conditions, i.e.,
P = 250 W, Vs = 255 V RMS, and Vbatt = 72 V, are analyzed and
summarized in this section. Initially, the average/RMS values
of voltage/current across/through passive components of the
presented charger (calculated using the expressions in Table I) at
the defined operating condition, and given in Table III. Further,
the values of each parameters, that contribute to the component
losses, obtained from standard datasheets and measurements,
are given as follows; DBR diode resistance (rT ) = 3 mΩ, DBR
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4261
TABLE III
CHARGER COMPONENTS VOLTAGE/CURRENT AVERAGE/RMS VALUES
diode forward voltage (VTO ) = 1.1 V, S1 / S2 ON-state forward
voltage (VCE ) = 0.85 V, S1 / S2 ON-state resistance (rCE ) =
3 mΩ, Rise-time of S1 / S2 (trise ) = 30 ns, Fall-Time of S1 /
S2 (tfall ) = 50 ns, Da / Db forward voltage drop (VFO ) = 0.4
V, ESR of C1 (ESRC1 ) = 2 mΩ, ESR of CDC (ESRCDC ) = 10
mΩ, resistance of L1 (rL1 ) = 50 mΩ, resistance of L2 (rL2 ) =
30 mΩ, resistance of Cf (rCf ) = 2 mΩ, resistance of Lf (rLf )
= 200 mΩ. Based on these values, the losses associated with
major components of the presented charger, are calculated and
given in Table IV. Therefore, at defined operating conditions, the
theoretical peak efficiency of the presented charger is obtained
around 95%. However, the peak efficiency obtained using the
same conditions in the proof-of-concept hardware is obtained
nearly around 94.5%.
F. Comparative Analysis With Existing Topologies
In this section, a comprehensive comparison of presented
charger with existing charger configurations is carried out, and
presented in Table V. In [22], a single-stage configuration with
a cascaded combination of a buck-boost cell and a quadratic
buck cell, is presented. This topology has wide step-down gain,
with reduced control complexity, with DICM operation of induc-
tors and single switch control. However, the increased device
count, which consists of the increased magnetic components
and diodes, compromises the cost, size, and efficiency of the
overall configuration. Further, the topologies given in [35] and
[36], use an interleaved boost converter at the frontend for PFC,
and isolated full bridge and isolated full bridge with LLC in
the backend, respectively. Even if, the boost PFC provides the
required PQ indices at the input side, the implementation of
the topology in two- stage and the use of a transformer in both
the topologies impact on the conversion efficiency, volume, and
4262 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO. 4, JULY/AUGUST 2023
TABLE IV
BREAKDOWN OF LOSSES ASSOCIATED WITH CHARGER CONFIGURATIONS
TABLE V
COMPARISON OF PRESENTED CHARGER TOPOLOGY WITH OTHER EXISTING BATTERY CHARGERS
cost of the overall charging system. Moreover, the requirement
of a supply voltage sensing circuitry for current shaping further
adds to the control complexity, along with increased component
count and size of magnetic components, due to the design
of the magnetic components in CICM. The charger in [37]
has a lower device count, including the magnetic components,
switches and diodes. Moreover, the operation of the charger
in DICM, improves the control simplicity of the charger by
incorporating inherent power factor correction, thus reducing
the sensing circuitry, reducing the size of magnetic components.
However, the use of a step-down transformer increases the size.
The leakage reactance of the windings further increases voltage
stress across the switches, and hence devices with higher ratings
would have to be used.
From the above-mentioned comparative analysis, it is evident
that the charger presented has advantages in terms of reduction
in control complexity, single-stage transformerless power
architecture, inherent power factor correction, reduction in
the size of magnetic components, and wide operating range
capability, and therefore, is found to be appropriate for LEVs
charging applications.
VII. CONCLUSION
A single-stage charger based on a quadratic buck-boost AC-
DC converter has been presented for the charging application
targeted for LEVs. Unlike conventional approaches, a trans-
formerless approach has been realized to carry out effective
charging of LEVs over a wide range of operating conditions.
With a transformerless structure, the presented charger has
ensured better conversion efficiency, low cost, and size, and
therefore, seems best suited for low-cost low power charger
applications, specifically, LEVs battery charger applications.
Further, the DICM design of magnetic components, has facil-
itated intrinsic unity power factor operation at the supply AC
mains, which has in turn simplified the control approach of
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the presented charger and has also reduced associated control
implementation cost. Further, zero current switching of semi-
conductor devices and low volume of magnetic components
have also been achieved through DICM design of the charger. A
comprehensive theoretical analysis of presented quadratic buck-
boost AC-DC converter including its operating principle, design
guidelines and component selection procedure, and realization
of control architecture, has been carried out. Finally, the overall
performance of the charger topology has been validated through
proof of concept test bench prototyping, and relevant results
under various operating conditions have been analyzed in detail.
The charger has shown satisfactory operation with improved
PQ indices at AC mains, while maintaining a desired and good
battery charging profile, and thus, seems best suited for low cost,
simple, compact, and efficient LEV charging applications.
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Aswin Dilip Kumar received the B.Tech. degree in
electrical engineering from the College of Engineer-
ing Trivandrum, Thiruvananthapuram, India, in 2020.
He is currently working toward the M.S. (Research)
degree in power electronics with the Indian Institute
of Technology Delhi (IIT Delhi), New Delhi, India.
His research interests include electric vehicle battery
chargers, design and control of AC-DC converters and
DC-DC converters, high-frequency magnetic design,
power quality improvement, and power electronics.
Jitendra Gupta (Member, IEEE) received the B.E.
degree in electrical and electronics engineering from
the Lakshmi Narain College of Technology, Bhopal,
India, in 2015, and the M.E. degree in power electron-
ics from SGSITS, Indore, India, in 2017. He is cur-
rently working toward the Ph.D. degree in power elec-
tronics with the Department of Electrical Engineer-
ing, Indian Institute of Technology (IIT) Delhi, New
Delhi, India. His research interests include electric
vehicle battery chargers, power factor correction, DC-
DC converters, AC-DC converters, high frequency
magnetic design, power quality, and power electronics.
Bhim Singh (Fellow, IEEE) received the B.E. degree
in electrical from the University of Roorkee (Now IIT
Roorkee), Roorkee, India, in 1977, and the M.Tech.
degree in power apparatus and systems and the Ph.D.
degree from IIT Delhi, New Delhi, India, in 1979 and
1983, respectively. In 1983, he was a Lecturer the
Department of Electrical Engineering, University of
Roorkee, where he became a Reader in 1988. In 1990,
he joined the Department of Electrical Engineering,
IIT Delhi, as an Assistant Professor, where he has be-
come an Associate Professor in 1994 and a Professor
in 1997. From 2007 to 2012, he was a ABB Chair Professor. From 2014 to 2016,
he was the Head of the Department of Electrical Engineering, IIT Delhi. From
2016 to 2019, he was the Dean, Academics, IIT Delhi. From 2015 to 2021, he
was a JC Bose Fellow of DST. Since 2021, he has been the SERB National
Science Chair Professor with IIT Delhi. Prof. Singh has guided 114 Ph.D.
dissertations, and 176 M.E./M.Tech./M.S.(R) theses. He has filed 105 patents.
He has executed ninety sponsored and consultancy projects. He has co-authored
a textbook on power quality: Power Quality Problems and Mitigation Techniques
published by John Wiley & Sons Ltd. 2015. His research interests include solar
PV grid interface systems, microgrids, power quality mitigation, solar PV water
pumping, improved power quality AC-DC converters, and electric vehicles.