Received: 17 May 2020 Revised: 11 August 2020 Accepted: 11 September 2020 IET Power Electronics

DOI: 10.1049/pel2.12016

ORIGINAL RESEARCH PAPER

A high-power quality battery charger for light electric vehicle using

switched inductor PFC converter

Radha Kushwaha Bhim Singh

Electrical Engineering, Indian Institute of Abstract

Technology Delhi, New Delhi, India
Correspondence
Radha Kushwaha, Electrical Engineering, Indian
Institute of Technology Delhi, New Delhi, India.
Email: eez158091@ee.iitd.ac.in
This work is focused on a new power quality improved battery charger for electric vehicle
using a two switch power factor correction (PFC) single-ended primary inductance con-
verter (SEPIC) at the front-end followed by a flyback converter. The single-ended primary
inductance converter is a high step-up PFC converter with a switched inductor configu-
ration at the input. Over a conventional single-ended primary inductance converter, this
new configuration operates with reduced duty ratio for a given DC-link voltage. By using
few additional components, this new single-ended primary inductance converter offers
reduced switch voltage stress to produce the same DC-link voltage. The operation at lower
duty cycle, gives the improved efficiency over a conventional SEPIC PFC converter. The
built-in advantage of soft switching in devices, is achieved due to discontinuous conduction
mode based design for both power factor correction converter and flyback converter. The
power quality improvement in charger is validated at steady state as well as under variation
in input voltage and DC-link voltage, to meet the IEC 61000-3-2 regulations. Performance
of this charger is verified in constant current mode with high step-up gain of power factor
correction converter and lower stress across the devices over a conventional single-ended
primary inductance configuration.

1 INTRODUCTION
The current situation of constant growth in hazardous carbon
emission and a low energy requirement for conventional cars
have led to the adoption of electric fleet on wider platform [1,
2]. The electric fleet has offered the obvious advantages over the
gasoline vehicle by reserving the conventional fuel and reducing
the air pollution. However, due to grid resilience, the deploy-
ment of these electric vehicles (EVs) into transport sector seeks
research effort to control improved power quality (PQ) opera-
tion. Moreover, to power these vehicles, advanced battery tech-
nology such as lead acid and Li-ion mechanism are available at
attractive prices. The electric vehicle battery chargers (EVBCs)
are the main element to charge these batteries, which affects
the quality of grid current [3]. The rich content of harmonics in
grid current, violates the recommended regulations [4] for unity
power factor (UPF) operation. Apart from improved PQ, an
off-board EVBC circuit should follow the objective of high effi-
ciency and density to follow the Society for Automotive Engi-
neers (SAE) standard [5]. A lot of research efforts have been
made in the literature for UPF operation of these EVBC cir-
cuits using power factor correction (PFC) converters.
The most general circuit of an EVBC consists PFC stage for
AC–DC conversion, preferably, either with boost or buck-boost
PFC converter at the input and an isolated converter to regulate
the battery side quantities. The simple structure and number of
components of DC–DC converter also have an impact on the
charger size and efficiency. As discussed in [6], an LLC resonant
converter is the appropriate choice compared to one switch iso-
lated DC-DC converters due to low electromagnetic interfer-
ence (EMI) noise, high efficiency and improved power density.
For PFC at first stage, a buck-boost converter [7] is preferable
than the boost converter [8], as an attractive range of duty ratio
is available. The use of inductor–inductor–capacitor (LLC) con-
verter at next stage, limits its efficiency for two stage configura-
tions. The reason behind this, is the fluctuations in operating
frequency of resonant converter over the change in input volt-
age. On the other hand, a high switch voltage stress is achieved

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properly cited.
© 2020 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology

120 wileyonlinelibrary.com/iet-pel IET Power Electron. 2021;14:120–131.


KUSHWAHA AND SINGH
in buck-boost converter due to pulsations in the input current.
Therefore, a device with higher voltage and current rating, is
needed for these converters. The conventional buck-boost con-
verters employing high rating devices show up with the follow-
ing demerits: (i) Switches with higher voltage and current rating
cause an increase in magnetic component size as well as more
losses as the peak current stress is higher at the input. (ii) Higher
rating devices give an increase in switch voltage stress during
operation. Based on this voltage rating, the switch on-state resis-
tance varies, which further causes an increase in the switch con-
duction loss. (iii) Moreover, conventional converters also oper-
ate at higher duty ratio as compared to high gain converters,
which gives high parasitic losses in the circuit with increased
switch voltage. (iv) A major part of reverse recovery losses is
observed in hard switched converters.
To solve these issues, novel topologies with coupled
inductors-based configurations have been reported in [9–12],
which overcome the switch stress limitations. However, the
need of an isolation transformer for these coupled inductor
structure limits its application for high density EV chargers.
Lu et al [13] have reported an integrated converter with boost-
forward PFC configuration. In order to minimize the current
stress, this converter operates during two separate conducting
intervals of line current. At the same time, a cascaded peak
current controller clamps the switch voltage to the bus voltage
level. The switch voltage stress in most of conventional buck-
boost configurations is the addition of supply voltage and DC-
link voltage.
One way to reduce the device voltage stress is to operate
this PFC converter at lower input voltage providing the same
DC-link voltage and power rating [14]. Therefore, to reduce
the device stress on a conventional EV charger, conventional
buck-boost converters can be replaced with high step-up gain
converters. These high step-up gain converters have ability to
operate at reduced duty cycle, therefore, same DC-link volt-
age is achieved with lower input voltage. Several high step-up
gain converters based on high frequency isolation transformer,
are reported in the literature [15, 16]. By selecting an appro-
priate transformation ratio, the required output voltage can be
achieved but it increases the converter cost, volume and size.
Moreover, a perfect design of the transformer leakage induc-
tance is required to suppress the additional switch voltage stress
during switch OFF time. The use of coupled inductor also
plays major role in reducing the switch voltage [17, 18]. How-
ever, despite easy design of inductances, the voltage spikes still
appear across the devices in these converters. Among different
buck-boost configurations, conventional SEPIC converter [19],
as shown in Figure 1, is quite popular for EV charging.
The conventional converter offers step down and step-up
feature with positive polarity. A low current ripple is achieved
at input, as high ripple affects the performance of the converter
with the distorted mains current. As discussed earlier, the volt-
age across the device in a SEPIC converter is an addition of
input voltage and DC-link voltage. To reduce the device stress
and an increase in the efficiency, several techniques with high
step-up gain SEPIC configurations, are presented in [20, 21].
However, the voltage gain of these converter, is still low and
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121
FIGURE 1 Architecture of EV chargers with conventional SEPIC
converter
this voltage boost is provided with additional large number of
components.
Several high voltage gain topologies based on soft switched
SEPIC PFC converter are presented in [22–26] for renewable
applications. However, it is seen that soft switching technique
needs complex circuit arrangement with additional inductor and
capacitors in the circuit. This restricts the goal of high-power
density and efficiency of battery chargers, as prescribed by the
standard. Many single stage single switch topologies based on
integrated SEPIC with LLC converter, flyback converter and
valley fill circuit, are discussed in the literature [27–29], which
are useful for EV charger. However, all these single stage solu-
tions suffer from high voltage and current stress through the
PFC device. Therefore, two stage EV chargers are quite popu-
lar these days to provide high reliability and low switch voltage
stress on devices of front-end PFC converter with the use of
high gain PFC converters.
An improved EV charger based on non-isolated switched
inductor SEPIC PFC converter followed by a flyback converter,
is discussed in this paper. A comparative analysis of this new
SEPIC converter over different high gain PFC converters is
given in Table 1. The highlights of this work are enlisted as
follows.
(i) A new high gain SEPIC converter is derived with conven-
tional SEPIC converter by incorporating switched inductor
(SI) configuration at the input. The addition of some auxil-
iary components (1 diode, and 1 capacitor) helps in achiev-
ing higher step-up gain than other conventional buck-boost
configurations and the topology in [15].
(ii) As derived later in (11), the voltage gain of this new SEPIC
converter, is obtained as (3D + 1)/(1 − D), where D is
the converter duty ratio. Therefore, the required DC-link
voltage is achievable with lower input voltage.
(iii) The operation of this converter at lower input voltage
gives reduced voltage stresses on PFC switches, than that
obtained with a conventional SEPIC converter. Therefore,
the charger cost is seen to be significantly low as it allows
the use of small rating devices.
(iv) Low device stress lets the use of switch with low on
state resistance, which reduces the cost of the switch and
charger, along with improving the efficiency.
(v) High voltage gain enables the converter to produce the
given DC-link voltage at lower duty ratio, which helps in
achieving low switch conduction loss.
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122 KUSHWAHA AND SINGH

(1 − D)

(1 − D)
Proposed

3D + 1/
Vsm /

2
3

3
1 + n(2 − D)/
(1 + n(2 −

(1 − D)
D))
Vo /
[21]

3
3

1
(1 − D)

(1 − D)
2(n + 1)/
Vsm /
[20]

FIGURE 2 Configuration of improved EVBC circuit with SI SEPIC con-

2

3
2

1
verter at front-end
(1 + 2n−nD)/
2(n + 1)

(1 − D)
Vo /
[19]

(vi) The control of improved converter is easy to implement as

2

4
3

similar pulses are given to both the switches.

Vo + Vsm (n + 1)/
(1 − D)(2 + n)

(1 + D + nD)/

The design of both the converters, is selected in discontin-

(1 − D)2

uous conduction mode (DCM), which inherently achieves the

zero-current switching of fast diodes and PFC switches. A test
[18]

set-up for this new charger, is developed for 600 W rating to

1

4
4

provide a 70.7 V AC to 300 V DC step-up conversion. This

high gain SEPIC converter cascades a flyback converter, which
(1 − D)

(1 − D)

facilitates the required current during constant current (CC) and

(1 + 2n)/

constant voltage (CV) charging regions. The performance vali-

Vsm /
[17]
Comparison between proposed converter and previously developed high gain PFC converters

dation of this charger with new SEPIC converter, is carried out

2

3
3

during steady state as well as over transients in input voltage

Vsm (M + n + 1)/

and DC-link voltage. A reduced stress on switches as well as an

(n + 2) + (n +

improved PF based charging is achieved, as per the IEC 61000-

(2n + 1)

(1 − D)

3-2 regulation.
1)D/
[16]

4
4

2 CIRCUIT CONFIGURATION AND

OPERATION
(2 + n + D)/
(1 − D)

(1 − D)

The circuit of presented charger with new step-up gain SEPIC

Vsm /
[15]

PFC converter is shown in Figure 2. The SEPIC PFC con-

1

4
5

verter is used for enhanced PQ feature at front-end and a

flyback converter facilitates the required current for constant
(1 − D)

(1 − D)

current-constant voltage regions. The configuration of this new

(1 + D)/

SEPIC converter for high voltage gain, is achieved with few

Vsm /
[13]

additional components in a conventional SEPIC converter. The

1

2
3

new SEPIC converter consists of a switched inductor configu-

ration at the input, which steps-up the PFC converter voltage
(2 + D)

(1 − D)
(2 + D)/

gain. The output voltage of SEPIC converter, which is regu-

Vo /
[12]

lated at 300 V, can be achieved at lower duty cycle as compared

2

4
5

to the conventional SEPIC converter. Both the converters are

designed to select the charger operation in DCM. DCM design
Number of diodes

inherently achieves soft-switching along with the fewer sensors

Voltage stress

capacitors
across the

inductors

in the circuit. Due to less sensing requirement, control imple-

Number of

Number of

Number of
switches

switches
Attributes

Static gain
TABLE 1

mentation is easy and, it helps in overall cost reduction. The

modes of operation, design and analysis of SEPIC converter as
well as the flyback converter, are discussed as follows.
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KUSHWAHA AND SINGH 123

FIGURE 3 Operation of PFC switched inductor converter based on

switch ON, OFF and DCM duration. (a) Stage -I. (b) Stage-II. (c) Stage –III

2.1 Operation of high gain SEPIC converter

The new SEPIC converter consists of a switched inductor con-
figuration at input with two switches Sm and Sa , as well as two
input inductors Lm and La . The intermediate transfer capac-
itor Cs , output inductor Lo , and the main output diode Dom
work in the similar way as in a conventional SEPIC converter.
An additional intermediate transfer capacitor Ca and the auxil-
iary diode Doa are used to further provide high step-up char-
acteristics to this converter. The inductance Lo is designed for
discontinuous current over one switching cycle Ts . Different
operating stages of SEPIC converter are analysed and discussed,
as follows.
Stage 1 (t1 -t2 ): Stage-I begins at the instant t1 , when the two
switches Sm and Sa are turned ON simultaneously, as shown in
Figure 3(a). The currents through the inductances Lm and La
increase with the slope shown in Figure 4. The capacitors Cs
and Ca start discharging through the switch Sm , Sa via the induc-
tances Lm,a and Lo . The main and auxiliary diodes, Dom and
Doa remain in reverse bias. Assuming Lm = La = L, the expres-
sions for the input inductor voltages (vLm , vLa ) and the inductor
voltage vLo, are written as follows.
FIGURE 4 Key waveforms of charger with SI SEPIC converter based
charger over a switching cycle
Where, Vsm is the peak input voltage, iLm,a , iLo are currents
through the inductances Lm,a , Lo , and VCs , VCa are the volt-
ages across capacitances Cs and Ca . This stage lasts until the
instant t2 , when pulses to the switches are turned OFF.
Stage 2 (t2 -t3 ): During this mode, both switches Sm and Sa are
in OFF-state. As shown in Figures 3(b) and 4, the energy stored
in inductances, Lm and La is transferred to the load through the
main diode Dom via capacitor Cs . Moreover, the energy is trans-
ferred to a capacitor Ca using the auxiliary diode Doa . During
same instant, the energy in inductance Lo is released through a
diode Dom . Expressions for three inductors voltages are written
as,
Vsm − Vo + VCs d iLm,a
vLm = vLa = = Lm,a (3)
2 dt

d iLm,a d iLo
vLm = vLa = Vsm = Lm,a (1) vLo = Lo = −VCs (4)
dt dt

d iLo where, Vo is the voltages across the DC-link capacitor, Co . This

vLo = Lo = Vsm − VCs + VCa (2) mode lasts until the instant t3 .
dt
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124 KUSHWAHA AND SINGH

Stage 3 (t3 -t4 ): This stage is known as DCM or freewheeling operating principle of a flyback converter during three different
period, as both switches remain turned OFF during this instant. stages, is explained as follows.
The currents iLm,a and iLo freewheel through path shown in During Stage 1, a device Sf is turned ON. At this instant, the
Figure 3(c), such as the currents through diodes Dom and Doa magnetizing current rises at a linear rate and the energy is stored
become zero, as shown in Figure 4. Using KVL for the path in the inductance Lf from the supply. The diode Df at the sec-
enclosed by Vsm , Lm , Cs , Lo , Ca and La , the voltage expres- ondary is in OFF state, which implies that no energy is given to
sions are written as, the secondary side. The output current to the battery is given by
a capacitor Cch .
−Vsm + vLm − VCs − vLo + VCa + vLa = 0 (5) Stage 2 starts when a switch Sf is made OFF. The voltage
across the primary winding collapses and positive voltage is
During steady state, the inductor voltages vLm,a , and vLo are achieved across the secondary side rectifier, Df . The energy of
considered to be zero, therefore, (5) is rewritten as, the inductance, Lf flows to provide the required battery current
via the diode Df .
Vsm = VCa − VCs (6) During Stage 3, none of devices conduct and converter enters
DCM. At this instant, the stored energy of the magnetizing
The voltages across the input and output inductance given in inductance is completely exhausted. The battery current is facil-
Equations (1)–(4) are equated for the converter duty cycle D, itated through the output capacitor Cch .
over one switching cycle Ts , as,
3 DESIGN CONSIDERATIONS
⎛ DTs Ts
(Vsm − Vo + VCs ) ⎞⎟
1 ⎜
Vsm dt + dt = 0 (7) The SI SEPIC PFC converter is designed in DCM so as the out-
Ts ⎜ ∫ ∫ 2 ⎟
⎝0 DTs ⎠ put inductor current, iLo becomes discontinuous over a switch-
ing interval. The expression of the instantaneous source voltage,
⎛ DTs Ts
⎞ is written as,
1 ⎜
(Vsm + VCa − VCs )dt + (−VCs )dt ⎟ = 0 (8) √ √
Ts ⎜ ∫ ∫ ⎟
⎝0 DTs ⎠ vs (t ) = Vs 2 sin(2𝜋 ft ) = 70.7 2 sin(2𝜋50t ) (12)

The voltages across capacitors Cs , and Ca are obtained by where, Vs and f are the rms supply voltage and supply frequency
substituting Equation (6) into Equations (7) and (8), as, (Hz). Using (11), the relation between the DC voltage Vo and
peak input voltage Vsm is expressed as,
2D
VCs = V (9)
(1 − D ) sm 3D + 1
Vo = V (13)
( ) (1 − D ) sm
1+D
VCa = Vsm (10)
1−D Rearranging (11), to achieve the required voltage of 300 V at
the SI SEPIC converter output, the expression for the duty ratio
To obtain the high voltage gain MH for new SEPIC converter, calculation is given as,
putting the value of VCs from Equation (9) into Equation (7) as,
Vo − Vsm
3D + 1 D= (14)
Vo
= = MH (11) Vo + 3Vsm
Vsm (1 − D )
Substituting the rated source rms voltage of 70.7 V (Vs ), and
It is obvious that the voltage gain of this new converter is for sudden perturbations from 55 V (Vsmin ) to 95 V (Vsmax ),
higher than the conventional buck-boost based configurations respectively, the range of duty cycle is obtained as 0.43 (Dmax ) to
and the configuration reported in [15]. Moreover, this step-up 0.23 (Dmin ) with nominal duty ratio of 0.33 (D). Using Equation
in gain is achieved in this work by using minimal number of (14), it is seen that to achieve the same DC-link voltage of 300 V
components than the earlier topologies in the literature. at the PFC converter output, this SI SPEIC converter operates
at reduced duty cycle than a conventional SEPIC converter, for
which expression for the duty cycle is written as,
2.2 Flyback converter operation
Vo − Vsm
D= (15)
The flyback converter operates same as in conventional man- Vo + Vsm
ner to facilitate the battery current in constant current (CC)
and constant voltage (CV) charging regions. The design of the Therefore, PFC converter operation at reduced duty cycle
isolated stage is achieved in DCM, such as the magnetizing ensures the low switch conduction loss and improves the effi-
inductor current is discontinuous over a switching duration. The ciency over the conventional SEPIC converter.
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KUSHWAHA AND SINGH 125

The maximum ripple in the inductances Lm and La occurs at

the minimum source voltage,Vsmin . Therefore, using Equation
(1), the design expression of inductances Lm and La for contin-
uous operation is achieved as:
( )
Vs min D Rin Dmax Vs min 2 Dmax
Lm,a = = =
𝜆iLm,a fs 𝜆 fs Pi 𝜆 fs
( 2
) √ (16)
Vs min 1 Vo −Vs min 2
= √
Pi 𝜆 fs Vo +3Vs min 2

Where, λ is permissible input current ripple, fs is switching fre-

quency and Rin is emulated input resistance. FIGURE 5 Profile of battery charger in CC-CV mode with SI SEPIC con-
The maximum ripple across capacitances Cs and Ca occurs verter at front-end
at maximum source voltage, Vsmax . For an allowable percent
voltage ripple of κ, transfer capacitors Cs , Ca (Cs = Ca = C), inductance is given as,
are designed using the expression given as,
1
Lf = (21)
Cs (= Ca ) = √
Vo
√
Vo
4𝜋2 fc 2Cf
𝜅 2Vs max fs (Vo 2 ∕Pi ) 2Vs max +Vo
(17)
Pi To provide CC–CV charging to a 48 V, 100 Ah battery, the
= √ √
𝜅 2Vs max fs ( 2Vs max +Vo ) charger output at flyback stage, is controlled at 65 V. The trans-
formation ratio (n) of flyback converter is assumed as 1/3 such
The voltage across the inductance Lo is observed to be 2Vsm , as the required output is achieved from 300 V DC-link voltage.
during stage-I. Considering a permissible ripple of twice the To achieve converter duty cycle Do, the input and output volt-
DC-link current, and using (2), the expression for the design ages of flyback converter are correlated as,
of Lo in DCM is achieved as,
( ) Vch =
nDo
V (22)
2Vsm D Rin Dmax Vs min 2 Dmax 1 − Do o
Lo = = = Lo
2iLo fs fs Pi fs
( ) (18) Where, Vch is the charger output voltage. As per Equa-
Vs min 2 1 Vo −Vs min
= tion (22), duty ratio for providing intrinsic ZCS to diode Df ,
Pi fs Vo +3Vs min
comes out to be 0.394. As shown in Figure 5, with respect to
SOC (State of Charge). The critical value of inductance Lpri , to
The design of a capacitance, Co is achieved for minimiz-
achieve DCM operation, is given as,
ing second harmonics ripple in DC-link current such as a bat-
tery current is more uniform at the output. Considering Δ
as a voltage ripple, design expression for a capacitance Co is (Vo Do )2
Lpri,c ≤ (23)
given as, 2Vch Ich fsw

Io (Pi ∕Vo ) Pi where, converter switching frequency (fsw ) is used as 50 kHz.

Co = = = (19) For providing rated power output in CC–CV mode and con-
2𝜔ΔVo 2𝜔ΔVo 2𝜔ΔVo 2
sidering 0.1% ripple in battery voltage, the capacitor (Cch ) is cal-
culated as,
Where, ω is the frequency of supply voltage in rad/s.
To limit the reflection of high frequency harmonics to DoVch
source side, an EMI L-C filter is used. The design expres- Cch = (24)
sion for maximum value of input capacitor filter is estimated fsw (Vch 2 ∕Pi )ΔVch
as,
Table 2 shows the specification of proposed charger and the
√ calculated values of above components of high gain SEPIC con-
Im (Po 2∕Vs )
C f << C f max , C f max = tan 𝜃 = √ tan 𝜃 verter as well as flyback converter are given in Table 3.
𝜔Vm (𝜔 2Vs )
(20)
where, θ = displacement angle of source current measured 4 CONTROL OF EV CHARGER
with respect to the fundamental mains voltage. To minimize
switching harmonics, filter cut-off frequency is selected as The proposed charger control is explained under two categories,
1/10th of the switching frequency of the converter, i.e. 5 kHz. as (i) SI SEPIC converter control and (ii) flyback converter con-
Now, at the tuned value of cut-off frequency fc , the input filter trol, which is discussed as follows.
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126 KUSHWAHA AND SINGH

TABLE 2 Specification of charger with SI SEPIC converter

S. No. Specifications Switched inductor SEPIC converter Flyback converter

1. Input voltage 70.7 V, Single phase AC 300 V,DC

2. Output voltage/current 300 V/2 A 65 V/10.83 A
3. Switching frequency 20 kHz 50 kHz
4. Output power 600 W
5. Battery rating 48 V/100 Ah
6. Percent current ripple in inductor, Lm,a (λ) 10%
7. Percent voltage ripple in transfer capacitor (κ) 10%
8. Percent voltage ripple in the capacitor Co (Δ) 3%
9. Percent voltage ripple in the capacitor Cch (ξ) 0.1%

TABLE 3 Design values for different charger components

Selected
S. No. Parameter Calculated value value

1 Input inductor (Lm,a ) 1.08 mH 1 mH

2 Transfer capacitor (Cs,a ) 5.11 μF 5 μF
3 Output inductance (Lo ) 108.39 μH 50 μH
4 Filter capacitance (Cfmax ) 976 nF 580 nF
5 Filter inductor (Lf ) 1.7 mH 2 mH
6 DC link capacitor (Co ) 1061 μF 1000 μF
7 Magnetizing inductance (Lf ) 240 μH 130 μH
8 Output capacitor (Cch ) 1119 μF 1000 μF

The two devices of the new SI SEPIC converter-based
charger operate with the pulses in synchronism over a switching
cycle. As the converter is designed in DCM, voltage feedback-
based controller is used to control the DC-link voltage. To
obtain the gate pulses, only one quantity, (Vo ) is sensed and
compared to the reference, Voref . An error, Voe is obtained
as a result of this comparison, which is used as an input of PI
(Proportional-Integral) controller. The expression for this error,
at kth sampling instant, is given as,
Voe (k) = Vo ref (k) − Vo (k)
A control signal, CI is obtained as a result of processing this
error through the voltage follower controller, which is written,
at kth sampling instant, as,
Cvo (k) = Cvo (k − 1) + Kp {Voe (k) − Voe (k − 1)} + Ki oVoe (k)
o Iche (k) = Ich ∗ (k) − Ich (k)
Where, Kpo and Kio are the gain constants for the propor-
tional and integral parts of the controller. By adjusting these gain
constants, a trade-off between the robustness and safe switch
voltage range is achieved during charging. The gate sequence
for two switches are obtained by comparing the above control
signal, Cvo to a high frequency carrier (St ), such as,
If St < Cvo then Sm,a = 1
for vs > 0; or vs < 0; (27)
If St ≥ Cvo then Sm,a = 0
where, 1 and 0 represent the pulses during Stages 1 and 2 oper-
ation for two switches Sm and Sa .
To generate flyback converter pulses, a cascaded PI controller
is used. A current PI controller followed by a voltage PI con-
troller is used, which facilitates a constant current charging for
CC mode. After the battery achieves the charge range beyond
(25) 80%, a low current is taken from the supply and the battery
starts charging in CV mode. During CC charging, the sensed
battery current, Ich , is compared to the battery reference cur-
rent, Ich * , and an error, Iche , is generated at the output. The
expression for the error, Iche , for the instance of sampling k,
is written as:
(28)
(26)
A control signal, CIch is obtained as a result of processing
this error through the current PI controller. Over the sampling
instant k, the expression of this control signal is given as,
CIch (k) = CIch (k − 1) + Kp {I (k) − Iche (k − 1)}
Ich che
+ Ki Ich Iche (k) (29)
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KUSHWAHA AND SINGH 127

Where, KpIch and KiIch are the gain constants for the propor-
tional and integral parts of the controller.
As soon as, the battery charge reaches the limit of 80%, i.e.
state of charge (SOC) is 80%, the charging of the battery is regu-
lated by the voltage loop. During CV mode, the current PI con-
troller is in inactive state. To charge the battery to attain 100%
SOC, a trickle current is drawn from the supply. The sensed bat-
tery voltage Vch and reference voltage Vch * . of the voltage loop
(i.e. battery voltage), are given to the comparator. At output,
an error signal, Vche is obtained after this comparison, which
expression is given as,

Vche (k) = Vch ∗ (k) − Vch (k) (30)

The output of this PI controller is the control signal, CVch ,

which is obtained after the processing through the voltage con-
troller. The expression for this control voltage, CVch , is given at
the sampling instant k, as,

CVch (k) = CVch (k − 1) + Kp {Vche (k) − Vche (k − 1)}

Vch
+ Ki VchVche (k) (31)

Where, KpVch and KiVch are the gains of voltage controller

for proportional and integral part, respectively. Using Equations
(29) and (31), the PWM generation is achieved by comparing
the control signals CVch and CIch to a high frequency carrier.
The pulse width determines the period of DCM, over which the
FIGURE 6 Steady state waveforms of charger showing UPF operation. (a)
satisfactory UPF operation is achieved for the charger. Charger voltage and current at input and output Side. (b) Output voltage and
current of SEPIC converter

5 RESULTS AND DISCUSSION at this 300 V, this new converter operates at lower duty cycle
over a conventional SEPIC converter.
In this section, the experimental verification of new charger
with SI SEPIC converter, is demonstrated with a battery pack
of 48 V and 100 Ah capacity. The circuit sensor and opto-
5.2 SI SEPIC converter performance
isolation boards are developed. The control platform for the
charger switches, is obtained using a digital signal processor
Figure 7(a) demonstrates steady state waveforms of diode
(DSP) make Texas instruments (TMS320F28377S). The charger
voltages (vDom and vDoa ) with respect to inductor currents
performance at steady state, as well as, for transients in source
(iLo and iLm,a ). The SEPIC converter operation in DCM
voltage and DC-link voltage, are recorded and discussed as
is observed with a peak current of 23A through an induc-
follows.
tance Lo . However, the inductance Lm,a shows the CCM cur-
rent over a switching interval. Similarly, Figure 7(b) shows
the continuity in voltages across the capacitances Cs and Ca
5.1 Charger performance under steady state with respect to these input inductor currents. It is to be
inferred that these voltages follow voltage specifications as per
Figure 6(a) shows the waveforms of source voltage (vs ), source
Equations (9) and (10).
current (is ), battery voltage and current (Vch and Ich ) are
recorded during steady state. The unity PF operation of the
charger is demonstrated from the in-phase source voltage and
5.3 Reduced switch voltage stress
current waveforms.
The output voltage Vch of the charger is controlled at 65 V
The voltage across and the current through the SI SPEIC con-
and a constant current of 10 A is observed through the battery
verter switches Sm , Sa are recorded as shown in Figure 7(c). As
in CC–CV mode. Figure 6(b) verifies that the DC-link voltage
per zoomed view of these waveforms, a peak voltage stress of
(Vo ) of SI SEPIC converter is controlled at 300 V, with corre-
230 V is observed across main and auxiliary switches, which is
sponding DC-link current (Io ). To regulate the DC-link voltage
slightly higher than analysis in mode-II.

128
FIGURE 7 SI SEPIC converter performance under steady state, (a) out-
put inductor current showing DCM with diode voltage. (b) continuous currents
iLm,a as well as voltages vCs and vCa , (c) reduced switch voltage and current
Due to switched inductor configuration at the input, the
device voltages are seen to be lower than a conventional
SEPIC converter-based charger i.e. (Vsm + Vo ). The increased
step-up gain of the converter implies to a reduced duty ratio
of converter to achieve a given output voltage of 300 V.
This leads to a low conduction loss in circuit and improved
efficiency.
5.4 Performance under transient condition
To test robust performance, the improved PF charging per-
formance of proposed charger is recorded under transients
in source voltage from 55 to 95 V (rms). It is seen from
Figure 8(a,b) that the supply current is the replica of the supply
voltage. For two extremes of supply voltage, supply current har-
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KUSHWAHA AND SINGH
FIGURE 8 Robust performance of the charger for transients in Supply
Voltage in CC mode. (a) Waveforms of vs , is , Vo and Io showing unity PF char-
acteristics for voltage 55V rms and (b) waveforms of vs , is , Vo and Io showing
unity PF characteristics for voltage 95V rms
monics are reduced to meet the IEC regulations [4]. Over com-
plete fluctuations range of input voltage, a constant battery volt-
age, (Vch ) is recorded. Moreover, for CC charging, the charging
current (Ich ) is seen to be constant with low ripple, same as in
steady state condition. The supply current observes a decrease
and an increase in magnitude from rated value, in proportion to
a change in supply voltage for 95 V(rms) and 55 V (rms) cases,
respectively. This verifies power profile of charger at these tran-
sients in the supply voltage.
This high gain SEPIC converter is tested to verify the
dynamic performance of the charger over the fluctuations in
DC-link voltages from 300 to 200 V and vice versa. Figure 9(a)
shows that during the change in the DC-link voltage from 300–
200 V, the rated current is taken from the supply after sudden
undershoot within limit. Similarly, as soon as the DC-link volt-
age rises from 200–250 V, the current drawn from mains shows
an overshoot, as shown in Figure 9(b). It is seen that irrespective
of variation in the DC link voltage during two cases, a constant
current based charging is facilitated for the battery. Moreover,
the improved PQ operation of the charger is maintained over
the entire varying range of the DC-link voltage.
5.5 High PQ performance at supply end
A high-power quality based performance of proposed charger
is recorded and shown in Figure 10(a–c) at rated source voltage
of 70.7 V (rms). Figure 10(a) show source voltage and current

KUSHWAHA AND SINGH
FIGURE 9 Charger performance showing waveforms of vs , is , Vo and Ich
during CC mode of charging. (a) over variation in DC-link voltage from 300 to
200 V and (b) over variation in DC-link voltage from 200 to 250 V
FIGURE 10 High PQ performance for source voltage of 70.7 V. (a) unity
PF source current with respect to line voltage. (b) Charger power profile and
high PF, DPF. (c) Rms input current and its harmonics spectrum
waveforms for unity PF based operation. The power profile for
the rated source voltage, along with input side power quality
indices, is observed as per Figure 10(b). The reactive power
requirement for the charger is very low unlike a conventional
charger shown in Figure 1. The indices are perfect for sinu-
soidal mains current e.g. PF are recorded as 0.99 and DPF is
equal to unity. Figure 10(c) exhibits the recorded harmonics
distortion for the source current as 4.9%. These parameters are
observed to be in compliance with the recommended standard.
Similar observations are recorded over sudden transients in
the source voltage for the range 55–95 V (rms), as shown in
Figures 11(a–c) and 12(a–c). The power profile, improved PQ
indices and current THDs are also observed as per the IEC
standard [4], for this source voltage range.
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129
FIGURE 11 High PQ performance for source voltage of 55 V. (a) unity
PF source current with respect to line voltage. (b) Charger power profile and
high PF, DPF. (c) Rms input current and its harmonics spectrum
FIGURE 12 High PQ Performance for source voltage of 70.7 V. (a) unity
PF source current with respect to line voltage. (b) Charger power profile and
high PF, DPF. (c) Rms input current and its harmonics spectrum
5.6 Performance comparison with earlier
SEPIC converter based chargers
The performance of this improved SEPIC converter is analysed
based on efficiency; losses and switch voltage stress comparison
with the previously developed conventional SEPIC converter,
single stage single switch integrated flyback converter [28] and
high gain SEPIC converter [20].
The peak efficiency of this SEPIC converter is recorded as
91.36%, which gives a rise than that with conventional cases,
as shown in Figure 13(a). This increased efficiency is observed
due to the high step-up gain of the converter, which implies
a reduced duty ratio of converter to achieve the given output
voltage of 300 V. This leads to a low conduction loss in the cir-
cuit, as shown in Figure 13(b). The efficiency of conventional
SEPIC converter-based charger and integrated SEPIC-flyback
converter based charger [28] is found to be degraded due to
operation at higher duty cycle to produce the required output
voltage.
Figure 13(c) shows that device voltage stresses are recorded
significantly low for new SI SEPIC converter and high gain
SEPIC converter [20] over traditional SEPIC converter. This,
further, helps in achieving reduced device loss and maximiz-
ing efficiency. On the other hand, higher switch voltage stress
is observed in conventional SEPIC converter as well as the inte-
grated converter presented in [28]. These converters are not
suitable for low cost and high power density based charger due
to use of larger power devices. Therefore, high step-up gain
PFC converter topologies are seen to be more efficient and cost-
effective means for PQ improvement at charger front-end.

130
FIGURE 13 Comparison of new SEPIC converter based charger with
previously developed SEPIC converter. (a) Efficiency vs. power variation. (b)
Losses in different devices and components. (c) Reduced device voltage stress
vs. DC voltage gain
6 CONCLUSION
A new SI SEPIC PFC converter with extended voltage gain,
is presented in this work for the EV charger. Due to switched
inductor configuration at the input, device voltages are seen to
be lower than a conventional SEPIC converter-based charger
i.e. (Vsm + Vo ) and other high gain converters. The increased
step-up gain of this converter implies to the reduced duty ratio
of converter to achieve the given output voltage of 300 V. This
leads to a low conduction loss in the circuit and improved effi-
ciency. Moreover, low stress enables the use of power devices
with lower rating, which gives size and cost advantages. The
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KUSHWAHA AND SINGH
control implementation is simple due to less sensing require-
ment in DCM design. The high-power quality charging perfor-
mance is validated at steady state as well as over transients in
source voltage and DC-link voltage. Moreover, improved PQ
indices and current THDs are observed as per the IEC standard
[4], even under these transient conditions.
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How to cite this article: Kushwaha R, Singh B. A
high-power quality battery charger for light electric
vehicle using switched inductor PFC converter. IET
Power Electron. 2021;14:120–131.
https://doi.org/10.1049/pel2.12016