IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO.

1, JANUARY 2005 25

Flyboost Power Factor Correction Cell and a New

Family of Single-Stage AC/DC Converters
Shiguo Luo, Weihong Qiu, Student Member, IEEE, Wenkai Wu, and Issa Batarseh, Senior Member, IEEE

Abstract—A novel power factor correction (PFC) cell, called

flyboost, is presented. The proposed PFC cell combines power
conversion characteristics of conventional flyback and boost con-
verters. Based on the flyboost PFC cell, a new family of single-stage
(S2 ) ac/dc converters can be derived. Prominent features of newly
derived S2 converters include: three power conversions, i.e., boost,
flyback, and another isolated dc/dc power conversions are simul-
taneously realized that typically uses only one power switch and
one simple controller; part of the power delivered to the load is
processed only once; bulk capacitor voltage can be clamped to the
desired level; and capable of operating under continuous current
mode. Experimental results on example converters verify that
while still achieving high power factor and tight output regulation,
the flyboost PFC cell substantially improve the efficiency of the
converter.
Index Terms—AC/DC converter, power factor, power factor cor-
rection, single-stage, single-switch.

I. INTRODUCTION

P OWER factor correction (PFC) techniques have become

increasingly important since several regulations that are
used to limit harmonic injection to the power utilities have been
enacted recently. There are two basic PFC approaches, namely,
active PFC and passive PFC. Active PFC, classified by the
system configurations, can be categorized into two-stage and
single-stage S schemes. A two-stage scheme results in high
power factor and fast response output voltage regulation by
using two independent controllers and optimized power stages,
as shown in Fig. 1(a). The main drawbacks of this scheme are its
relatively higher cost and larger size resulted from its compli-
cated power stage topology and control circuits, particularly in
low power applications. An S scheme combines the PFC cell
and dc/dc power conversion cell into one stage, and typically
uses only one controller and shares power switches, as shown
in Fig. 1(b). It should be pointed out that from the viewpoint of
functionality, in order to get high power factor and regulated
output, an S converter actually still needs to complete PFC
Manuscript received April 10, 2003; revised January 5, 2004. This work was
supported in part by NASA and the National Science Foundation under Grant
ESC-0132965. This paper was presented in part at 33rd IEEE Annual Power
Electronics Specialists Conference (PESC’02), 2002. Recommended by Asso-
ciate Editor S. Y. Hui.
S. Luo is with Dell Computer Corporation, Round Rock, TX 78682 USA
(e-mail: shiguo_luo@dell.com).
W. Qiu is with Intersil Corporation, Palm Bay, FL 32905 USA (e-mail:
wqiu@intersil.com).
W. Wu is with Osram Sylvania, Beverly, MA 01915 USA.
I. Batarseh is with the Department of Electrical and Computer Engi-
neering, University of Central Florida, Orlando, FL 32816 USA (e-mail:
batarseh@mail.ucf.edu).
Digital Object Identifier 10.1109/TPEL.2004.839876
0885-8993/$20.00 © 2005 IEEE
Fig. 1. Functional block diagram of PFC converters: (a) two-stage PFC
converter and (b) typical single-stage PFC converter.
and dc/dc regulating tasks as a two-stage converter. Usually, the
high power factor of an S PFC converter is guaranteed by
operating the PFC cell in discontinuous current mode (DCM),
while the fast response output regulation is achieved by the
dc/dc cell. Many S converters have been presented in recent
years [1], [2]. Although the single-stage scheme is especially
attractive in low cost and low power applications due to its
simplified power stage and control circuit, major issues still
exist, such as low efficiency and difficulty being moved to
higher power level, and high as well as wide-range intermediate
dc bus voltage stress [3], [4].
In conventional PFC ac/dc converters, as shown in Fig. 1(a)
and (b), no matter whether it is a single-stage or a two-stage
configuration ac/dc converter, ac input power is first transferred
into somewhat pulsating dc power stored on intermediate bulk
capacitors, this process is completed by a PFC functional cell.
The power stored on the bulky capacitors is processed again by
a dc/dc functional cell to reach final output. This double power
processing results in low conversion efficiency, which is the
product of the efficiency of each power conversion. In an ac/dc
converter, the way with which power is processed only once is
referred to as direct power transfer (DPT) in this paper. Use of
26
DPT concept to obtain increased conversion efficiency has been
reported in [5]–[11].
As described in [10] and [11], the simplest circuit to carry out
the DPT concept is the flyback circuit. However, the following
arguments still exist.
1) Large low-frequency ripple is present at the output, par-
ticularly at double the utility line frequency. A very large
size output filter is needed, in which the capacitor could
be actually understood as an equivalent part of the bulk
storage capacitor in other S converters. Usually, a bulk
capacitor is necessary to realize required holdup time and
handle low-frequency power unbalance between input
power and output power within a half line cycle.
2) Slow regulation of the output voltage due to the large
output filter and the low loop crossover frequency.
3) Holduptimecannotbeguaranteedduetolackofbulkstorage
capacitor in the high voltage primary side. A complicated
circuit for hold-up time has been designed to solve this issue
[10], however, it is not a cost-effective solution.
A parallel power factor correction (PPFC) approach has been
proposed in [5] and [6], which allows partial input power to be
processed only once. However, the parallel circuit configura-
tion inherently implies that multiple power switches and control
loops must be used, as demonstrated in example converters in
[5] and [6]. Complicated circuit structure may cause practical is-
sues such as sophisticated operation mechanism, complex con-
trol, and thus difficult design and poor reliability. That is why
the authors in [5] and [6] suggest that the applications may be
suitable for high power only.
Assuming that a complete converter stage consists of a con-
troller and one or more power switches responding to specific
turn-on and turn-off commands, technical approaches presented
in [7] and [8] to reduce redundant power processing actually
employ a two-stage circuit configuration with a main converter
and an auxiliary converter. Typically, the auxiliary converter
that uses either a buck-boost converter in [7] or a postregulator
in [8] is put in the secondary side. Consequently, a controller
has to be placed in secondary-side. As discussed for flyback
converter above, since bulk capacitors are put in the secondary
low voltage side, capacitor size (total capacitance) cannot be re-
duced to realize required holdup time and handle low-frequency
power unbalance between input power and output power within
a half-line cycle. Therefore, at the expense of higher efficiency
while using those circuitries will be an increased cost in prac-
tical applications, caused by more complex circuit structure,
large size filter, floating metal oxide semiconductor field effect
transistor (MOSFET) driver, and multiple bias power supplies
for controls. In addition, as claimed by authors in [8], the range
of output voltage is limited by input voltage, and thus applica-
tions may not be good for universal input (85 to 265 ).
Authors in [9] attempt to generate a set of universal power
flow configurations that might include all circuit structures of
known and unknown PFC converters. Based on the partial power
flow configurations that those authors think of as desired, an-
other family of PFC regulator configurations with reduced re-
dundant power processing has been constructed. However, even
in equivalent circuits of the so-called simplest reduced redun-
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005
dant power processing configurations, each circuit configuration
is still composed of two basic switching converters. A 100 W
example PFC regulator in that paper shows its complex cir-
cuit configuration with three inductive components, three power
switches, and two controls. Therefore, the penalty in realizing
DPT idea is the same as in [5] and [6].
In this paper, a novel PFC cell called “flyboost” is presented
and provides an alternative method to reduce redundant power
processing. Further, a new family of S converters with the
DPT concept is derived, which are intended for use in low
to medium power level ac/dc converters such as adapters of
personal computers. Compared to existing S PFC converters
with reduced redundant power processing [5]–[9], newly de-
rived S converters are of simplified circuit configuration
and control, and typically, only one simple voltage control
and one power switch are needed in circuit implementation.
However, good tradeoff can be obtained in terms of cost, effi-
ciency, size, bulk capacitor voltage level, and component stress.
Experimental results with a representative flyboost converter
demonstrate that the flyboost cell significantly improves the
efficiency over the conventional converter. Moreover, experi-
ments also verify that a newly derived S converter can operate
in discontinuous current mode continuous current mode
(DCM CCM) operation due to the clamped bulk capacitor
voltage characteristic of flyboost PFC cell. Our main focus
in this paper is in comparative study rather than optimization
of a specific converter as well as investigating improvements
of existing S converters while using the flyboost PFC cell
to replace conventional boost PFC cell. Further theoretical
analysis and research for applications of the flyboost PFC cell
in other PFC converters needs to be done in the future.
II. FLYBOOST PFC CELL AND ITS OPERATION MECHANISM
As described above, the efficiency of PFC converters can be
improved by converting a part of the input power to output
power with the DPT concept. The present topic is how to im-
plement the DPT concept using a simple circuit structure with a
simple control. First consideration would be to use a simple fly-
back converter to implement the DPT idea. Since there is only
one power switch and one controller, flyback topology is indeed
a single-stage PFC converter when used as a front-end PFC con-
verter with all input power directly transferred to the output.
This is the simplest approach to carry out the DPT concept. It
was reported that an above 85% efficiency could be obtained by
using a relatively complex active clamp flyback topology [10].
However, the above arguments have tarnished the inherent ad-
vantages of the flyback converter when considered as a front-end
PFC converter.
On the other hand, it is well known that the flyback con-
verter can automatically produce near unity power factor with
constant duty ratio under DCM operation [10], [11], as does
the boost converter. Therefore, it is desirable to still keep the
input PFC cell with flyback or/and boost features. The second
desirable feature is to let the input PFC cell implement DPT, al-
lowing a part of input power to be processed once. Meanwhile,
the input PFC cell will allow a part of the input power trans-
ferred to energy buffer bulk capacitors. Bulk capacitors used as
LUO et al.: FLYBOOST POWER FACTOR CORRECTION CELL
Fig. 2. Flyboost PFC cell as a general PFC cell.
holdup time storage components should be placed in the pri-
mary-side in order to reduce the size and number. Further, we
have to keep a conventional dc/dc cell in an ac/dc converter to
obtain tight output regulation and fast dynamic response. The
above deducing triggers the idea that it may be a good choice to
merge flyback with boost topology to achieve a new PFC cell.
Based on this idea, a novel PFC cell was presented, as shown in
Fig. 2.
Unlike any existing PFC cells, the proposed PFC cell simul-
taneously implements both flyback power transfer and boost
power transfer. The transformer modified from the original
boost inductor is named the flyboost transformer because
the combined word flyback boost exactly expresses its new
functionality. The flyboost PFC cell consists of a switch, a
capacitor, a flyboost transformer, and two diodes.
Although there is only a small difference physically between
theflyboostPFC cellandcurrentlyknownPFC cellssuchasboost,
SEPIC,buck-boost,Cuk,andbuck,etc,itsoperationalmechanism
is very different. If considering leakage inductor of flyback trans-
formerandcertaincapacitance,mutualinteractionsamongcircuit
operation modes will definitely exist. Ideally, assuming that the
capacitance of intermediate bulk capacitor is infinitely large such
that it could be regarded as an ideal voltage source, and leakage in-
ductor of the transformer is ignored. There are only two operation
modes for flyboost cell, as shown in Fig. 3(a). These two modes
of operation are discussed as follows.
1) Flyback mode: When rectified input voltage V is
lower than V V , where V is the intermediate
bus voltage and is the turns ratio of T , T operates as a
flyback transformer. When switch is ON, T is charged
by rectified line voltage linearly. When is OFF, T will
discharge all of its stored magnetizing power to the output
through its secondary winding. So the input power stored
in T as magnetizing power during ON period is directly
transferred to the output, resulting in this portion of input
power being processed only once. Operational waveforms
are presented in Fig. 3(b).
2) Boost mode: When V is higher than V V ,
T1 works as a boost inductor. When is ON, T is
charged by rectified line voltage linearly. When is
OFF, T will discharge all of its magnetizing power to
intermediate bus capacitor. The power stored in the dc bus
capacitor will be transferred to the output by the dc/dc
27
Fig. 3. Operation modes of flyboost PFC cell in one line frequency cycle: (a)
j j
mode changes at ( v (t ) = V 0 V =n ), (b) flyback mode, and (c) boost
mode.
conversion cell, with this portion of input power being
processed twice. Operational waveforms are presented in
Fig. 3(c).
According to the operational mechanism of the flyboost PFC
cell, the flyboost PFC cell integrates the functions of flyback
and boost PFC cells. Since high power factor can be achieved
by either the DCM flyback PFC cell or the DCM boost PFC
cell, a high power factor can also be expected from the fly-
boost PFC cell. The tight output regulation and fast dynamic
response would also be accomplished by the dc/dc conversion
cell following the flyboost PFC cell. In addition, the other two
unique advantages of the flyboost PFC cell may be summarized
as follows.
1) Direct power transfer (DPT): At flyback mode, all input
power is directly transferred to load through transformer
T . This portion of input power is processed only once. It
means lower current stress on power devices, and higher
power efficiency.
2) Intermediate bus voltage is clamped automatically:
Only when the rectified input voltage is higher than
V V , will the intermediate bus capacitor be
charged by the input power. The higher bus voltage,
the less charging power to the bus capacitor, thus the
28
maximum intermediate bus voltage will be automati-
cally clamped to V peak V under any load
condition. It means that S PFC converters with the
flyboost cell can operate either in DCM DCM mode or
in DCM DCM mode without high bus voltage problem
with a light load, which is one of the main drawbacks
existing in other S PFC converters in [3], [4], and [13].
As a result, the proposed PFC cell is especially more
suitable for universal input voltage applications with
higher power handling capabilities when compared with
other well-known S PFC converters that cannot operate
under DCM CCM.
By integrating flyboost PFC cell with conventional dc/dc con-
version cells, new S PFC converters can be constructed with
high power factor and tight output regulation. In order to keep
simple control while obtaining both high power factor and tight
output regulation, it is desirable to keep the input cell operating
under DCM. The dc/dc cell can operate either in DCM or in
CCM, depending on dc bus voltage and power level.
III. COMPARISON OF EFFICIENCIES FOR DIFFERENT
POWER TRANSFERS
In a conventional two-stage or S PFC ac/dc converter,
there are two functional cells, i.e., PFC cell and dc/dc cell.
AC input power is first transferred into somewhat pulsating
dc power stored on intermediate bulk capacitors by the PFC
cell. The stored dc power on the bulk capacitors is processed
again by the dc/dc cell to the desired dc output power. So the
input power is processed twice to reach the output, as shown in
Fig. 4(a). Assuming the PFC cell has unity input power factor,
and the efficiency of the PFC cell and dc/dc cell are and ,
respectively, we have output power
(1)
and the resultant efficiency of S PFC ac/dc converter is
(2)
From the above equations, we can see that the dual power
processing approach means lower conversion efficiency since it
is the product of the efficiency of each power conversion.
Some new power transfer approaches have been proposed in
[5]–[9] that allow a part of the input power to be processed
only once and let the remaining input power to be processed
twice while still achieving both high power factor and tight
output regulation. Those power transfer approaches provide a
new way to achieve more efficient and higher power rating PFC
converters than the conventional double power processing ap-
proach. A block diagram of the proposed power transfer ap-
proach with the DPT concept is expressed in Fig. 4(b).
In Fig. 4(b), k portion of the power from the PFC cell is di-
rectly transferred to the output, and the remaining power
from PFC cell is stored in the intermediate bus capacitor and
then processed by the dc/dc cell. Based on this concept, we have
(3)
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005
Fig. 4. Power transfer block diagrams of PFC ac/dc converters: (a)
conventional power transfer and (b) proposed power transfer with DPT
concept.
so the efficiency of this S PFC ac/dc converter is
(4)
Comparing (2) with (4), it is clear that the converter with the
DPT generally has higher efficiency than its counterpart without
the DPT approach, simply because the converter with the DPT
concept follows an inequality
(5)
where , , and .
The above efficiency comparison enhances our understanding
why the DPT concept will help build an inherently more effi-
cient PFC converter.
IV. NEW FAMILY OF S CONVERTER TOPOLOGIES BASED ON
THE FLYBOOST PFC CELL
Like other PFC cells such as boost, SEPIC, buck-boost, and
Cuk [1], the flyboost PFC cell in Fig. 2 can be used to replace
existing PFC cells in the family of S topologies and thus a new
family of topologies can be derived from the general functional
structure shown in Fig. 1(b). A similar derivation using the fly-
boost cell can be applied into other existing two-stage topolo-
gies. As a result, a new family of two-stage topologies can be
achieved through a general structure diagram shown in Fig. 1(a).
The research in this paper is concentrated on only S converters.
Fig. 5 gives some sample topologies obtained through mod-
ifying existing S converter topologies. For clarity and sim-
plicity, the input EMI filter, the reset and clamp circuits of the
single-switch flyback and forward converter cells are not de-
picted. Flyboost PFC cell combines the characteristics of con-
ventional flyback and boost functional cells. Therefore, com-
pared to other known S converters, the derived converters in
Fig. 5 have the following potential merits:
1) high power factor due to inherent characteristics resulting
from both the flyback and boost converters;
LUO et al.: FLYBOOST POWER FACTOR CORRECTION CELL 29

Fig. 5. Derived new family of S converter topologies based on the flyboost

+
PFC cell and typical dc/dc cells: (a) flyboost PFC flyback dc/dc, (b) flyboost
+
PFC forward dc/dc, (c) modified BIBRED with flyboost PFC, (d) flyboost
+ +
PFC two switch flyback dc/dc, (e) flyboost PFC two switch forward dc–dc,
(f) flyboost PFC + half-bridge dc/dc, and (g) flyboost PFC + series/parallel
flyback.
Fig. 6. Example S topologies: (a) Russian’s topology, (b) simplified topology
based on the Russian’s topology, and (c) newly modified topology with flyboost
2) high efficiency due to partial input power being processed PFC cell.
only once;
3) intermediate dc bus voltage is clamped automatically
within a desirable range, which is determined by peak V. OPERATION AND BASIC DESIGN CONSIDERATIONS
OF AN EXAMPLE CONVERTER
input voltage and the turns ratio of the flyboost trans-
former; A. Converter Operation
4) relatively low voltage stress power devices can be used in
For the sake of topology comparison, related topologies to
the proposed converters because of controllable interme-
example converter with flyboost PFC cell are drawn as follows.
diate dc bus voltage;
5) input inrush and surge current protection because of in- So-called Russian’s S topology is depicted in Fig. 6(a) [17].
herent characteristics of flyback and boost converters; A simplified S topology based on the Russian’s topology that
6) simple circuit structure due to the use of only one power uses leakage inductors of the transformer is investigated in detail
switch (or one stage) and one controller while keeping the in [12], as shown in Fig. 6(b), where and are the leakage
same number of magnetic components; inductors. Combining the flyboost cell, the Russian’s topology
7) higher power processing capability due to dual power can be further modified into a new topology shown in Fig. 6(c),
transfer channels and the CCM operation possibility of which basically consists of a flyboost PFC cell and a series/par-
the dc/dc cell; allel forward converter cell. Compared to Fig. 6(a), physically,
8) holdup time in the proposed converter is guaranteed by the only added part is diode . One more winding (usually
primary side bulk capacitors; with a few turns) on the same core of the previous boost in-
9) fast output voltage regulation is provided by dc/dc con- ductor that changes it into a special transformer to implement
version cell. the DPT concept.
30 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005

For most of the existing S topologies, simply and optimally,

both the PFC cell and the dc/dc cell should operate in DCM,
otherwise, it is almost impossible to satisfy trade-offs of design.
This is because the intermediate dc bus voltage variation range
is load-dependent and unacceptable if DCM CCM operation is
employed [3], [4]. In the topology shown in Fig. 6(c), an impor-
tant trait is that the intermediate dc bus voltage is controllable if
only the flyboost PFC cell is properly designed. DC bus voltage
can be limited to a desired range. This means that the proposed
topology can operate either DCM DCM or DCM CCM while
still keeping a simple controller. With the first DCM, by the end
of the switching cycle, the flyboost delivers all of its stored en-
ergy to either the next stage or the output. With the second DCM,
the output-filtering inductor current for the dc/dc forward cell is
discontinuous on a cycle-by-cycle basis. With the second CCM,
the output-filtering inductor current for the dc/dc forward cell is
continuous. At the first DCM there is only a slightly increased
conduction loss because the reverse recovery loss of diodes will
be decreased. But the switching losses associated with the hard
turn-off of the rectifier diodes are eliminated.
Like other S converters, the example topology has only one in-
ductiveenergy-storagecomponentforeachconversioncell.How-
ever,therearethreepowertransfermodessimultaneouslyexisting
in the converter, i.e., flyback, boost, and forward modes. As dis- Fig. 7. Key waveforms of example converter.
cussedearlier,thePFCcellhastwobasicoperationmodes:flyback
mode and boost mode. For the forward cell, we need to consider TABLE I
that the circuit is operating in the DCM or CCM. Fig. 7 shows key +
CONDUCTION STATUS OF POWER COMPONENTS IN DCM CCM MODE
operation waveforms of the example converter in Fig. 6(c). Table I
givesconduction status of power components under DCM CCM
operating, corresponding to typical four periods of circuit opera-
tion in one switching cycle in Fig. 7.

B. Basic Design Considerations

In example converter shown in Fig. 6(c), a simple voltage
mode control strategy is used for either DCM operation or
DCM CCM operation. According to the characteristics of the
proposed flyboost PFC cell and topology, basic design consid-
erations are discussed as follows.
1) Control: Like other regular dc/dc converters, a single
fast voltage control loop can be employed, which keeps the
output voltage constant by monitoring the output voltage and
correcting it as needed. Current-mode controls (either con-
stant-frequency or variable-frequency) are also applicable. But
this family of topologies complicates the control strategy of
current mode, because the inner current-controlling loop must
be based on the current flowing in the dc/dc cell and current
flowing in the secondary side of the flyboost cell. Both currents
are substantially contributing to the load. Due to pulsating fly-
boost secondary current, average switch current-mode (ASCM)
control might fit this application. The benefits of the current
mode control are decreased low-frequency ripple at the output
and increased dynamic response.
2) Intermediate Bus Voltage and Component Voltage
Stresses: The voltage stresses on all power switches depend on
the intermediate bus voltage. So it should be as low as possible
to reduce the voltage rating of power components, which will
result in low cost and higher efficiency. However, V should
be high enough to keep the PFC in the DCM operation at
the lowest input voltage with full load. Since the maximum
intermediate dc bus voltage is clamped at V V ,
the turns ratio n of the flyboost transformer determines the bus
voltage level. Meanwhile, rated component voltage in primary
side at the worst case might be considered with certain safety
coefficient (say 1.2) based on this maximum dc bus voltage
V .
3) Design of dc/dc Cell Transformer: The demagnetizing
voltage for the dc/dc forward transformer is clamped at V , The
magnetic constraints require that the maximum duty cycle must
be lower than 0.5.
Taking the CCM operating mode as example, the following
constraints should be applied:
(6)
where represents designed maximum duty cycle, V
represents minimum dc bus voltage, is turns ratio, and V
output voltage.
LUO et al.: FLYBOOST POWER FACTOR CORRECTION CELL
Turns number of transformer at primary and secondary sides
can be determined by
(7)
and
(8)
where and represents turns numbers of primary-side and
secondary-side, respectively, and is the designated max-
imum flux density, usually taking , and is the mag-
netic core across-section area.
4) Design of Flyboost Transformer: In a flyboost converter
the most challenging design is for the transformer. The trans-
former performs both the flyback and boost types of power
transfer, with most of the power transferred by the flyback
mode with DPT concept. Therefore, it can be concluded that
flyback operation dominates the activity of flyboost PFC cell.
For purpose of analysis it can be considered that all of the
power is transferred by an equivalent flyback transformer. The
following are the simplified design procedure.
a) First, for a DCM operating flyback transformer (inductor),
to protect from flux walking, magnetic reset must be taken
into account, and volt-second balance must be followed
by
(9)
where V represents output voltage, expresses turns
ratio of the flyboost transformer, is designed max-
imum duty cycle (less than 0.5), which is decided by dc/dc
forward controller, corresponding to minimum ac input
voltage V . run in DCM CCM mode that is impossible for conventional
b) Considering power balance between input and output
and also employing the quasistatic principle that ac input
voltage resource is replaced by an equivalent dc voltage
resource with the same value as ac rms, peak current at pri-
mary-side of flyboost could be approximately determined
by
(10)
where is the converter efficiency from input to output,
and is the average output power.
c) Equivalent inductance at the primary side could be
roughly determined as
(11)
5) Capacitors and Inductor: The two bulk capacitors are
mainly designed to meet the holdup time requirement. Setting
holdup time factor (this means 20% voltage drop
during one cycle is permitted), we can determine storage capac-
itance of capacitor by
(12)
31
where V V : ratio of intermediate dc bus voltage to
output voltage, represent load resistor, and T line cycle
(here also holdup time).
Output filter inductor and capacitor can be designed by fol-
lowing typical forward converter design procedures. In gen-
eral, output capacitor at secondary side is mainly determined by
output voltage ripple and max ripple current level at high line
and heavy load conditions. Output inductor is determined by
max ripple current as well as its operating mode in either CCM
or DCM.
6) High Efficiency Design Consideration: In order to
achieve high efficiency while meeting holdup time and tight
regulation, and the more input power must be allowed to
reach the output through flyboost with the DPT method and
duty-cycle should be designed as large as possible.
7) Operation Over a Wide Line Voltage Range: The voltage
across the bulk capacitor is a proportional function of the
line voltage. Several simulation results show that although
maximum dc bus voltage is controllable, the voltage still varies
over two times when the line voltage varies between 85 and
265 V . It is difficult to design the power supply to accom-
modate that variation and to keep high efficiency in the whole
input voltage range. So the optimum point has to be considered
at nominal line voltage.
More practical design considerations and steady-state anal-
ysis with MathCAD can be found in previously published pa-
pers [13]–[15].
VI. EXPERIMENTAL VERIFICATIONS
A. Verification for DCM CCM Operation
This is to verify that the proposed converter has capability to
S converters using only a simple voltage mode controller [3],
[4]. The key circuit parameters designed are: kHz,
H, H, , ,
F [see Fig. 6(c)].
Target specifications are
1) universal line voltage: V ;
2) nominal line voltage: 110 ;
3) output voltage: 28 ;
4) output power: 150 W;
5) holdup time: 0.17 ms;
6) switching frequency: 100 kHz;
7) ripple limit: 200 mV p-p;
8) power factor: higher than 0.95;
9) regulation: 1%.
Fig. 8 shows experimental waveforms of input line voltage
and input line current at nominal line voltage. A near unity
power factor 0.994 is measured and a sinusoidal waveform is
drawn from input line. Fig. 9 shows experimental power factor,
efficiency, and bulk capacitor voltage varying with input line
voltage. The power factor and efficiency only change a small
amount under universal input from 85 to 265 , and dc bus
voltage varies only from 110 V to 265 V , which allows
the use of commercially available 600 V power devices. In
DCM CCM operation, comparison study cannot be completed
32
Fig. 8. Experimental line voltage and line current at nominal voltage
110 Vrms: trace A, line voltage (100 V/div, 5 ms/div); trace B, line current
(measured after auxiliary line filter; 1 A/div; 5 ms/div), and the measured
power factor is 99.4%.
+
Fig. 9. Experimental results under DCM CCM operation: (a) power factor,
(b) efficiency, and (c) bulk capacitor bus voltage varying with input line voltage.
because unchanged topologies in Fig. 6(a) and (b) cannot be
run in this mode.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005
=
Fig. 10. Experimental comparison for conventional and proposed topologies
+
under DCM CCM operation: (a) power factor, (b) efficiency, and (c)
intermediate bus voltage.
B. Verification and Comparison for DCM DCM Operation
Prototypes based on the topologies in Fig. 6(a)–(c) were built
to meet the following major design specifications:
1) input: 85 265 ;
2) output: 28 at 150 W;
3) switching frequency: 100 kHz;
4) circuit parameters: H, H,
, and .
All measurements were completed at 150 W full load, and all
power losses were included while calculating efficiency.
Measured power factor under universal input is shown in
Fig. 10(a). Compared to the simplified topology in Fig. 6(b),
it can be seen that the newly modified converter in Fig. 6(c)
significantly improves power factor and an above 0.97 power
factor can be achieved under universal input. For the Russian
topology shown in Fig. 6(a), although high power factor is
obtained, it has no operating capability under universal input
because excessive dc bus voltage is encountered with increased
input voltage. Fig. 10(b) shows experimental efficiency com-
parison with different topologies at full load 150-W output.
LUO et al.: FLYBOOST POWER FACTOR CORRECTION CELL
The topology with the flyboost PFC cell achieves the highest
efficiency, and the second is Russian. Fig. 10(c) shows experi-
mental intermediate dc bus voltage comparison at full load. The
simplified topology in Fig. 6(b) has the lowest dc bus voltage,
but its variation range is comparable to the topology with
flyboost PFC cell, about 130 . The Russian topology has
excessive bus voltage when the input exceeds 150 thereby
making it impractical for universal input applications.
Another application example based on a simple bi-flyback
topology has been reported in [16]. Detailed simulation work
was also completed in [13].
VII. CONCLUSION
A novel PFC cell, called flyboost, has been proposed in this
paper, from which a new family of S PFC topologies can be de-
rived. The proposed flyboost PFC cell allows a portion of input
power transferred to the output directly, resulting in improved
efficiency. In addition, the derived PFC converters based on the
flyboost PFC cell have been characterized with the unique ad-
vantages of controllable dc bus voltage, inherently high power
factor, low component stress, and simple circuit structure. These
unique merits allow newly derived PFC converters to operate
under DCM CCM for universal input applications with sub-
stantially improved efficiency. Therefore, good tradeoff can be
obtained in terms of cost, efficiency, size, bulk capacitor voltage
level and component stress.
Based on a 150 W at 28 V experimental prototype, the ex-
periments for a specific example converter were carried out to
verify the operation of the converter under both DCM CCM
and DCM CCM modes. Experimental results demonstrate that
while obtaining high power factor, the flyboost cell substantially
improves the efficiency of the converter over conventional PFC
ac/dc converters without the flyboost PFC cell.
The newly proposed flyboost PFC cell is a generalized one
that can be used in any existing PFC converters, either two-stage
or S configurations, and particularly suitable for those where
the boost converter is being used as a PFC cell.
ACKNOWLEDGMENT
The authors wish to thank Dr. P. Kernetzky for providing the
help in conducting the experimental work and R. J. Maley for
his time used in helping to refine the technical writing.
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1994.
Shiguo Luo received the B.S. degree in industrial
automation from the Southwest Institute of Tech-
nology, Sichuan, China, in 1985, the Ph.D. degree in
electrical engineering from Chongqing University,
Chongqing, China, in 1993, and the Ph.D. degree in
electrical engineering from the University of Central
Florida (UCF), Orlando, in 2001.
Starting in 1985, he was an Assistant Lecturer
and later an Associate Professor at Chongqing En-
gineering Institute, Chongqing. From 1993 to 1995,
he was with the School of Electrical Engineering,
Southwest Jiaotong University, Sichuan, as a Post-Doctoral Fellow. From 1997
to 1998, he was a Visiting Professor in the Virginia Power Electronics Center
(now CPES), Virginia Polytechnic Institute and State University, Blacksburg.
In more than 15 years of professional experience, he also worked for Huawei
Technology Ltd., Shenzhen, China, Lucent Technologies Power Systems, Inc.,
Mesquite, TX, and Artesyn Technologies, Inc., Framingham, MA. He is now
a Senior Consultant Engineer at Dell Computer, Inc. His current research
interests are computing system-oriented power analysis and design techniques.
Weihong Qiu (S’02) received the B.S. degree from
Xiangtan University, Xiangtan, China, in 1991, the
M.S. degree from Nanjing University of Aeronautics
and Astronautics, Nanjing, China, in 1994, and the
Ph.D. degree from the University of Central Florida,
Orlando, in 2003.
He joined Intersil Corporation, Palm Bay, FL, in
2003. His research interests include modeling and
control design of switching power converter, PFC,
and VRM techniques.
34 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005

Wenkai Wu received the B.S. degree from Jiao Tong Issa Batarseh (S’84–M’85–SM’92) received the
University, Xi’an, China, in 1986, the M.S. and Ph.D. B.S. degree in computer engineering, and the M.S.
degrees from Tsinghua University, Beijing, China, in and Ph.D. degrees in electrical engineering from the
1993 and 2000, respectively, and the Ph.D. degree in University of Illinois at Chicago, in 1983, 1985, and
electrical engineering from the University of Central 1990, respectively.
Florida, Orlando, in 2003. He is a Professor and Chair of the Electrical and
His interests include ac/dc converters with active Computer Engineering Department, University of
power factor correction, maximum power tracking ar- Central Florida (UCF), Orlando. He was a Visiting
chitectures, high power electronic ballast, and low Assistant Professor of Electrical Engineering at
voltage dc/dc converters. He is a Principal Engineer Purdue University, Calumet, IN, from 1989 to 1990
with Osram Sylvania, Beverly, MA. before joining the Department of Electrical and
Computer Engineering, UCF, in 1991. His major research interest is power
electronics, focusing on high frequency dc-dc conversion, soft-switching and
dynamic modeling of dc-to-dc converters, harmonic analysis, and power factor
correction. He has more than 11 U.S. patents, and more than 50 refereed journal
and 200 conference publications. His research work has been sponsored by
federal agencies and private sector. He authored Power Electronic Circuits
(New York: Wiley, 2003).
Dr. Batarseh received many national and international teaching, research, and
service awards. He served as Session Chairs and Committee Member for APEC
and PESC Conferences. He will be the General Chair for the PESC’07 Con-
ference, Orlando. He has served as a Chairman of the IEEE Orlando Power
Engineering Chapter, Chairman of the IEEE Orlando Section, and as Faculty
Advisor for the IEEE Student Branch and Eta Kappa Nu. He is a Registered
Professional Engineer in Florida.