Electrical Power and Energy Systems 125 (2021) 106496

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International Journal of Electrical Power and Energy Systems

journal homepage: www.elsevier.com/locate/ijepes

Sliding mode controller-based switched-capacitor-based high DC gain and

low voltage stress DC-DC boost converter for photovoltaic applications
Qun Qi a, *, Davood Ghaderi b, *, Josep M. Guerrero c
a
School of Rail Transit, Guangdong Communication Polytechnic, Guangzhou, Guangdong 510650, China
b
Electrical and Electronics Engineering, Department of Bursa Technical University, Bursa 16310, Turkey
c
Center for Research on Microgrids (CROM), Department of Energy Technology, Aalborg University, 9220 Aalborg East, Denmark

A R T I C L E I N F O A B S T R A C T

Keywords: High-gain DC-DC power boost converters blocks have been converted to the main transitional topologies for the
Single-switch boost converter PV applications to enhance the level of the generated voltages of these panels for grid applications. The single-
High voltage gain switched and transformer-less converters due to their higher efficiency, and cheaper and light-weighted features
Reliability
are the first selection for these converters design. This study presents a transformer-less DC-DC power boost
Renewable energy sources
converter with a switched-capacitor structure with a sliding mode controller (SMC) to increase the DC voltage
gain and decrease the voltage stress on the power switch. This advantage is doing based on the preamplifier block
by using an extra inductor at the input side. Also, the switched-capacitor block easily decreases the voltage
stresses on the main power switch and other diodes. Presenting high voltages under the small duty cycles is one
of the most important features of the proposed converter that allows longer off-time duration for power switch
for Continuous Current Mode (CCM) operations. This leads to lower amounts of the dynamic losses for the power
switch and higher efficiency. On the other hand, the control process of the proposed converter under the different
input voltages and output powers and loads due to using only one power switch is simpler compared with multi-
switched topologies. All calculations for obtaining the gain, currents follow through the components, voltage
ripples through the capacitors, and efficiency is presented. The hardware prototype with 300 W power is tested
and the results confirm the theoretical calculations.

converters use the transformer in their design that leads to the heavy
and large structures that normally the efficiency of these converters are
1. Introduction
not considerable compared with the new high-gain and high-efficiency
designs. For fly-back and all other converts that use the transformer,
High efficiency, small size, reasonable price and high reliability in
the input DC voltage normally by a resonant circuit or an inverter is
switching power converters make them widely be applicable in elec­
converted to the AC voltage and for the next step an AC voltage with
trical and electronic industries and Renewable Energy Sources (RESs)
higher magnitude is obtained at the secondary side of the transformer
applications. DC-DC boost converters are the undeniable and the most
and then by a rectifier block, this voltage is converted to the DC voltage
important parts for the PV and fuel cell applications since these sources
with the desired amplitude. Therefore, the efficiency of these types of
generate the specified and limited amounts of the voltages [1–4]. These
converters in impressed by the high number of the middle blocks and
converters enhance these voltages to an acceptable level to be applied
components in the converter [16–19]. Fly-back and push–pull con­
for grid-side [5,6].
verters are known as the isolated converters. This means based on the
Various designs for this type of power converters have been pro­
existing a transformer in their structure, the ground of the sections
posed. The conventional boost converters [7–10] are the basic designs of
before and after the transformer is different and separate. Therefore, it
the DC-DC step-up converters including the one inductor, one power
needs to more components an approaches for load connections. The
switch, and one power diode. Since the structure of this converter is
leakage inductor is the next problem of these converters. to overcome to
simple, and the interleaved structures have not been considered for
these problems active-clamp and snubber topologies should be added to
these topologies, they are proper for low-power applications. Also, the
the converter that increases the number of the components and cost of
fly-back [11–13] and Cuk [14,15] converters are presented. Fly-back

* Corresponding authors.
E-mail addresses: qiqunqi@163.com (Q. Qi), davood.ghaderi@btu.edu.tr (D. Ghaderi).

https://doi.org/10.1016/j.ijepes.2020.106496
Received 20 April 2020; Received in revised form 18 July 2020; Accepted 1 September 2020
Available online 15 September 2020
0142-0615/© 2020 Elsevier Ltd. All rights reserved.
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

Nomenclature rDS Internal resistance for the power switch

RF1 to RF6 Internal resistance for the diodes
CCM Continuous Current Mode RC1 to RC6 and RCO Internal resistance for the capacitors
RES Renewable Energy Sources rL1 torL3 Internal resistance for the inductors
EMI Electromagnetic Interference RMS Root Mean Square
SC Switched-Capacitor PSw Switching losses of the switch
SI Switched-Inductor PSwitch Total losses of the switch
ZVS Zero Voltage Switching PrDS Dynamic loss for the switch
ZCS Zero Current Switching (PVF )D Power losses for the diodes
L1, L2 and L3 Inductors L1 to L3 PRC Power losses across the serial equivalent resistance of the
D1-D6 Power diodes capacitors
C1-C5 and CO Capacitors PrL Power losses on these inductors
VC1, VC2, VC3, VC4, VC5 and VCO Voltage across the capacitors η Efficiency
VL1, VL2 and VL3 Voltage across the inductors ΔVC,ESR Ripple caused by the internal resistance of per capacitor
D Duty cycle ΔVC,cap Ripples values rooted in charging-discharging time
Vi Input voltage intervals for the capacitors
Vo Output voltage Dm Duty cycle for the DCM working state
MCCM Gain of the proposed converter ID− Peak Total of the peak currents for the diodes D3, D4 and D6
IC,on Current of the capacitors when the switch is activated x1 Voltage error
IC,off Current of the capacitors when the switch is deactivated x2 Error dynamics
IM Current of the power switch x3 Integral of the error
ΔIL1 , ΔIL2 , ΔIL3 The ripples for the inductor currents Vref Reference voltage
fs Switching frequency β Ratio of the feedback network
ΔIL1,max , ΔIL2,max , ΔIL3,max maximum current ripples for the inductors SMC Sliding Mode Controller
ΔVo Output voltage ripple IST Instantaneous State Trajectory
ΔQ Electrical charge across the output capacitorCo PWM Pulse Width Modulation
Co,min Minimum value for output capacitor to fix the output VC Control wave
voltage Vtri Triangular wave
Dmin Minimum value of the duty cycle for the CCM operational ζ Damping factor
mode

the circuit and decreases the efficiency of these topologies. Cuk con­
verters normally ae used as the buck-boost converters and the voltage
gain of these converters is not considerable. Higher DC voltage gains are
obtained in longer duty cycles in these converters that lead the higher
dynamic losses and lower efficiencies. Working in these levels of the
duty cycles makes problems such the diode back-flow and electromag­
netic interference (EMI) that all directly decrease the reliability of the
converter especially in high-power values. One of the most important
criteria in designing a proposed converter is the control process. Since
these converters have a non-linear behavior and reaction against the
parameters like power, changes in input voltage and output load and
voltage and currents of the power components in the topology, the
control design for these converters to obtain a fixed DC voltage at the
load side normally is difficult and should be considered as a major
concern [20–24]. For this reason, normally the single-switch converters
are selected and a part of the voltage gain concedes to the switched-
capacitor section of the converter.
Cascaded converters are presented for high-gain approaches and
since there is only one switch in the per-block the control process seems
to be simple for them. The efficiency of a DC-DC boost converter is
impressed under the parameters like the internal resistance of the power
switches, power diodes, and inductors. Therefore, for the cascaded
converters, although the high-gains can be obtained, the efficiency of
these types of converters is extremely low, especially for high serial
numbers blocks [6,25,26].
To solve these problems, the switched-capacitor (SC) [27,28] and
switched-inductor-based (SI) [29–31] DC-DC boost converters are sug­
gested. These converters use a block of the capacitors and diodes or
inductors and diodes to enhance the voltage gain of the converter. The
basic proposed SC and SI converters have problems such as the high
current stresses on the power switches and diodes. These parameters are
important for the converter efficiency. Also, they had the complex
connections for the SC and SI blocks and therefore the high number of
the components to obtain the high DC gains. For the decreasing the
voltage and current stresses across the switches and diodes, the soft
switching approaches like the zero voltage switching (ZVS) or zero
current switching (ZCS) should be considered for these converters
[32–34].
Another type of DC-DC boost converters is the coupled-inductor-
based converters. Although the number of the turns in the inductor is
important for determining the converter’s voltage gain in this converter,
the input current levels will increase with enhancing the number of the
turns, that causes to be experienced high-level input currents with large
ripples that will impact of the long-life of the inductor and input
capacitor. To obtain higher efficiencies, cross-coupled inductor topol­
ogies using the active or passive clamp structures are used. This tech­
nique gives a soft-switching condition to the power switch [31,35,36].
Refs. [29,31,37] present different modes for these types of converters
including the interleaved connections at the input side for more reli­
ability and lower current values for the coupled-inductors.
In all types of DC-DC converters, the interleaved connections can be
applied. This method uses the same input power source and the parallel
connections the DC-DC boost converter is used. Per block can transfer a
part of the input power and therefore, the efficiency of the converter will
be higher. Although the number of components is more, this technique is
a proper method for high power applications [10,38]. On the other
hand, since the level of the currents is less per block, the long-life of the
components will be more and reliability will increase in these
converters.
This study presents a switched-capacitor-based quadratic single-
switch power boost converter to obtain the high voltage gains and low
voltage stresses across the power components and decrease the
complexity of the controller designs. The control process is done by the
field-programmable gate array (FPGA)-based MyRIO microcontroller

2
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

D1
C2
L2 D3
L1
D2
L3

Vin + +
C3
C1 M

Load
C4 CO

D4 D5

C5 D6
+

(a)

D1
C2
L2 D3
L1
D2
L3

Vin + +
C3
C1

Load
C4 CO
M
D4 D5

C5 D6
+

(b)

D1
C2
L2 D3
L1
D2
L3

Vin + +
C3
C1 M
Load

C4 CO

D4 D5

C5 D6
+

(c)
Fig. 1. (a) Proposed converter and the state of the converter when the power switch acts in the (b) ON and (c) OFF modes.

board under the sliding mode controller (SMC) technique. All details for
designing the controller is presented. The high voltage gain approaches
are achievable by the used switched-capacitor block where at the same
time this block can act as a snubber structure to decrease the voltage and
current stresses on the power switch. The gain of the proposed converter
is extremely high and around 70 times the input voltage can be obtained
in 0.8 of the duty cycle theoretically. For the simulation, under this duty
cycle value, a voltage-gain around 64.5 is obtained. For the hardware
tests by applying the 10VDC as the input voltage and 0.8 of the duty
cycle a voltage around 620VDC is obtained. Although around 12% of
ripple for the output voltage is reported by the experimental tests, it
should be considered that this converter is designed to work at the lower
duty cycles with lower voltage gains. Section 2 investigates the ON and
OFF-states of the switch and two working modes analysis, gain calcu­
lations for CCM, current calculations for the power components, current
ripples calculations for the inductors, output voltage ripples, efficiency
calculations, voltage ripple calculations for other capacitors, operation
analysis for DCM and controller design steps theoretically. Components
values calculations, simulation, and experimental results steps are
shown in section 3. Finally, the conclusion section is presented.

3
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

Vgs operational mode. Since the voltage on the inductor L3 is positive in this
working mode, this inductor begins to be charged. Some of the current
Vds t follow paths are shown in Fig. 1b. Based on KVL laws for this mode, the
below equations can be obtained.
VL1, VL2, VL3

IL1 VL1 = Vi (1)

IL2 IL3 t
VC3 = VC5 (2)

ID1, ID3 VL2 = VC1 (3)

ID2 t VL3 = VC1 + VC4 + VC2 + VC5 − VC3 − Vo (4)

ID4, ID6 In these equations, Vi and VO are the input and output voltages
ID5 t respectively. VL1, VL2 and VL3 are the voltages across the inductors L1, L2,
and L3 and VC1, VC2, VC3, VC4, VC5, and VCO are the voltages across the
0 DT T
capacitors C1 to C5 and CO respectively.
Fig. 2. The gate-source and drain-source voltage across the power switch, Mode 2: The equivalent circuit for this working state is presented in
voltages and currents across the inductors, and currents of the diodes. Inductors Fig. 1c. for this mode, the power switch is deactivated and diodes D2 and
charge and discharge simultaneously. Diodes D1, D3, D4 and D6 are activating D5 work in off-mode and other diodes are activated. Voltages on the
and deactivating synchronously and diodes D2 and D5 activate and deactivate inductors L1 and L2 begin to discharge and the capacitors C2, C3, and C4
simultaneously. are charged and the capacitor C5 is discharged. Also, the inductor L3 that
was in charging mode for the first working mode, for this state will be
discharged. The equations for the components in this mode can be
2. Proposed converter summarized as:

The proposed power converter is illustrated in Fig. 1. This structure VL1 = Vin − VC1 (5)
includes a power switch M, three inductors L1, L2 and L3, six power
diodes D1-D6 and six capacitors C1-C5 and CO. The operation of the VL2 = − VC2 (6)
proposed converter can be investigated in two different modes under the
VL2 = VC1 − VC3 (7)
continue conduction mode (CCM) that are described respectively.
VL3 = VC4 − Vo (8)
2.1. ON and OFF states of the switch and working modes analysis
VC4 = VC3 + VC5 (9)
Mode 1: For time intervals that the power switch is activated, diodes Fig. 2 presents the state of the power components in the proposed
D1, D3, D4, and D6 work in off-state and diodes D2 and D5 act in on-state. converter in a time period. The switching pulses, voltage states for the
The equivalent circuit for this state is shown in Fig. 1b. The voltage on inductors and currents for the diodes and inductors can be found in this
the inductor L1 will be equal to the input source voltage and will charge figure. DT is the time interval that the power switch is activated and T is
linearly. Also, the voltage on capacitor C1 will discharge on inductor L2 a time period.
through this time interval. The voltage on the capacitor C3 will discharge
on the capacitor C5 and capacitors C2 and C4 will discharge in this

DC Gain (M)
70

60 Boost
Cascaded Boost
50 Buck-Boost
Voltage gain (M)

Cuk
40 KY
Proposed
30

20

10

0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Duty cycle

Fig. 3. DC voltage gain comparison between the proposed and other conventional boost converters.

4
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

2.2. Gain calculations for CCM

− IL3 = IC2,on = IC4,on = − Io (20)
Duty cycle is defined for a power switch as below: In this equation, IC2,on and IC4,on are the currents of capacitors C2 and
Ton C4 for the first operation mode. As described for the inductor, a similar
D= (10) law is valid for the capacitor and the average current of a capacitor is
T
zero for a time period of the switching. So, one can write for the
In Eq. (10), Ton is equal to DT in Fig. 2 and is the time interval that the capacitor C4:
switch receives pulses in gate-source pins and is activated. A time period
∫ DT ∫T
of the switching is illustrated by T. Based on the voltage balance theorem
IC4,on dt + IC4,off dt = 0 (21)
in steady-state, the average value of the voltage across an inductor is 0 DT
equal to zero. By applying this law for the inductor L2 and by consid­
The current of C4 for the off-state IC5,off from Fig. 1c can be written by:
eration Eqs. (3) and (6):
( )
∫ DT ∫T IC5,off = − IL3 + IC4,off (22)
VC1 dt + ( − VC2 )dt = 0 (11)
0 DT So, the current of the capacitor C5 in off-state by Eqs. (20)–(22) can
be calculated:
The voltage across the capacitors C1 and C2 can be obtained
respectively as: Io
IC5,off = − (23)
1− D
Vi
VC1 = (12) Also, the current of C3 in on-state can be obtained by:
1− D
Io
VC2 =
DVC1
(13) IC5,on = − IC3,on = (24)
1− D D

By using Eqs. (12) and (13), the voltage across the capacitor C2 can In these equations, IC3, on and IC5, on are the currents of the capacitors
be rewritten as follow: C3 and C5 in on-state (first mode). The current of the inductor L2 by
considering Fig. 1 can be calculated by:
Vi
VC2 = (14) 2+D
(1 − D)2 IL2 = IC2,off + IC3,off + IC4,off + IL3 = Io (25)
1− D
Also by this law for the inductor L2, one can write based on (3) and
In this equation, the IC2,off , IC3,off , and IC4,off are the currents of the
(7):
capacitors C2, C3, and C4 in off-mode respectively. The currents equa­
∫ DT ∫T tions for the diodes D3, D4, D5, and D6 can be found by:
VC1 dt + (VC1 − VC3 )dt = 0 (15)
0 DT Io
ID3 = IC2,off + IL3 = (26)
The voltage across the capacitors C3 and C5 based on Eq. (2) can be 1− D
obtained as:
Io
ID4 = IC3,off = (27)
VC1 Vi 1− D
VC2 = VC5 = = (16)
1 − D (1 − D)2
Io
ID5 = − IC3,on = (28)
According to Eq. (9), the voltage value across the capacitor C4 can be D
obtained by total value of the voltages across the capacitors C3 and C5:
Io
2VC1 2Vi ID6 = − IC5,off = (29)
VC4 = = (17) 1− D
1 − D (1 − D)2
The current for the power switch can be written by Eq. (30):
Based on Fig. 1b and 1c and the described law for the inductor L3:
1 + 2D Vo3 − Vo VC1
2
∫ DT ∫T IM = IL2 − IC2,on − IC4,on = Io = ( 2
) (30)
D(1 − D) VC1 Vo − 2VC1 R
(VC4 + VC2 + VC5 − VC3 − Vo )dt + (VC4 − Vo )dt = 0 (18)
0 DT
Through Eq. (13), IM can be rewritten by:
So for the CCM working mode, the gain of the proposed converter 2

can be presented as: 1 + 2D Vo3 − Vo (1−V D)i 2

IM = IL2 − IC2,on − IC4,on = Io = ( ) (31)
D(1 − D) (
Vo 2+D Vi 2
− 2 (1−V D)i 2
MCCM = = (19) 1− D
)Vo R
Vi (1 − D)2

Fig. 3 presents the gain curves of the proposed converter and the The average value of the input current can be written by:
conventional boost converters such as the KY converter or cascaded ∫ DT
( )
∫T
( ) 2+D
converter with two serial blocks. This figure easily can prove that the Ii = IL2 − IC2,on dt + IL2 − IC2,off dt = Io (32)
(1 − D)2
gain of the proposed converter is considerable against all of these con­
0 DT

verters. This figure presents the voltage gain comparison for the con­ In this equation, Io is the output average current.
verters for the duty ratios 0 < D < 0.8. The figure shows that for the D =
0.5, the proposed converter presents a voltage gain equal to 10, while
the nearest gain belongs to the cascaded boost converter with M = 4. 2.4. Current ripples calculations for the inductors

2.3. Current calculations for the power components The current equations for the inductors can be written for the 0 ≤ t ≤
DT time interval as:
Based on the configuration of the proposed circuit presented in ∫
1 DT
Fig. 1, the current flow through the capacitors C2 and C4 and inductor L3 IL1 (t) = Vi dt + IL1 (0) (33)
L1 0
can be obtained by:

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Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

∫ DT presented by rDS , PRF1 to PRF6 , RC1 to RC6 , and RCO , and rL1 torL3 respec­
1
IL2 (t) = VC1 dt + IL2 (0) (34) tively. In the first step, the dynamic losses are calculated for the power
L2 0
switch. The root mean square (RMS) value of the current follows through
∫ DT the switch is shown by IS,rms :
1
IL3 (t) = (VC4 + VC2 + VC5 − VC3 − Vo )dt+IL3 (0) (35) This current IS,rms , can be written by (47):
L3 0
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ √̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
( )2
∫ ∫
The ripples for the inductor currents can be calculated by Eqs. (36)– 1 DT ( )2 1 DT 1 + 2D
IS,rms = IL2 − IC3,on − IC4,on dt = Io dt
(38): T 0 T 0 D(1 − D)
DVi D(1 − D)Vo Vi Vo − 2Vi2 1 + 2D
ΔIL1 = = = (36) = √̅̅̅̅
D(1 − D)
Io
L1 fs (2 + D)L1 fs (Vi + Vo )L1 fs
(47)
DVC1 D(1 − D)Vo Vi Vo − 2Vi2
ΔIL2 = = = (37) Therefore, the power loss for the switch can be calculated by Eq.
L2 fs (2 + D)L2 fs (VC1 + Vo )L2 fs
(48):
DVi D(1 − D)Vo Vi Vo − 2Vi2 (1 + 2D)2
ΔIL3 = = = (38) 2
PrDS = rDS IS,rms = rDS Io2 (48)
L3 fs (2 + D)L3 fs (Vi + Vo )L3 fs D(1 − D)2
In these equations, ΔIL1 , ΔIL2 , and ΔIL3 are the current ripples of the Also, the switching losses of the switch is obtained by Eq. (49):
inductors L1, L2, and L3 respectively and fs is the switching frequency for ( )2
the power switch. The maximum current ripples for these inductors can VC1 Vi2
PSw = fs CS VS2 = fs CS = fs CS (49)
be calculated by (39)–(41): 1− D (1 − D)2
Dmin Vi,max Dmin (1 − Dmin )Vo CS is the parasitic capacitor value across the power switch and VS is
ΔIL1,max = = (39)
L1 fs (2 + Dmin )L1 fs the voltage across the switch for the off-state. This equation can be
presented according to the gain of the converter MCCM , by the Eq. (50):
Dmin Vi,max Dmin (1 − Dmin )Vo
ΔIL2,max = = (40) (
(MCCM +2)Vo
)2
L2 fs (2 + Dmin )L2 fs PSW = fs CS (50)
4MCCM
Dmin Vi,max Dmin (1 − Dmin )Vo
ΔIL3,max = = (41) By considering the dynamic and switching losses for the total losses
L3 fs (2 + Dmin )L3 fs
of the switch PSwitch , one can write:
ΔIL1,max , ΔIL2,max , and ΔIL3,max are the maximum current ripples for the PSw
inductors L1, L2 and L3 respectively. So, the maximum current for these PSwitch = PrDS + (51)
2
inductors can be obtained through Eqs. (42)–(44):
The RMS current values for the power diodes D1 and D2 are equal to:
ΔIL1 2+D D(1 − D)Vo
IL1,max = IL1,av + = Io + (42) √̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
∫ ( )2 ̅
2 (1 − D)2 2(2 + D)L1 fs 1 T Io Io
ID1,rms = dt = √̅̅̅̅̅̅̅̅̅̅̅̅ (52)
T DT 1 − D 1− D
ΔIL2 2 + D D(1 − D)Vo
IL1,max = IL1,av + = Io + (43) √̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
2 1− D 2(2 + D)L2 fs ∫ ( )2 ̅
1 DT (2 + D)Io (2 + D)Io √̅̅̅̅
ID2,rms = dt = D (53)
ΔIL3 D(1 − D)Vo T 0 1− D 1− D
IL2,max = IL2,av + = Io + (44)
2 2(2 + D)L3 fs Therefore, simply the dynamic losses for these diodes can be ob­
tained by Eqs. (54) and (55):
2.5. Output voltage ripples
Io2
2
(PRF )D1 = RF1 ID1,rms = RF1 (54)
1− D
The output voltage ripple generally can be calculated by Eq. (45):
( )2
Io
ΔVo =
ΔQ 1 ΔIL3 Ts 1
= * * * =
Vo D(1 − D)
(45)
2
(PRF )D2 = RF2 ID2,rms = RF2 (2 + D) (55)
Co Co 2 2 2 8(2 + D)L3 Co fs2 1− D

In (45), ΔQ is the electrical charge across the output capacitor Co . The average value for the currents of the diodes D1 and D2 is:
The minimum value for this capacitor to fix the output voltage is equal ∫ (
1 T Io
)
to: ID1,av = dt = Io (56)
T DT 1 − D
ΔIL3,max Vo Dmin (1 − Dmin )
Co,min = = (46) ∫ DT ( )2 ( )2
8fs ΔVo 8(2 + Dmin )L3 fs2 ΔVo 1 Io Io
ID2,av = (2 + D) dt = D(2 + D) (57)
T 1− D 1− D
In Eq. (46), Dmin is the minimum value of the duty cycle for the CCM
0

operational mode. The power losses for these diodes when are operating in on-state can
be obtained by Eqs. (58) and (59):
2.6. Efficiency calculations (PVF )D1 = VF1 ID1,av = VF1 Io (58)

The main important parameter that should be considered for the ef­ (
Io
)2
ficiency calculations is the internal resistance of the components. Some of (PVF )D2 = VF2 ID2,av = VF2 D(2 + D) (59)
1− D
these components like the power switch and diodes have this resistance
only for the on-state time intervals and some of them lose power for both The effective current for the diodes D3, D4 and D6 are:
on and off-states like the inductors and some the capacitors. The internal
resistance for the power switch, diodes, capacitors, and inductors can be

6
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
)2 ̅
∫ ( √̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅
1 T Io Io √ [ ∫ DT ( )2 ∫T( )2 ]
ID3,rms = ID4,rms = ID6,rms = dt = √̅̅̅̅̅̅̅̅̅̅̅̅ (60) √1 1 D 1
T DT 1 − D 1− D IC3,rms = IC5,rms = √ Io dt + * Io dt
T 0 D DT 1− D D
The dynamic losses for these diodes respectively can be presented by
1
(61)–(63): = √̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅Io (77)
D(1 − D)
Io2
2
(PRF )D3 = RF2 ID3,rms = RF3 (61) And the serial equivalent resistors for the C3 and C5 can be shown
1− D
respectively by:
Io2
2
(PRF )D4 = RF4 ID4,rms = RF4 (62) 2
PRC3 = rC3 IC3,rms = rC3
1
I2 (78)
1− D D(1 − D) o
Io2
2
(PRF )D6 = RF6 ID6,rms = RF6 (63) 1
1− D
2
PRC5 = rC5 IC5,rms = rC5 I2 (79)
D(1 − D) o
The average current for these diodes are equal to:
The current follows from the output capacitor CO for the 0 ≤ t ≤ DT
∫ ( )
1 T Io and DT ≤ t ≤ T time intervals are respectively equal to:
ID3,av = ID4,av = ID6,av = dt = Io (64)
T DT 1 − D
ΔiL3 t ΔiL3
ICo,on = − (80)
The losses of these diodes for the on-state time interval can be DT 2
calculated as:
ΔiL3 (t − DT) ΔiL3
(PVF )D3 = VF3 ID3,av = VF3 Io (65) ICo,off = − + (81)
(1 − D)T 2

(PVF )D4 = VF4 ID4,av = VF4 Io (66) So, the effective current for this capacitor can be obtained as:
D(1 − D)RIo
(PVF )D6 = VF6 ID6,av = VF6 Io (67) ICo,rms = √̅̅̅̅̅ (82)
( 12(2 + D)L3 fs
The effective current value for the D5 is equal to:
The power losses caused by the internal resistance for the CO is:
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ √̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
( )2̅
∫ ∫
1 DT 2 1 DT Io 1 D2 (1 − D)2 R2 Io2
ID5,rms = I C3,on = = √̅̅̅̅Io (68) 2
PRCo = rCo Ico,rms = rCo (83)
T 0 T 0 D D 12(2 + D)2 L23 fs2
The losses on the internal resistance of this diode can be obtained by: The RMS current values for the inductors L1 (IL1,rms ), L2 (IL2,rms )and L3
1 (IL3,rms )and the power losses on these inductors (PrL1 to PrL3 )can be
2
(PRF )D5 = RF5 ID5,rms = RF5 Io2 (69) calculated through the Eqs. (84)–(89) respectively:
D
( )2
The effective current value for the D5 is equal to: 2+D
IL1,rms = Io (84)
∫ ∫ ( ) 1− D
1 DT ( ) 1 DT Io
ID5,av = − IC3,on dt = dt = Io (70)
T 0 T 0 D ( )2
2+D
2
PrL1 = RL1 IL1,rms = RL1 Io2 (85)
The losses for the on-time interval for this diode is obtained by: 1− D
1
2
(PRF )D5 = RF5 ID5,rms = RF5 Io2 (71) 2+D
D IL2,rms = Io (86)
1− D
The average current of the D5 is:
( )2
∫ ∫ ( ) 2+D
1 DT ( ) 1 DT Io
2
PrL2 = RL2 IL2,rms = RL2 Io2 (87)
ID5,av = − IC3,on dt = dt = Io (72) 1− D
T 0 T 0 D
So the losses of this diode for the ON state is equal to: IL3,rms = Io (88)

(PVF )D3 = VF3 ID3,av = VF3 Io (73) 2

PrL3 = RL3 IL3,rms = RL3 Io2 (89)
The effective current value for capacitors C2 and C4 are: By considering all of these losses, the total power losses can be ob­
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
√ [ ∫ DT ∫T( )2 ] √̅̅̅̅̅̅̅̅̅̅̅̅ tained through the equation (90):
√1 D D
IC2,rms = IC4,rms = √ (Io )2 dt + Io dt = Io ∑6 ∑6 ∑6
T 0 DT 1− D 1− D Ploss = PM + (PRF )Da + (PVF )Da + PRCa + PrL1 + PrL2
a=1 u=1 a=1

(74) + PrL3 + PRCo

And the serial equivalent resistance for these capacitors are: (90)

D The classic equation for the efficiency is presented by the equation

2
PRC2 = rC2 IC2,rms = rC2 I2 (75) (91):
(1 − D) o
Po 1
D η= = (91)
PRC4 = 2
rC4 IC4,rms = rC4 I2 (76) Po − Ploss 1 + PPloss
(1 − D) o o

Therefore, the efficiency of the converter is obtained by equation

The effective currents of capacitors C3 and C5 are calculated by:
(92):

7
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

2.7. Voltage ripples calculations for the capacitors

VC2
ΔVC2,cap ΔVC1,ESR Fig. 4 presents the expected voltage ripples across the capacitors C2
to C5. Some of the parameters are shown in these figures that need to
ΔVC1,ESR
ΔVC2 explain. ΔV presents the general magnitude of the ripple for any of the
t capacitors. ΔVC,ESR and ΔVC,cap respectively show the ripple caused by
VC3 the internal resistance of per capacitor and ripples values rooted in
ΔVC3,cap ΔVC3,ESR charging-discharging time intervals for the capacitors. Therefore, the
total ripple value of voltage should be calculated by considering both of
ΔVC3,ESR
ΔVC3 these ripples. For the capacitor C2:
t
VC4 ΔVC2 = ΔVC2,ESR + ΔVC2,cap (96)
ΔVC4,cap ΔVC4,ESR For this capacitor and by considering the ΔVC,ESR , the maximum
ΔVC4,ESR magnitude of this ripple is shown by:
ΔVC4 t ( ) ESRC2 Io
ΔVC2,ESR = ESRC2 ΔIC2 ≅ ESRC2 IC2,off − IC2,on = (97)
VC5 1− D
ΔVC5,ESR here ESRC2 is presented by:
ΔVC5,cap
ΔVC5,ESR tanδC2
ΔVC5 t ESRC2 = (98)
DT T 2π fs
That, tanδC2 is the losses coefficients.
Fig. 4. Voltage waveforms for capacitors C2, C3, C4 and C5.
ΔVC2,cap simply can be written by:

1 IC2,off (1 − D)T DTVo

η= (92) ΔVC2,cap = = (99)
φ D2 (1− D)2 R fs Cs Vi2 C2 RC2
1+ RD(1− D)2
+ rCo 12(2+D) 2 2 2
L3 fs
+ (1− D) 2
RIo2
The same equations can be written for other capacitors. Eqs. (100)–
here φ can be presented by: (113) present the ripple calculations for the capacitors C3 to C5:

D(1 − D)2 ∑6 ΔVC3 = ΔVC3,ESR + ΔVC3,cap (100)

φ = (1 + 2D)2 rDS + D(1 − D)(RF3 + RF4 + RF6 ) + VFu
Io u=1
( ) ESRC3 Io
+ (1 − D)2 RF5 + D2 (1 − D)(rC2 + rC4 ) + (1 − D)(rC3 + rC5 ) + DRL1 ΔVC3,ESR = ESRC3 ΔIC3 ≅ ESRC3 IC3,on − IC3,off = (101)
D(1 − D)
2 2
+ (2 + D) DRL2 + D(1 − D) RL3
( ) ESRC3 Io
(93) ΔVC3,ESR = ESRC3 ΔIC3 ≅ ESRC3 IC3,on − IC3,off = (102)
D(1 − D)
Based on efficiency definition, the efficiency of the proposed con­
verter by considering the parasitic resistances of the components can be tanδC3
ESRC3 = (103)
obtained by: 2π fs

Po Vo Io MCCM (1 − D)2 IC3,on DT TVo

η= = = (94) ΔVC3,cap = = (104)
Pi Vi I i 2+D C3 RC3
The voltage stress on power switch M, can be shown by:
ΔVC4 = ΔVC4,ESR + ΔVC4,cap (105)
VC1
VS = = (1 − D)2 Vo (95) ( ) ESRC4 Io
1− D ΔVC4,ESR = ESRC4 ΔIC4 ≅ ESRC4 IC4,off − IC4,on = (106)
(1 − D)
Eq. (95) illustrates that the voltage stress on the switch is less than
the output voltage and the dynamic losses are lower.

D1
C2
L2 D3
L1
D2
L3

Vin + +
C3
C1 M
Load

C4 CO

D4 D5

C5 D6
+

Fig. 5. The third working state of proposed converter when operates in DCM.

8
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

Vgs DTs (1-D-Dm)Ts The average currents values follow through the diodes D3, D4 and D6
are:
DmTs
VO
ID3,ave = ID4,ave = ID6,ave = (122)
t R
By considering the voltage balance conditions for inductors L2 and L3
IL2+IL3 that guarantee the positive and negative voltages across the inductors to
obtain zero volts as the average voltage for the inductor, the duty cycle
for the DCM working state Dm can be obtained:
t
(2 − MDCM )D2m + Dm D(5 − MDCM ) + 3D2 = 0 (123)
0 DTs (D+Dm)Ts Ts
According to Fig. 6 one can write:
Fig. 6. Voltage across the gate-source pins of the power switch and the currents
of the inductors L2 and L3 for the DCM.
1
ID3,ave + ID4,ave + ID6,ave = Dm ID− Peak (124)
2
tanδC4 In this equation ID− Peak is the total of the peak currents for the diodes
ESRC4 = (107) D3, D4, and D6 and can be calculated as follow:
2πfs
Vin DTs
IC3,on DT TVo ID− = (125)
(108)
Peak
ΔVC3,cap = = Lq
C3 RC3
And Lq is equal to:
ΔVC5 = ΔVC5,ESR + ΔVC5,cap (109)
1 1
Lq = + (126)
( ) ESRC5 Io L2 L3
ΔVC5,ESR = ESRC5 ΔIC5 ≅ ESRC5 IC5,off − IC5,on = (110)
(1 − D) Eqs. (122)–(126) indicate that the voltage gain of the DCM can be
calculated as:
IC5,off (1 − D)T DTVo
ΔVC5,cap = = (111) DDm
C RC MDCM = (127)
3τ
tanδC5
SRC5 = (112) In Eq. (127), R is the load value and τ is equal to:
2πfs
2Lq
IC5,off (1 − D)T DTVo τ= (128)
ΔVC5,cap = = (113) RT
C RC
Eq. (114) presents the voltage ripple for the output capacitor and is 2.9. Controller design
depended on parameters like duty cycle D, the value of the inductor L3,
output capacitor value Co , and the switching frequency fS : A simple sliding mode controller is considered for the proposed
converter to fix the output voltage of the converter under different input
Vo D(1 − D)
ΔVo = (114) voltages and output load values. The state variables for the prototype are
8(2 + D)L3 Co fs2 as follows:
⎡ ⎤
Vref − βVO
2.8. Operation analysis for discontinuous current mode (DCM) ⎡ ⎤ ⎢ ⎥
x1 ⎢ d ⎥
⎢ (V − βVO ) ⎥
Similar operational states can be considered for the discontinuous x = ⎣ x2 ⎦ = ⎢ dt ref ⎥ (129)
⎢∫ ⎥
x3 ⎣ ⎦
current mode (DCM). DCM has an extra working mode that is presented
(Vref − βVO )dt
in this sub-section. For the third working state, all of the switches and
diodes in the switched-capacitor side of the converter are deactivated. In
In this equation, x1 , x2 , and x3 are the voltage error, error dynamics
this operational mode, the currents follow through the inductors are
and integral of the error respectively. Vref and β indicate the reference
fixed and currents for the diodes and the power switch are zero. This
voltage and the ratio of the feedback network for the proposed con­
state can be seen in Fig. 5.
verter. By considering the relation between input and output voltages,
The currents of the diodes D1 to D6 can be presented respectively as
and voltages across the inductors, Eq. (129) can be rewritten as follows:
follows:
⎡ ⎤
x1 = Vref − βVO
ID1 = IL1 − ID2 (115) ⎢ ∫ ⎥
⎢ ⎥
⎢ x2 = βVO + β (VO − Vin )(DTS )dt ⎥
ID2 = IL1 − ID1 (116) x=⎢ ⎢ RL CO L1 CO ⎥
⎥ (130)
⎢ ∫ ⎥
⎣ ⎦
ID3 = IL2 − IC3,off − IC4,off (117) x3 = (Vref − βVO )dt

ID4 = IC3,off (118) Therefore, steady space descriptions can be obtained as follows:
d( ) dVO
ID5 = IC2,on (119) x˙1 = Vref − βVO = x2 →x˙1 = − β = x2 (131)
dt dt
ID6 = IL3 + IC4,off (120) β dVO β − x2 βVO βVin
x˙2 = + (VO − Vin )(DTS ) = +( − )(DTS )
According to these equations, one can write: RL CO dt L1 CO RL C O L1 CO L1 CO
(132)
ID3 + ID4 + ID6 = IL2 + IL3 (121)

9
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

D1
C2
L2 D3
L1
D2
L3

+
Vin + + R1
C3
C1 M

VO

Load
C4 CO

R2
D4 D5

-
C5 D6
+

-KP1× ico ico

-KP1
βVo

+ +

+
+
PWM
β(Vo-Vin) -
βVin Vref

+
β(Vo-Vin)
Vtriangular KP2×x1
KP2 -
x1

Fig. 7. Proposed SMC controller for the converter.

x˙3 = Vref − βVO = x1 (133) Eq. (138) can be summarized as follow:

( )
The general form of steady space matrix is presented by: ( )
u*eq = − iCo βL1 αα12 − RL1CO + αα32 Vref − βVO L1 CO + β(VO − Vin )
⎡ ⎤ ⎡ ⎤
⎡ ⎤ 0 1 0 ⎡ ⎤ 0 0 < ueq = <1
x˙1 ⎢ ⎥ x1 ⎢ βV β(VO − Vin )
1 βVin ⎥
⎢
ẋ = Ax + Bu→⎣ x˙2 ⎦ = ⎢ 0 − 0⎥ ⎢
⎥⎣ x2 ⎦ + ⎢
O
− ⎥
⎥DTS (139)
⎣ RL C O ⎦ ⎣ L1 CO L1 CO ⎦
x˙3 x3
1 0 0 0 Eq. (139) indicates that:
( )
(134) α1 1 α3 ( )
VC = u*eq = − βL1 − i + L1 CO V − βVO + β(VO − Vin )
The law of the SMC indicates the switching function as follow:
α2 RL CO Co α2 ref
{ (140)
1, when S > 0
u= (135) In a similar expression:
0, when S < 0
( )
S is the instantaneous state trajectory (IST) and is equal to: VC = − KP1 iCo + KP2 Vref − βVO + β(VO − Vin ) (141)

(136) By considering the = β(VO − Vin ), the relation between VC and

Vtri
⋀
S = α1 x1 + α2 x2 + α3 x3 = J T x
β(VO − Vin ) is defined. According to the damping factor and the settling
J = [ α1 α2 α3 ] presents the sliding coefficients.
T
time, the SMC coefficients can be calculated. Based on the natural time-
For driving the power switch by the pulse width modulation (PWM) constant τ, TS = 5τs can be evaluated as proper settling time. Therefore:
technique, two control wave VC and triangular wave Vtri are compared.
The switching frequency of the power switch is indicated by the fre­ α1 10 α3 25
= , and = 2 2 (142)
quency of the triangular wave. Through the unstable condition of the α2 TS α2 ζ TS
converter, for the first step, the equivalent control signal ueq is obtained In Eq. (142), ζ is the damping factor. Fig. 7 presents the proposed
and then the PWM is generated by the result of the first step:

( )
[ ]− 1 βL1 α1 1 α3 L1 CO
ueq = − J T B J T Ax = − iCo − (V − βVO ) (137)
β(VO − Vin ) α2 RL CO α2 β(VO − Vin ) ref

For this equation, 0 < ueq < 1. By considering the ueq = 1 − ueq :

[ ( ) ]
βL1 α1 1 α 3 L 1 CO 〈
0 < ueq = 1 − − iCo − (Vref − βVO ) 1 (138)
β(VO − Vin ) α2 RL CO α2 β(VO − Vin )

10
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

converter and controller circuit.

Table 1 presents a comparison between the proposed converter and

8(2 + D)L2 Co fs2

Vo D(1 − D)
(Vi + Vo )L1 fs

Io
Vin

Vi Vo − 2Vi2
some of the well-known DC-DC power boost converter structures. In this

(1 − D)2 Vo

D(1 − D)
Proposed

1 + 2D
(1 − D)2
table, the number of the components, the DC voltage gain, the voltage

2+D

1− D
and current stresses across some of the switching components and the

Io

√̅̅̅̅
3
6
6
1
input inductor and output diode’s currents are presented. Results show
that the proposed circuits in [44] and [46] use the maximum number of

2(1 − D)Lf 1 + n
Vin
the inductors and diodes. The proposed converter since applies a

)
switched-capacitor block uses the maximum number of the capacitors
and the circuit in [44] and [45] have three power switches in their to­

D
pologies. Totally the circuits in [42] and [43] have eight components

)Vin
while the proposed topology in [44] includes 22 components. Other

+
(1 + n)(1 + nD)
(1 + D)4 R 2Lf
references propose elements numbers from 10 to 16. The proposed
(1 + nD) D

(1 − D)2 R
+
converter in this study has 16 components totally. For a power converter
(1 − D)2

(1 − D)2

(1 − D)2
structure, some of the parameters that should be considered are the
1 + nD

nDVin
Vin
[46]

number of the components, the voltage, and current stresses across the

Vin
Lf
6
3
5
1

( components, the voltage ripple across the output capacitor, the current
ripple of the input current, gain of the converter and the efficiency. Also,
√̅̅̅
Vin(1 − d)d d
(n + 1)√̅̅̅3Lf

the control of the converter will be simpler when the structure includes
√̅̅̅
Vin(n)d d

Vin(n)d d
1 − D √̅̅̅

fewer numbers of the switches. It should be considered that it is

3Lf

3Lf
√̅̅̅

√̅̅̅
1− D
n+1

impossible to have all of these features in a converter and designs should

CfVo
[45]

Vin

DIO
4
2
1
3

be done according to the existing conditions. This means sometimes the

gain of the converter is important but somewhere the input voltage is
IO

large enough so there is no need to have a high gain structure and there
( − D)(3D + (n + 1) − 1)

the voltage and current stresses and efficiency are the main concerns.
Io(1 + n) 26 − 14D
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Vo

In the proposed converter in this study, although topology includes

3(1 − D)Cf
( − D)(3D − 1)

12(1 − D)

higher numbers of the components compared with topologies in [39–43]

3Lf(n + 1)

√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Io 10 − 14D

or [45] and [46], some of the valuable parameters like the voltage gain
6(1 − D)

and voltage stresses across the main power switch is considerably more
1− D

1− D
n+1
[44]

Vin

desirable. These specifications guarantee the reliability of the topology

2
3
2
3
7
3
9
3

and make the converter ready to be used in PV applications since nor­

mally high gain circuits ae used in PV utilization because the generated
Io
Io

5 − 12D + 8D2

voltage of these panels is below the 50VDC normally in the best oper­
2 − 5D + 4D2

Io

1 − 2D

ational condition under proper temperatures and irradiances.

Vin (1 − D)
1 − 2D
VO − Vin
2(1 − D)

2(1 − D)
(1 − 2D)

1 − 2D

1 − 2D

Fig. 8a illustrates the voltage gain for all of the presented topologies
[43]

in Table 1. Results show that the proposed converter presents the highest
2
3
2
1

DC voltage gain after the duty cycle D = 0.3. Although the gain of the
circuits in [42] and [43] is being more than other converters between
2π LCf
fo = √̅̅̅

the 0.4 < D < 0.6, this range of the duty cycle should be avoided to be
1

applied for these converters. This caused by the (1 − 2D) term in the
denominator of the gain equation in these converters. Reaching to high
Io
VO Dπ2 fo2

(1 − D)2
2D

DC gain around the D = 0.5 imposes a sudden and large impulse voltage
1 − 2D

1 − 2D
̅
IO D
1 −√̅̅̅
2f
[42]

VoD
1

across the many of the power components that easily can harm these
Lf
Vo
2
3
2
1

elements. Fig. 8b presents a comparison curve for the gain of the pre­
sented converters. The distinguished specification of the proposed con­
+ )
1− D D
1

verter is the voltage stress on the main power switch. As can be seen,
ΔVCin + ΔVCo
2Rds + Rd

where the converters in [42] and [43] endure a voltage closed to output
√̅̅̅̅ 2
VO + Vin

voltage across their main power switch, the proposed converter gives
IO D(
3+D
1− D

1− D
4

CfVo
[41]

2Io

very smaller voltage stress for the main power switch. This figure shows
2
3
3
2

that the stress of the main power switch approximately remains the same
Comparıson for proposed and other Boost converters.

for all amounts of the duty cycles. Especially for the PV panels, the high
2+D
1− D

2+D
VinD

VinD
[40]

VO

Lf

Lf
Cf

gain applications are needed. Therefore, sometimes it is necessary to

IO

IO
2
5
4
1

switch the power MOSFET with higher duty cycles. The figure shows
√̅̅̅̅̅̅̅̅̅̅̅̅
5− D
Iin (1 − D)

Iin (1 − D)

that for D > 0.6, the proposed converter receives the minimum stresses
4
2Cf

across the power switch. This curve also shows that for smaller duty
1− D

2
VinD
[39]

Lf
VO
2

Iin

cycles, the voltage stress is completely lower than the output voltage.
2
3
4
2

For a comparison, 24VDC as the input voltage has been considered as the
Voltage stress on output capacitor

same input voltage for all converters, and the output voltages of the
Current stress on input inductor

Current stress on output diode

Current stress on main switch

converters were considered by data of Table 1 for different duty cycles.

Voltage stress on switches

The voltage stress for this level of the voltage is around 50VDC for D <
0.6 and 64.8VDC for D = 0.7.
Capacitors numbers
Inductors numbers

Switches numbers

Fig. 9 shows the efficiency comparison curves for all topologies in

Diodes numbers

Table 1. For obtaining the curves, the input and output voltages are fixed
Voltage Gain
Parameter

at the 24, and 240VDC and loads are changed. Therefore, the different
Table 1

amounts of the output power are obtained. Since the simulation is done
in MATLAB/SIMULINK, easily the average currents at the input and

11
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

Voltage gain
45
40
35
30
Gain

25
20
15
10
5
0
0.1 0.2 0.3 0.4 0.45 0.475 0.5 0.55 0.575 0.6 0.7
Duty cycle (D)

[45] [46] [47] [48] [49] [50] [51] [52] Proposed

(a)

Voltage stress on main switch

300

250
Voltage (V)

200

150

100

50

0
0.1 0.2 0.3 0.4 0.45 0.475 0.5 0.55 0.575 0.6 0.7
Duty cycle (D)

[45] [46] [47] [48] [49]

[50] [51] [52] Proposed

(b)
Fig. 8. Comparison for (a) DC Voltage gain and (b) voltage stress across the switch between the proposed and structures in Table 1.

output sides are monitored and then the power at the input and output 3.1. Components values calculations
sides are calculated. Then the efficiency is obtained. This figure shows
that for the lower amounts of the output power, normally the efficiency Eqs. (39)–(44) present that forD = 0.5 and fs = 50 kHz as the
is less. This is reasonable and comes back to the fixed power losses in a switching frequency, and around 2.5 A current ripples for the inductors
converter. Around 100 W, all of the converters reach initial real effi­ L1 and L2, the values of these inductors should be selected around
ciencies. The proposed converter reaches to the highest efficiency 200μH:
around the 150 W and after that can fix this parameter. The highest DC
Dmin Vi,max Dmin (1 − Dmin )Vo 0.5 × 0.5 × 240
gain means the lower load currents at the output side and higher ΔIL,max = = →L =
Lfs (2 + Dmin )Lfs (2 + 0.5) × 2.5 × 50k
efficiency.
= 200 μH (143)
3. Sımulatıon and hardware test results Inductor L3 is supplying the load current and the ripple is less for this
inductor compared to inductors L1 and L2. Eqs. (42)–(44) show the
To confirm the theoretical investigations, a prototype with around currents of the inductors. Therefore, a smaller inductor around 100μH
300 W is tested. The same values for the components are chosen for the will be a proper value for this inductor. Eq. (46) illustrates that for
simulation and experimental hardware tests. These parameter values around 1% of voltage ripple for the output capacitor, a capacitor with a
can be found in Table 2. Input voltage is selected to be equal to 24VDC minimum 5 μF capacity should be applied. For fewer values of the
and D = 0.5. According to Eq. (19), the output voltage around 240VDC fluctuations, higher amounts of the capacitors can be selected. In this
should be obtained. study, a capacitor with 470 μF capacity for Co is used:

12
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

Efficiency

98

93

Efficiency
88

83

78

73

68
20 50 100 150 200 250 300
Output power (W)

[45] [46] [47] [48] [49]

[50] [51] [52] Proposed

Fig. 9. Efficiency of the proposed converter and comparison with other presented topologies in Table 1.

coefficients can be obtained. The coefficients Kp1 and Kp2 can be calcu­
Table 2 lated as follows:
Components values. ( )
α1 1 α3
Components and parameters Value for simulation Value for hardware test Kp1 = βL1 − , and Kp2 = L3 CO (148)
α2 RCO α2
Input voltage Vin 24VDC 24VDC
Output Voltage VO 240VDC 240VDC In Eq. (148), β is defined by:
Output power PO 300 W 300 W
Inductors L1, L2 200 μH 200 μH Vref
β= (149)
Inductor L3 100 μH 100 μH Vout
Capacitors C1, C2, C3, C4, C5 100 μF 100 μF
Capacitor CO 470 μF 470 μF Since the control process will be done by a microcontroller board, the
Diodes D1-D6 According to DSEP15-06A Vref
Vref should be selected smaller than 5VDC. By β = Vout
= 16, since the
DSEP15-06A features
Power MOSFET According to IXTQ460P2 Vout = 240VDC, the Vref = 4VDC.
IXTQ460P2 features
Switching Frequency fs 50 KHz 50 KHz
3.2. Simulation results

Fig. 10a illustrates the I-V and P-V features of the applied PV panel.
ΔIL3,max Vo Dmin (1 − Dmin ) 240 × 0.5 × 0.5
Co,min = = = This figure shows the specifications of the panel according to the
8fs ΔVo 8(2 + Dmin )L3 fs2 ΔVo 8 × (2.5) × 100μ × 2500M × 2.4
MATLAB/SIMULATION results. The commercial name of this panel is
= 5 μF JIANGYIN HR-200 W-24 V. As can be seen, one panel at the 25 ◦ C of
(144) temperature can generate a power value around 200 W. for this purpose,
the panel needs to generate around 28VDC. The maximum power gen­
Eqs. (99)–(114) are presented to calculate the values of the capaci­
eration in a PV panel depends on parameters like temperature and
tors C1 to C5. The general form of these equations can be presented as:
irradiation. It means based on different weather conditions different
DVo ΔVC,cap 0.5 × 240 levels of the voltages can be generated. The important issue when a PV
ΔVC,cap = → = 0.1 = (145)
RCf Vo 10 × C × 50k panel is used is the maximum power point tracking (MPPT). It guaran­
tees that for per time, the proposed circuit works under the maximum
Since the values of the components should be selected under the
power of the PV panel. Fig. 10b presents the proposed algorithm for the
worst operational conditions, by considering = 0.1 and R = 10 Ω,
ΔVC,cap
Vo MPPT. This algorithm is planned according to the I-V and P-V features of
the values of these capacitors will be equal to 100 μF. The reason why the applied PV panel. Fig. 10b shows that for the first step, the instant
small values are selected for R is that the output current and power and voltage and current values of the panel are measured. Therefore, the
current and voltage fluctuations in the components reach their instant power value can be calculated. The power value is compared
maximum value and design should be done under the worst working with the power of the previous moment. Now totally four different ap­
conditions. proaches can exist. If the measured power and voltage value are more
For the controller design, since the switching frequency is selected than previous values or the power is less and voltage is more than the
fS = 50 kHz, so we can have: previous values, the reference voltage for the PV side should be
rad 1 1 decreased and if the measured power is more and the voltage is less than
ωn = 2πf = 264k →TS = = = 5.35 μs (146) the previous values for these parameters or both the power and voltage
sec ζωn 0.707 × 264k
values are less than the previous values of these parameters, the refer­
According to SMC rules, the relation between coefficients α1 , α2 and ence voltage should be increased. More detail about the algorithm can
α3 can be presented by: be found in [20].
α1 10 α1 10 α3 25 α3 25 MATLAB/SIMULINK is used for the simulation. Fig. 11a presents the
= → = , and = → = (147) input and output voltages of the converter under 50% of the duty cycle,
α2 TS α2 5.35μ α2 ζ2 TS 2 α2 (0.707)2 (5.35μ)2
24 VDC as the input voltage. The result for the gain of the converter
This means if select one of coefficients α1 , α2 and α3 , other confirms the equation (19) since around 240VDC is obtained at the

13
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

Array type: Jiangyin Hareon Power HR-200W-24V;

10
Current (A)

25 oC
5
45 oC
0
0 5 10 15 20 25 30 35 40
Voltage (V)
300
25 oC
Power (W)

200

100
45 oC
0
0 5 10 15 20 25 30 35 40
Voltage (V)

(a)

D1
C2
L2 D3
L1
D2
L3

+
+ R1
C3
C1 M

VO

Load
Yes C4 CO
Vref=Vref-ΔV

Yes R2
V(t)>V(t-1) D4 D5
Power measurement
V(t)

-
Vref=Vref+ΔV C5 D6
Voltage No
P(t)=V(t).I(t) P(t)>P(t-1) t=t+1 +
measurement
Power
Yes
-KP1× ico ico
I(t) comparison Vref=Vref-ΔV -KP1
Current V(t)>V(t-1) βVo
+ +

measurement No
+

PWM
β(Vo-Vin) -
Vref=Vref+ΔV Vref
No βVin
+

Vtriangular KP2×x1
KP2 -
x1
β(Vo-Vin)

(b)
Fig. 10. (a) I-V and P-V characteristics of the JIANGYIN HR-200 W-24 V PV panel and (b) proposed converter with MPPT algorithm for PV side.

14
Q. Qi et al.
Fig. 11. The input and output (a) voltage, and (b) current waveforms under D = 0.5 at the Po = 170W. (c) The input and output currents under D = 0.5 and Po =
300W and (d) input and output voltages under D = 0.8 and Po = 300W.
Fig. 12. Voltage waveforms for the inductors L1, L2 and L3.
output side of the converter. For 24VDC and 240VDC as the input and
output voltages, 0.5 for the duty cycle, and 170 W as the output power, a
current around 0.7A for the load side is expected. Fig. 11b shows the
input and output current. The average value of the input current ac­
cording to equation (32) is equal to 7A and based on Eq. (39) around
2.4A ripple is obtained for the input current. Fig. 11c illustrates the input
and output currents under 300 W of the output power. With a fixed
240VDC at the output nodes, a current with around 1.25 A is expected to
follow through the load while according to Eq. (32), with D = 0.5, the
average value of the input current is expected to obtain around 12.5 A.
This figure confirms this theoretical result. Fig. 11d presents the output
voltage of the presented converter under 0.8 of the duty cycle. Eq. (19)
shows that ideally around 1680VDC should be obtained, but because of
the voltage drops across the components and the reaction of the parasitic
parameters in the converter’s elements, a voltage around 1550VDC has
been gained. This voltage gain is considerable since the serial and par­
allel connections for the PV panels should be considered to operate
under higher voltages and output powers.
Fig. 12 shows the voltage waveforms across the inductors. As can be
seen and based on the presented theoretical investigations for the
15
International Journal of Electrical Power and Energy Systems 125 (2021) 106496
operating of the converter in on and off-states, all of the inductors charge
and discharge simultaneously. The charging and discharging of the in­
ductors will occur in the no and off-states respectively.
Fig. 13a and b presents the voltage waveforms across the diodes in
the converter circuit. The state of the diodes theoretically has been
presented in Figs. 1b, 1c and 2. From Fig. 13a, the theorem that at the
same time only one of the diodes D1 and D2 will be activated is
confirmed and according to the presented results in Fig. 13b, the theo­
rem that for time intervals that the diode D5 is activated the diodes D3,
D4 and D6 will be deactivated and vice versa is approved.
Fig. 14a and b illustrates the obtained voltage waveforms across the
capacitors C1 to CO. as can be seen by these figures, the voltage across
the output capacitors is closed to the output voltage, voltages across the
capacitors C3 and C5 are approximately equal and the voltage across the
capacitors C4 is equal to the total of voltages across the capacitors C3 and
C5. By this result, Eq. (9) is confirmed.
3.3. Experimental results
Fig. 15a shows the prototype hardware and Fig. 15b–i presents the
experimental test results. For the implementation, the input side of the
converter is connected to a parallel connection of the two JIYANGYIN
HAREON HR-200 W-24 PV panels. To fix the output voltage of these
panels at the 24VDC, the presented algorithm in Fig. 10b is applied. The
components values and features are selected according to the presented
calculation and results in Section 3.1. It is planned to obtain to 240VDC
at the output nodes of the converter. Fig. 15b presents the voltages at the
gate-source and drain-source pins. The output voltage of the TLP350
power MOSFET driver is about 20 V peak to peak. This integrated circuit
(IC) is connected to the output of the controller to switch the power
MOSFET. As can be seen in this figure for Vin = 24VDCand Vout =
240VDC, around 46 V is obtained across the drain-source pins. This
value of the voltage stress is considerable and easily can approve the
presented facts in section 2 for the theoretical analysis. The input and
output voltages are shown in Fig. 15c. Around 232VDC is obtained at the
Q. Qi et al.
Fig. 13. Voltage waveforms across the power diodes (a) D1, D2 and (b) D3-D6.
Fig. 14. Voltage waveforms across the capacitors (a) C1, CO and (b) C2-C5.
output nodes. The voltages across the inductors L1 to L3 are illustrated in
Fig. 15d and e. These two figures present some of the most important
results that they are the fundamental issues that have been considered
for theoretical analysis. Based on these results, all of the inductors are
charged and discharges simultaneously. The charging process will be
done when the power switch is activated and discharging is done for
deactivating the time interval of the power switch. Fig. 15f, g and h show
the voltage waveforms across the anode–cathode pins of the power di­
odes. Fig. 15f approves that for any time interval only one the power
diodes D1 and D2 can be activated. The voltage across these diodes for
deactivation time interval reaches to − 45 V. Fig. 15g confirms that both
diodes D3 and D4 are activating and deactivating simultaneously and
Fig. 15h shows that the diodes D5 and D6 are working asynchronously.
Fig. 15i, j, and k show the voltages across the input, output and snubber
capacitors. The interesting fact of the proposed converter is that the
voltage on capacitor C4 is equal to the total of voltages on capacitors C3
and C5 and this result confirms all mathematical and simulation results.
Although an oscillating voltage is obtaining across the capacitor C1, after
passing through the capacitors C3, C4 and C5, a fixed voltage is obtained
at the end nodes of the converter. Fig. 15i shows the input inductor
current. A ripple around 3A is reported by this figure. The ripple of this
current for the simulation, based on Fig. 11b is 2.2A. The average cur­
rent for both simulation and hardware tests is around 7A which shows a
good overlap and confirmation.
Fig. 16 presents the results of the hardware test under D = 0.75 and
D = 0.80 and also the reaction of the controller when the second load is
connected or disconnected at the end nodes of the converter. For this
test, the input voltages set on 10VDC. The gate-source and drain-source
voltages of the converter under D = 0.75 is shown in Fig. 16a. Around
30 V peak to peak as the voltage across the drain-source pins is obtained.
This confirms the presented equations in Table 1 and Fig. 8. Fig. 16b and
c shows the voltages across the diodes D1-D2 and D5-D6 of the converter
at this duty cycle.
16
International Journal of Electrical Power and Energy Systems 125 (2021) 106496
As can be seen, the diodes D1 and D2 and also diodes D5 and D6
operates asynchronously. These results approve the presented theoret­
ical investigations in Section 2 and presented simulation and experi­
mental results in Section 3. Fig. 16d shows the output voltage of the
converter with Vin = 10VDC and D = 0.8. according to Eq. (19), around
700VDC is expected to be obtained at the load side. This figure shows
that a DC voltage with around 680VDC amplitude with the peak to peak
30 V ripple is obtained. This result is considerable since the converter
can operate in high gain applications. The ripple of the output voltage
can be less by applying the controller for this level of the voltage.
Fig. 16e and f shows the states of the output voltages and currents when
the second load is connected or disconnected. A resistive 350 Ω load is
connected at the first step. Then, the same load is connected and the
reaction of the controller is investigated. For these tests, the input and
output voltages are considered to be equal to 24VDC and 240VDC
respectively. Fig. 16e shows that at the connection moment an overshoot
occurs. The reaction of the controller is quick enough and fixes the
current and voltage during a short time. The amplitude of the overshoot
can be improved with more accurate mathematical modeling for SMC. A
periodic connection and disconnection of the second load with 10 kHz
frequency and the reaction of the controller is evaluated in Fig. 16f. The
overshoot in voltage reaches to around 80 V but the current station is
more proper.
Fig. 17 presents the efficiency curves for the simulation and hard­
ware tests. The main parameter that directly impact the efficiency is the
internal resistance of the components. Especially the resistance of the
inductors, power switch, and diodes are effective. The voltage drops
across these resistors, not only causes to obtain less voltage gain but also
directly decreases the efficiency. Many of the parasitic capacitors
especially when the switching frequency considers to be more will be
made across the different pins of the semiconductor devices and
generate more power losses. Therefore, the difference between the
simulation and experimental results is reasonable.
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

Fig. 15. The results of the implemented prototype. (a) Hardware, (b) voltage across the G-S and D-S pins of the switch, (c) input and output voltages, (d) VL1 and VL2
and (e) VL2 and VL3, (f) VD1 and VD2, and (g) VD3 and VD4, and (h) VD5 and VD6, and voltages on capacitors (I) VC1 and VC2, (j) VC3 and VC4, (k) VC5 and VCo and (i)
input current.

17
Q. Qi et al. International Journal of Electrical Power and Energy Systems 125 (2021) 106496

Fig. 16. The results of the implemented prototype. (a) Voltage across the G-S and D-S pins of the switch under D = 0.75, (b) VD1 and VD2 under D = 0.75, (c) VD5 and
VD6 under D = 0.75 (d) output voltage under D = 0.8, (e) output current and voltage when load changes (f) output current and voltage when load changes frequently.

can give a higher DC gain and work under fewer duty cycles. Operating
Efficiency with low values of the duty cycles directly decreases the dynamic losses in
98 the circuit and give higher efficiencies. The voltage stresses across the
power semiconductors especially power switch is in a reverse relation­
96
ship with the duty cycle and mitigated voltage stress is performed by the
94
proposed switched-capacitor block. Only one power switch is used in this
Efficiency (%)

92 structure that needs a simpler controller. More than one switch needs to
90 more complicated controller functions and causes more implementation
88 problems. The reaction of the circuit and proposed sliding mode
86 controller under the CCM and DCM working conditions are analyzed and
84 the voltage and currents of the components are investigated mathemat­
ically and practically by a 300 W implemented hardware.
82
80
78 Declaration of Competing Interest
20 50 100 150 200 250 300
Output power (W) The authors declare that they have no known competing financial
Simulation Implementation interests or personal relationships that could have appeared to influence
the work reported in this paper.
Fig. 17. Efficiency of the proposed DC-DC converter under the simulation and
experimental tests for PO = 300 W.
Acknowledgement

4. Conclusion This work was supported by VILLUM FONDEN under the VILLUM
Investigator Grant (no. 25920): Center for Research on Microgrids
In this study, a high-voltage gain DC-DC boost converter is presented. (CROM).
A switched-capacitor block is activated between the power switch and the
output load and decrease the voltage stress across the power switch. The
Appendix A. Supplementary material
states of this block for both ON and OFF modes of the power switch are
analyzed. For the 80% of the duty cycle, the proposed converter can
Supplementary data to this article can be found online at https://doi.
generate a voltage with 70 and 68 times greater than the input side
org/10.1016/j.ijepes.2020.106496.
voltage theoretically and in implementation respectively. This feature
prepares the converter to be applied in PV applications since the gener­
ated voltage of these panels is less than 50VDC normally. According to the References
results, the proposed converter in comparison with the conventional
[1] Alanazi Mohana, Mahoor Mohsen, Khodaei Amin. Co-optimization generation and
boost, buck-boost, Cuk, KY, and all the structures presented in Table 2, transmission planning for maximizing large-scale solar PV integration. Int J Electr
Power Energy Syst 2020;118. https://doi.org/10.1016/j.ijepes.2019.105723.

18
Q. Qi et al.
[2] Ghaderi D, Molaverdi D, Kokabi A, Papari B. A multi-phase impedance source
inverter with an improved controller structure. Electr Eng 2020;102(2):683–700.
https://doi.org/10.1007/s00202-019-00903-9.
[3] Li S, Subramaniam U, Yang G, Ghaderi D, Rajabiyoun N. Investigation of the
thermal loading and random vibration influences on fatigue life of the solder joints
for a metal-oxide-semiconductor-field-effect transistor in a DC-DC power boost
converter. IEEE Access 2020;8:64011–9. https://doi.org/10.1109/
ACCESS.2020.2985320.
[4] Ghaderi D. An FPGA-based switching photovoltaic-connected inverter topology for
leakage current suppression in grid-connected utilizations. Int J Circ Theor Appl
2020:1–20. https://doi.org/10.1002/cta.2844.
[5] Ghaderi Davood, Padmanaban Sanjeevikumar, Maroti Pandav Kiran,
Papari Behnaz, Holm-Nielsen Jens Bo. Design and implementation of an improved
sinusoidal controller for a two-phase enhanced impedance source boost inverter.
Comput Electr Eng 2020;83. https://doi.org/10.1016/j.
compeleceng.2020.106575.
[6] Cheng Zhiping, Li Zhongwen, Li Shuihui, Gao Jinfeng, Si Jikai, Das Himadry
Shekhar, Dong Weizhen. A novel cascaded control to improve stability and inertia
of parallel buck-boost converters in DC microgrid. Int J Electr Power Energy Syst
2020;119. https://doi.org/10.1016/j.ijepes.2020.105950.
[7] Hang L, Subramaniam U, Bayrak G, Moayedi H, Ghaderi D, Minaz MR. Influence of
a proposed switching method on reliability and total harmonic distortion of the
quasi Z-source inverters. IEEE Access 2020;8:33088–100. https://doi.org/
10.1109/ACCESS.2020.2973797.
[8] Prabhakaran P, Agarwal V. Novel boost-SEPIC type interleaved DC–DC converter
for mitigation of voltage imbalance in a low-voltage bipolar DC microgrid. IEEE
Trans Ind Electron 2020;67(8):6494–504. https://doi.org/10.1109/
TIE.2019.2939991.
[9] Zhang Y, et al. Wide input-voltage range boost three-level DC–DC converter with
quasi-Z source for fuel cell vehicles. IEEE Trans Power Electron 2017;32(9):
6728–38. https://doi.org/10.1109/TPEL.2016.2625327.
[10] Azer P, Emadi A. Generalized state space average model for multi-phase
interleaved buck, boost and buck-boost DC-DC converters: transient, steady-state
and switching dynamics. IEEE Access 2020;8:77735–45. https://doi.org/10.1109/
ACCESS.2020.2987277.
[11] Du H, Huo Z. PSM control technique for primary-side regulating fly-back
converters. IET Power Electron 2018;11(3):531–8. https://doi.org/10.1049/iet-
pel.2017.0332.
[12] Wu B, Li S, Ma Smedley K. A new single-switch isolated high-gain hybrid boosting
converter. IEEE Trans Ind Electron 2016;63(8):4978–88. https://doi.org/10.1109/
TIE.2016.2554542.
[13] Sravan Kumar SLV, Ravi Sankar Reddy N, Vijay Kumar M, Voltage mode control of
integrated boost series parallel fly-back converter for energy storage applications.
Energy Procedia 2017; 117: 62–70. https://doi.org/10.1016/j.egypro.2017.05.10
7.
[14] Pandey R, Singh B. A power-factor-corrected LLC resonant converter for electric
vehicle charger using cuk converter. IEEE Trans Ind Appl 2019;55(6):6278–86.
https://doi.org/10.1109/TIA.2019.2934059.
[15] Ma W, et al. Hopf bifurcation and its control in the one-cycle controlled cuk
converter. IEEE Trans Circ Syst II: Express Briefs 2019;66(8):1411–5. https://doi.
org/10.1109/TCSII.2018.2880868.
[16] Choudhury Tanmoy Roy, Nayak Byamakesh, Santra SubhenduBikash. Investigation
of voltage stress on a single switch boost-fly-back integrated high gain converter
with light load condition. Ain Shams Eng J 2019;10(1):217–26. https://doi.org/
10.1016/j.asej.2018.10.009.
[17] Winder Steve. Chapter 9 – Fly-back converters and isolated PFC Circuits. In:
Winder Steve, editor. Power supplies for LED driving (2nd ed.). Newnes; 2017. p.
189–201 [ISBN 9780081009253]. https://doi.org/10.1016/B978-0-08-100925-
3.00009-4.
[18] Narayana CL, Suryawanshi HM, Reddy P Vijaya Vardhan, Nachankar P. A High
Gain soft-switching quintupler rectifier and coupled inductor integrated F1y-back
converter for DC microgrid. In: 2020 IEEE International Conference on Power
Electronics, Smart Grid and Renewable Energy (PESGRE2020), Cochin, India;
2020. p. 1–6. https://doi.org/10.1109/PESGRE45664.2020.9070576.
[19] Chen C, Li J, Gao S, Ma Y. Design of staggered fly-back single-phase photovoltaic
grid-connected micro-inverters. In: 2019 IEEE 3rd Information Technology,
Networking, Electronic and Automation Control Conference (ITNEC), Chengdu,
China; 2019. p. 1793–8. https://doi.org/10.1109/ITNEC.2019.8729402.
[20] Huang R, Hong F, Ghaderi D. Sliding mode controller-based e-bike charging station
for photovoltaic applications. Int Trans Electr Energ Syst 2020. https://doi.org/
10.1002/2050-7038.12300.
[21] Ghaderi D, Maroti PK, Sanjeevikumar P, Holm-Nielsen JB, Hossain E, Nayyar A.
A modified step-up converter with small signal analysis-based controller for
renewable resource applications. Appl. Sci. 2020;10:102.
[22] Bayrak G, Ghaderi D. An improved step-up converter with a developed real-time
fuzzy-based MPPT controller for PV-based residential applications. Int Trans Electr
Energ Syst. 2019:e12140. https://doi.org/10.1002/2050-7038.12140.
19
International Journal of Electrical Power and Energy Systems 125 (2021) 106496
[23] Jiang W, Chincholkar SH, Chan C. Investigation of a voltage-mode controller for a
DC-DC multilevel boost converter. IEEE Trans Circ Syst II: Express Briefs 2018;65
(7):908–12. https://doi.org/10.1109/TCSII.2017.2723660.
[24] Chincholkar SH, Jiang W, Chan C. An Improved PWM-based sliding-mode
controller for a DC–DC cascade boost converter. IEEE Trans Circ Syst II: Express
Briefs 2018;65(11):1639–43. https://doi.org/10.1109/TCSII.2017.2754292.
[25] Madouh Jamal, Ahmed Nabil A, Al-Kandari Ahmad M. Advanced power
conditioner using sinewave modulated buck–boost converter cascaded polarity
changing inverter. Int J Electr Power Energy Syst 2012;43(1):280–9. https://doi.
org/10.1016/j.ijepes.2012.05.002.
[26] Ghaderi D, Bayrak G. A novel step-up power converter configuration for solar
energy application. Elektronika Ir Elektrotechnika 2019;25(3):50–5. https://doi.
org/10.5755/j01.eie.25.3.23676.
[27] Lee SS, Bak Y, Kim S, Joseph A, Lee K. New family of boost switched-capacitor
seven-level inverters (BSC7LI). IEEE Trans Power Electron 2019;34(11):10471–9.
https://doi.org/10.1109/TPEL.2019.2896606.
[28] Ghaderi D, Bayrak G. Performance Assessment of a High-Powered Boost Converter
for Photovoltaic Residential Implementations. Elektronika Ir Elektrotechnika 2019;
25(6):40–7. https://doi.org/10.5755/j01.eie.25.6.24825.
[29] Xu H, Chen D, Xue F, Li X. Optimal design method of interleaved boost PFC for
improving efficiency from switching frequency, boost inductor, and output voltage.
IEEE Trans Power Electron 2019;34(7):6088–107. https://doi.org/10.1109/
TPEL.2018.2872427.
[30] Yao J, Zheng K, Abramovitz A. Small-signal model of switched inductor boost
converter. IEEE Trans Power Electron 2019;34(5):4036–40. https://doi.org/
10.1109/TPEL.2018.2875438.
[31] Spiazzi G. Analysis and design of the soft-switched clamped-resonant interleaved
boost converter. CPSS Trans Power Electron Appl 2019;4(4):276–87. https://doi.
org/10.24295/CPSSTPEA.2019.00026.
[32] Ghaderi D, Celebi M, Minaz MR, Toren M. Efficiency improvement for a DC-DC
quadratic power boost converter by applying a switch turn-off lossless snubber
structure based on zero voltage switching. Elektronika Ir Elektrotechnika 2018;24
(3):15–22. https://doi.org/10.5755/j01.eie.24.3.20977.
[33] Frivaldský Ing Michal, Drgoňa Peter, Špánik Pavol. Experimental analysis and
optimization of key parameters of ZVS mode and its application in the proposed
LLC converter designed for distributed power system application. Int J Electr
Power Energy Syst 2013;47:448–56. https://doi.org/10.1016/j.
ijepes.2012.11.016.
[34] Ueda H, Koizumi H. Class-E2 DC-DC converter with basic Class-E inverter and
Class-E ZCS rectifier for capacitive power transfer. IEEE Trans Circ Syst II: Express
Briefs 2020;67(5):941–5. https://doi.org/10.1109/TCSII.2020.2981131.
[35] Park M, Baek J, Jeong Y, Moon G. An interleaved totem-pole bridgeless boost PFC
converter with soft-switching capability adopting phase-shifting control. IEEE
Trans Power Electron 2019;34(11):10610–8. https://doi.org/10.1109/
TPEL.2019.2900342.
[36] Wang Y, Song H, Xu D. Soft-switching bidirectional DC/DC converter with an LCLC
resonant circuit. IEEE J Emerg Sel Top Power Electron 2019;7(2):851–64. https://
doi.org/10.1109/JESTPE.2019.2904535.
[37] Tseng Sheng-Yu, Hsu Chih-Yang. Interleaved step-up converter with a single-
capacitor snubber for PV energy conversion applications. Int J Electr Power Energy
Syst 2013;53:909–22. https://doi.org/10.1016/j.ijepes.2013.06.007.
[38] Muhammad M, Lambert S, Armstrong M, Pickert V. High step-up interleaved boost
converter utilising stacked half-bridge rectifier configuration. J Eng 2019;6 2019
(17):3548–52. https://doi.org/10.1049/joe.2018.8015.
[39] Yi J, Choi W, Cho B. Zero-voltage-transition interleaved boost converter with an
auxiliary coupled inductor. IEEE Trans Power Electron 2017;32(8):5917–30.
https://doi.org/10.1109/TPEL.2016.2614843.
[40] Gules R, Pfitscher LL, Franco LC. An interleaved boost DCDC converter with large
conversion ratio. In: Proc IEEE int symp ind electron; 2003. p. 411–6.
[41] Wu G, Ruan X, Ye Z. Nonisolated high step-Up DC–DC converters adopting
switched-capacitor cell. IEEE Trans Ind Electron 2015;62(1):383–93. https://doi.
org/10.1109/TIE.2014.2327000.
[42] Tang Y, Wang T, He Y. A switched-capacitor-based active-network converter with
high voltage gain. IEEE Trans Power Electron 2014;29(6):2959–68. https://doi.
org/10.1109/TPEL.2013.2272639.
[43] Galigekere P, Kazimierczuk MK. Analysis of PWM Z-source dcdc converter in CCM
for steady state. IEEE Trans Circ Syst I, Reg Pap 2012;59(4):854–63.
[44] Shen H, Zhang B, Qiu D, Zhou L. A common grounded Z-source DC–DC converter
with high voltage gain. IEEE Trans Ind Electron 2016;63(5):2925–35. https://doi.
org/10.1109/TIE.2016.2516505.
[45] De Alcântara Bastos GH, Costa LF, Tofoli FL, Torrico Bascopé GV, Torrico
Bascopé RP. Nonisolated DC–DC converters with wide conversion range for high-
power applications. IEEE J Emerg Sel Top Power Electron 2020;8(1):749–60.
https://doi.org/10.1109/JESTPE.2019.2892977.
[46] Shreelakshmi MP, Das M, Agarwal V. Design and development of a novel high
voltage gain, high-efficiency bidirectional DC–DC converter for storage interface.
IEEE Trans Ind Electron 2019;66(6):4490–501. https://doi.org/10.1109/
TIE.2018.2860539.