A Self-Balanced Step-Up Multilevel Inverter Based On Switched-Capacitor Structure

This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2669377, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS 1
A Self-balanced Step-up Multilevel Inverter

based on Switched-Capacitor Structure
Amir Taghvaie, Jafar Adabi, and Mohammad Rezanejad
1
In many applications with low input DC sources (high or
Abstract— In this paper, a DC to AC converter with the low power, single or multiple DC sources), a high output AC
ability of voltage increasing is presented. This inverter is voltage is required. Transformers or inductors are used in
designed in a way that just one DC source is used. Also, by many topologies to boost the voltage in many applications
using power storage technique and with combining such as grid connected DG systems [7], electric vehicle [8]
charged capacitors and DC source in series form, output and renewable sources [9] in which the input voltage is less
voltage levels can be increased. This inverter is in a than the required output voltage. However, high volume cores
modular structure and has the ability of capacitor’s in transformers and inductors lead to bulky and heavy
voltage self-balancing. H-bridge inverter wasn’t used at converters in mentioned systems [10]. Researchers seek for
the end of the proposed converter and all elements tolerate MLI structures with combination of DC sources and
a voltage stress equal to the amount of input DC source. capacitors through different power semiconductors in order to
This leads to remarkable decrease of Total Standing achieve higher output AC voltage in staircase form. Therefore,
Voltage (TSV) and Peak Inverse Voltage (PIV). Other transformer-less or Inductor-less topologies are introduced.
advantage of the proposed inverter is its potentiality of These inverters are required to have minimum possible
performance in high frequency applications. The modular number of DC sources and low total standing voltage (TSV)
form of the proposed inverter provides the potentiality of for the semiconductors.
extension to higher voltage levels and eases the Hence, new converters were designed based on switched-
maintenance. Moreover, considering to the fact that the capacitors structure [11-14] in order to increase the voltage
stress of all components of the suggested inverter is equal levels but they suffers from high voltage stress on switching
to input source, performance in high voltage is added to components. A generalized MLI is presented in [15] which
the characteristics of the proposed inverter. The 9-level has the ability of self-balancing and the voltage stress of all
structure of the proposed inverter is simulated and elements is equal to input DC source (except output H-bridge
laboratory test is carried out for the verification of its inverter), but a high number of components are used. As
performance. shown in Fig.1.a, [16] presented a multilevel inverter based on
unipolar Marx converter structure for inductively coupled
Index Terms— Self-balancing, bipolar inverter, Switched- power transfer. This switched-capacitor inverter has been
capacitors, Step-Up extended to high frequency applications at [17]. In this
inverter, the voltage stress of all elements is equal to input DC
I. INTRODUCTION voltage (except output H-bridge inverter). High switching
frequency is used in this structure and multi-carrier PWM
M ultilevel inverters (MLIs) play important role in energy

conversion systems such as wind, photovoltaic, fuel
cells and electric vehicles [1]. These converters, which consist
technique is used as switching method. Proposed structure of
[18] reduces number of switches to one in each module which
leads to reducing drivers and ease the control in comparison
of DC sources, active switches and power diodes, can produce with other topologies. However, voltage stress of each
staircase voltage waveform with low Total Harmonic switches increase by voltage level increment as well as
Distortion (THD). Power semiconductors in MLIs normally increasing number of series diodes. A MLI topology is
tolerate less voltage stress in comparison with the traditional presented in [19] based on cascaded connection of sub-
2-levels counterparts [2]. The other advantages of MLIs are multilevel units with reduced switching components.
reducing the total losses and output filter size [3]. On the other Moreover, MLI based on full bridge inverter with the ability
hand, the common MLIs such as Flying Capacitor (FC) and of self-balancing is presented in [20] but it suffers from high
Neutral Point Clamped (NPC) have challenges regarding amount of TSV and PIV in higher levels (see Fig.1.b). In [21-
capacitors voltage balancing especially when the number of 22], boosting inverter is presented based on switched-
levels increases [4-5]. Cascaded H-bridge (CHB) MLIs need capacitors in which an inductor is used in the converter input.
separate DC sources [6]. It is essential to consider that all of the above-mentioned
structures require an H-bridge inverter at the end of the
Manuscript received March 15, 2016; revised May 27, 2016 and November topology in order to achieve negative and zero voltage levels
14, 2016; accepted February 2, 2017.
Amir Taghvaie and Jafar Adabi are with the Department of Electrical
[23]. Due to application of four power switches, which have to
Engineering Faculty, Babol Noshirvani University of technology, withstand total load voltage, it leads to limitation on selection
Mazandaran, Babol, Iran (amir.taghvaie@gmail.com, j.adabi@nit.ac.ir). of semiconductors especially in higher output voltage. Since
Mohammad Rezanejad is with Mazandaran University of Science and the requirement for high voltage AC power supplies increases
Technology, Mazandaran, Babol, Iran (m.rezanejad@ustmb.ac.ir).
0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2669377, IEEE
[24], a self-balanced MLI topology is introduced in this paper B. The proposed bipolar module
to achieve lowest possible TSV and PIV for switches with the
Fig.3.a shows the proposed basic module, which consists of
capability of staircase multi-level bipolar voltage generation.
five power switches per one capacitor. The input source in the
All components in proposed structure withstand voltage stress
above module can be fuel cell, PV panel and batteries. As
equal to input DC voltage by eliminating end side H-bridge
shown in Fig.3.b, during charging state, S mi2 and Smi5 are in
inverter. Four main step-up SCMLIs topologies are shown in
ON-state, which connects the input source with the capacitors
Fig.1.
in parallel. Fig.3.c shows discharging state of the capacitor
In section II, general structure and performance of
where Smi2 and Smi3 are in ON-state and the output voltage is
proposed inverter are presented as well as investigation of
equal to +Vdc. To generate negative voltage level, as shown in
different charging and discharging states. Modulation
figure 3.d, Smi1 and Smi4 are in ON-state. It should be
technique is brought in section III. Section IV calculates
mentioned that (Smi1 and Smi2) and (Smi3 and Smi4) have to be
capacitors, losses and efficiency. A comparative study with
turned on and off complementary.
other existing topologies is conducted at section V. Laboratory
test and simulation are carried out and the results are shown in
section VI to verify the inverter performance. Finally,
conclusion of this paper is presented in section VII.
Fig.3. (a) proposed module (b) its charging state (c) discharging positive state
and (d) discharging negative state
Fig.1. Different structures of step-up SCMLIs (a) [17] (b) [20] (c) [24] (d) [18]
C. Proposed Switched-Capacitor Topology
II. CIRCUIT TOPOLOGY AND OPERATING PRINCIPALS
A. Unipolar module Fig.4 shows the proposed 9-level switched-capacitor
structure, which is a cascaded version of bipolar modules of
Fig.2.a shows the module of the switched-capacitor Fig.3. Since voltage stress of all elements is 1Vdc, for a (2n+1)
presented in [17]. Fig.2.b and c show the charging and levels output voltage, TSV is obtained as:
discharging states of the above module respectively. However,
this module is unipolar and just produces positive voltage. TSV  (5n  1).V dc (2)
A A A
+ +
C Vdc C Vdc C
S1 S1 -
S1 -
S2 S2 S2
Vdc S3 Vdc S3 Vdc S3
B B B
(a) (b) (c)
Fig.2. presented module in [17]
By cascading mentioned modules, a unipolar multilevel

inverter is created which needs a full bridge inverter to create
bipolar levels. The number of steps is considered as n, the total
standing voltage (TSV) of this inverter is obtained as:
TSV   3(n  1)  4n  .Vdc  (7n  3) Vdc (1) Fig.4. proposed switched-capacitor MLI
D. Start-up Mode
Voltage stress of all components is 1Vdc except four full bridge
In the proposed switched-capacitor inverter, the capacitors
switches that should tolerate output AC voltage peak ( nV
. dc ).
are needed to be charged at first. All capacitors are charged in
parallel with DC input source. Fig.5 shows the switching state
for circuit start-up.
Fig.5. Charging mode of the proposed SCMLI
In start-up mode, Smi2, Smi4 and Smi5 switches are in ON-

state and all capacitors are charged equal to 1Vdc while the
output voltage is zero. In charging state of capacitors, the
voltage drop occurs when switches and diodes are in the path.
Capacitor‟s voltage during charge state is as follows:
t

C n
V C n (ch arg ing ) (t ) V inputC .(1  e ) (3)
n
where V inputC is the input voltage of capacitors and C n is

n
time constant of each capacitor. It is worth mentioning that the

number of ON state switches or diodes and their on-state
resistant for different paths are not equal. So, capacitor‟s
voltage during charge state is obtained as following equations:
V C 1(ch arg ing ) (t )  V dc  (2V on ,sw  2V on , D  (2(Ron ,sw  Ron , D )  rC1 ).i C av 
 1 

t (4)
 2( Ron ,sw  Ron ,D )  rC1 .C1
.(1  e )
V C 2 (ch arg ing ) (t )  V dc  (4V on ,sw  4V on , D  (4(Ron ,sw  Ron , D )  rC 2 )i C av ) 
 2 

t (5)
 4( Ron ,sw  Ron ,D )  rC 2 .C 2
.(1  e )
V C 3(ch arg ing ) (t )  V dc  (6V on ,sw  6V on , D  (6(Ron ,sw  Ron , D )  rC 3 ).i C av ) 
 3 

t (6)
.(1  e  on ,sw on ,D C 3  3 )
6( R R )  r .C
where Ron, sw represents collector-emitter on-state

resistance, Ron,D is antiparallel diode on-state resistance, Von,
sw is the IGBT on-state zero-current collector-emitter forward
voltage drop, Von, D is representing the on-state zero-current
forward voltage drop of anti-parallel diode and rC is ESR of Fig.6. discharging states of the proposed inverter
the capacitors and iCavi is the average current of capacitors.
III. MODULATION STRATEGY
E. Multilevel Output Voltage Generation Mode
As shown in Fig.7, a carrier-based PWM method is used to
However, for producing output voltage and creating control the proposed SCMLI in which 8 triangular carrier
staircase waveform with the desired frequency and amplitude, signals are compared with a sinusoidal 50Hz reference signal
the charged capacitors should be discharged in series in a way to generate required pulses for switches. According to this
that different levels could be created. Because of simplicity figure, e1, e2, e3 and e4 are triangular carriers for positive half-
and modularity of the proposed switched-capacitors inverter, cycle of output voltage which generates required switching
staircase voltage production is possible by a very simple pulses for Smi1 and Smi2. Similarly, e5, e6, e7 and e8 are
switching strategy. Fig.6 shows discharging modes and triangular carriers for negative half-cycle of output voltage
staircase voltage production. As it is clear from the figure, S mi2 which generates required switching pulses for Smi3 and Smi4.
and Smi3 (Smi1 and Smi4) switches are in ON-state to produce Also, Smi5 will be turned on only when both Sm12 and Sm14
positive (negative) voltage levels. (Smi1 and Smi3) or (Smi2 and are in ON state. Table I illustrates the ON state switches in
Smi4) switches would be turned on for bypassing the capacitor each level.
of each module.
IV. CALCULATION OF CAPACITANCE, LOSSES AND

EFFICIENCY
A. Determination of Capacitance
The capacitors calculation is one of the most important
issues in the switched-capacitors converters to prevent
appearance of high voltage ripples across capacitors. For a
nine level inverter (see Fig.7), t1, t2… t6 are calculated as
follows [17]:
1 (7)
sin 1 4
 
t1 
2  f ref
2 (8)
sin 1  
4
t2 
2 f ref
3 (9)
sin 1  
4
t3 
2 f ref
3 (10)
 sin 1  
4
(a) t4 
2  f ref
2
 sin 1   (11)
4 
t5 
2  f ref
1
 sin 1   (12)
4 
t6 
2  f ref
The longest discharging times (tx,i, tyi) for each capacitor

(C1, C2 and C3) are (t1, t6), (t2, t5) and (t3, t4), respectively.
Where tx,i and tyi are the beginning and time of the longest
discharging period of ith capacitor. Therefore, the maximum
discharge amount of capacitors is obtained as:
t y ,i
QC i   tx ,i
I load .sin (2 f ref t ) dt (13)
The capacitor‟s capacity depends on the maximum flowing

current and the longest discharging time on load. Considering
k as a ripple ratio, the capacitance is calculated as following
equation:
QC i
Ci  (14)
k . V dc
B. Calculation of Losses
(b)
Fig. 7(a) Carrier-based PWM modulation technique (b) logic modulating for Three types of losses are considered for the switched-
proposed MLI capacitors converters which include capacitors charging losses
TABLE I
(Ploss, cap), switching losses (Psw) and conduction losses (Pcond).
LIST OF ON STATE SWITCHES IN EACH LEVELS 1. Capacitor charging loss
Output
ON state switches In charging state of capacitors, losses of capacitor ripple
voltage
V ref  e1 Sm11, Sm14, Sm21, Sm24, Sm31, Sm34, Sm41, Sm44 4Vdc (Pcr) occur due to voltage differences between DC input and
the voltage across capacitors. Capacitors voltage ripple is
e1  V ref  e 2 Sm11, Sm14, Sm21, Sm24, Sm31, Sm34, Sm42, Sm44 3Vdc
obtained by following equation [17]:
e 2  V ref  e 3 Sm11, Sm14, Sm21, Sm24, Sm32, Sm34, Sm42, Sm44 2Vdc 1 ty,i
VCi   iCi (t ) dt (15)
e 3  V ref  e 4 Sm11, Sm14, Sm22, Sm24, Sm32, Sm34, Sm42, Sm44 1Vdc Ci tx ,i
e 4  V ref  e 5 Sm12, Sm14, Sm22, Sm24, Sm25, Sm32, Sm34, Sm35, 0 where iCi is the current passing from ith capacitor and (tx,i,
Sm42, Sm44,Sm45 ty,i) are discharging time during series connection of capacitors
e 5  V ref  e 6 Sm12, Sm13, Sm22, Sm24, Sm32, Sm34, Sm42, Sm44 -1Vdc
according to Fig.6. Therefore, capacitors ripple losses is
e 6 V ref  e 7 Sm12, Sm13, Sm22, Sm23, Sm32, Sm34, Sm42, Sm44 -2Vdc obtained from following equation [13].
f 3 (16)
e 7  V ref  e 8 Sm12, Sm13, Sm22, Sm23, Sm32, Sm33, Sm42, Sm44 -3Vdc
PC ripple  ref C i V C i 2
2 i 1
e 8 V ref Sm12, Sm13, Sm22, Sm23, Sm32, Sm33, Sm42, Sm43 -4Vdc
Also, the additional losses happen by the internal resistance where V off-state,i is the off-state voltage of ith switch (equal
of capacitors (rC). The conduction losses of capacitors (P CC) to 1Vdc in the proposed structure) , Ion-state1,i is the current of ith
and capacitor‟s total losses are calculated as: switch when the switch becomes completely turned on, and
 2 f ref  3 t y , i Ion-state2,i is the current of ith switch before the turn-off of the
PCC     t x , i rc . i C k .dt
2
(17) switch. fs is the switching frequency that in the proposed
   k 1 structure is obtained as following equation [17]:
Ploss ,cap  PC ripple  PCC (18) f s ,on  N S ,on . f ref [21]
2. Switching losses f s ,off  N S ,off . f ref [22]
One of the most important sources of the power loss is
switching losses which are generated due to switching delays In the above equations, NS, on and NS, off are the number of
that are intrinsic to the semiconductor devices. As shown in turn on and turn off of each switch and diode, respectively.
Fig.8, in turn-on process, at the end of delay time (t delay, on), NS, on and NS, off for switches of each module is calculated as
gate-emitter voltage (VGE) reaches to threshold voltage (VT) following equations:
and the collector current (ID) starts increasing. In this case, ton, sw f
N S , on   Nt  sw [23]
collector-emitter voltage (VCE) starts decreasing. The 2 f ref
operation in this state finishes when VCE reaches to Von-state
toff , sw f sw
which shows the end of turn on process. On the other hand, in N S , off   Nt  [24]
the turn-off process, at the end of delay time (tdelay, off) when 2 f ref
VGE reaches to VGE-sat, ID starts decreasing and VCE starts In the above equations, ton, sw is the time when switch is ON
increasing. Because in turn-on and turn-off processes, voltage and toff, sw is the time when switch is OFF, fsw is switching
and current do not instantaneously change, both of them can frequency and Nt is total number of turn ON or OFF in each
simultaneously have significant values, and their power can switching cycle which is 1for the proposed structure.
reach very high amounts. The loss during turning ON and OFF Therefore, switching losses is obtained from the relation (27).
of the active switches is obtained as following equations [27]:
t on
Psw ,i (ON )  f s  V off state ,i (t ). i (t ) dt
N switch
 N on ( i ) N off ( i )

0 Psw , total     sw ,on (ij )  Psw ,off (ij ) 
P  (25)
t on  V off  state ,i  I 
i 1  j 1 i 1 
fs  (t  t on )   on  state 1,i t  dt (19)
0
 t on   t on  Where Non (i) and Noff (i) is the number of turn-on and turn-
off of the ith switch during one period and N switch is the
1
 f s V off  state ,i I on  state 1, i t on number of switches. According to the above equations,
6 switching power loss is proportional to the value of the
t off
Psw ,i (OFF )  f s  V off state ,i (t ). i (t ) dt blocked voltage across the semiconductor devices, i.e. off-
0 state voltage. Therefore, it is important to reduce this loss
t off V off state ,i  I off state 2,i  because it will be dissipated in the form of heat on the switch.
fs  t   (t  t off )  dt (20) In the proposed structure, all devices are switched when each
 t off  t off 
0
of them tolerates 1Vdc. As a result, the switching losses of the
1
 f s V off state , i I on state 2, i t off proposed structure are very smaller than the conventional
6 structures.
3. Conduction losses
Conduction losses for the power switch and power diode is
obtained from the equations (26-27) [25].
Pcond , sw (t )  V on ,sw .i sw , avg  Ron , sw .i sw ,rms 2 (26)
Pcond , D (t ) V on ,D .i D , avg  Ron , D .i D ,rms 2

(27)
where irms is the RMS current of semiconductors (switches
and diodes) and iavg is the average current of semiconductors.
As shown in Fig.6, there are some switches and diodes during
discharging paths in each level that cause conduction losses.
For steps (1, 2,3, 4). V dc , the conduction losses are obtained as
following equations:
Pcon , (1V dc )  (5V on ,sw .i load , avg  5Ron ,sw .i load , rms 2 )
(28)
 (3V on , D .i load , avg  3Ron , D .i load , rms 2 )
Fig. 8 Transient process of a power switch [27]
Pcon , (2 V dc )  (6V on ,sw .i load , avg  6Ron ,sw .i load , rms 2 )

(29)
Pcon , (3V dc )  (7V on ,sw .i load , avg  7Ron ,sw .i load , rms 2 )
(30)
Pcon , (4 V dc )  (8V on ,sw .i load , avg  8Ron ,sw .i load , rms 2 )
(31)
Pcon , ( 1V dc )  (3V on ,sw .i load , avg  3Ron ,sw .i load , rms 2 )
(32)
 (5V on , D .i load , avg  5Ron , D .i load , rms 2 ) (a)
Pcon , (  2 V dc )  (2V on ,sw .i load , avg  2Ron ,sw .i load , rms 2 )
(33)
 (6V on , D .i load , avg  6Ron ,D .i load , rms 2 )
Pcon , ( 3V dc )  (1V on ,sw .i load , avg  1Ron ,sw .i load , rms 2 )
(34)
Pcon , (  4V dc )  (8V on , D .i load , avg  8Ron , D .i load , rms 2 ) (35)
As a result, total conduction loss is sum of positive and
negative steps and calculated as following equation:
Pcon ,total  Pcon , (1V dc )  Pcon , (2V dc )  Pcon , (3V dc )  Pcon , (4V dc )
(36)
 Pcon , ( 1V dc )  Pcon , ( 2V dc )  Pcon , ( 3V dc )  Pcon , ( 4V dc ) (b)
Finally, the efficiency can be achieved as:

 V out ( rms ) 2 
 
 Pout   R  100
   100  
load
(37)
 out  Ploss
P  V out ( rms ) 2 
  (Psw  Pcond ) 
 R load 
V. COMPARATIVE STUDY
As shown in Table II, the proposed inverter is compared
with four well-known topologies for a (2n+1) level or n steps.
Compared with structures of [17], [18], [24] and [26], the
proposed MLI has higher number of switches but, TSV and
PIV of the suggested inverter are remarkably lower than other
structures (see Fig.9). Since proposed inverter doesn‟t use H- (c)
Fig.9. comparison diagram of proposed topology with [17], [18], [24] and
bridge inverter and provides 1Vdc voltage stress on all [26] (a) Number of Semiconductor (b) TSV (c) PIV
components has a high chance to perform in medium and high
powers and also high frequencies applications. Moreover, comparison between the proposed SCMLI and
TABLE II others in efficiency point of view is carried out and the results
COMPARISON OF PROPOSED TOPOLOGY WITH SUGGESTED STRUCTURES IN show that the proposed topology has better efficiency with the
[17], [18], [24] AND [26] FOR A 2N+1 LEVEL OUTPUT same characteristics. Note that for efficiency comparison, a
Fig .1 Fig. 1 Fig. 2 Fig. 2 case study with input voltage of 48 volts, switching frequency
Comparing items Proposed
in [17] in [18] in [24] in [26]
of 2KHz, boost ratio of 4 (n=4) and load resistance of 100 Ω is
Electrolytic
n-1 n-1 n-1 n-1 n-1 considered for all topologies. Switches from IRF MOSFET
Capacitors
Number of Active family (IRF520, IRF630, IRF634 and IRF740 for voltage
3n+1 n+4 2n+4 3n+1 5n-1
Switches ratings of 100, 200, 250 and 400 volts) are used. Note that a
Series diode 0 2n-2 2n-2 0 0 50% voltage rating margin is considered for selection of
H-bridge‟s stress nVdc nVdc nVdc nVdc No need switches. Detailed specifications of these switches can be
PIV nVdc nVdc nVdc nVdc 1Vdc extracted from their datasheets. Series diodes for other
2
topologies are selected among MBR10100, MBR 10200 and
n
TSV ( ) 7n  3 n 2  4n n 2  5n  1  5n 5n  1 APT30D30B. Using precise calculation of losses at previous
2
section, efficiency values for all 5 topologies are calculated
Efficiency 88.36% 87.76% 86.67% 88.25% 91.7%
which is shown at Table II. Note that, cases with other
parameters are also tried which leads to better performance of
proposed topology in terms of efficiency.
Generation of bipolar voltage levels is one of the advantages

of proposed circuit. As mentioned before, an H-Bridge
inverter is required at the end side of the traditional converters
with the switches with PIV of n×Vdc. This adds 4n×Vdc to
TSV of the circuit. This may be a drawback for the
applications with higher DC input voltage. If the output
voltage is very large, it will become very difficult to find
appropriate power switches for an H-bridge inserted before the
load at an acceptable price. In such applications, it will be
preferable to have more low voltages rated power switches
with their drivers in each SC module. According to the
analysis of this section, following issues can be concluded.
(1) PIV of proposed topology is 1Vdc while other topologies
need switches with more peak inverse voltage. This is a
benefit especially when the input voltage is high and (c)
consequently, the rating of switches for H-Bridge converter is
very high.
(2) In addition, selection of a topology depends on the
constraints of customers. To explain this, a cost function (CF)
is defined as follows to consider the effects of different
constraint [19].
TSV PIV
CF  N semiconductor   .V TSV pu   .V PIV pu  N semiconductor    (38)
V dc V dc
where  is the importance factor of TSV and β is the
importance factor of PIV against number of semiconductors. If
TSV and PIV are more important than the number of
semiconductors, so α and β>1. If TSV and PIV are less
important than the number of semiconductors, so α and
β<1.Fig.10 shows comparison between the proposed structure (d)
and others in view point of CF. As shown in this figure, the Fig.10. CF factor versus number of steps for proposed structure compare with
[17], [18], [24] and [26] (a) α=0.5, β=0.5 (b) α=1.5, β=0.5 (c) α=0.5, β=1.5 (d)
proposed SCMLI has less CF factor than other topologies in α=1.5, β=1.5
different conditions.
VI. THE SIMULATION AND EXPERIMENTAL RESULTS
A. The simulation results

Parameters of Table III are used for simulation of the
proposed 9-level inverter.
TABLE III
SIMULATION PARAMETERS
Input Voltage(Vin) 100Volt
Number of Output Voltage levels 9
Output Frequency 50Hz,500Hz
4700µf (refer to calculations
Capacitors
of section IV.A)
Resistive Load (R) 100Ω
(a) Inductive-Resistive Load (R-L)
100Ω , 318.5mH
for 50 Hz output
Inductive-Resistive Load (R-L)
100Ω , 31.85mH
for 500 Hz output
Fig.11 show output voltage and current waveform of the
proposed inverter for Rload with 50Hz. Moreover, the proposed
inverter has the potentiality of performance in high
frequencies, which Fig.12 shows output voltage waveform in
500Hz with resistive load.
(b)
B. The experimental results
At the implementation stage, features of table IV are used

for the verification of the circuit performance. At this stage a
9-level is implemented, too. Fig.15 presented a lab sample of
the proposed circuit.
Fig.11. output voltage and current waveform in 50Hz frequency with R-load
Fig.15.Experimental test setup

TABLE IV
COMPONENTS OF THE 9-LEVELS INVERTER
Input Voltage(Vin) 48Volts
Number of Output Voltage levels 9
Output Voltage Frequency 50Hz and 1KHz
Electrolyte Capacitors 4700µF
Resistive Load (R) 250Ω
Inductive-Resistive Load (R-L) 100Ω , 100mH
Fig.12. output voltage and current waveform in 500Hz frequency with R-load
Diode MUR860(600 Volts)
Also, Fig.13&14 show output voltage and current
IGBT 12n60a4 (600 volt)
waveforms of the proposed inverter with R-L load in 50Hz
and 500Hz frequencies. Driver/Optocoupler HCPL 3120
Processor DSP TMS320F28335
Voltage probe PINTEK DP- 50
Current probe FLUKE 80i-110s AC/DC
To control IGBTs (12n60a4), pulses are created by

processor (DSP TMS320F28335) based on Carrier-Based
PWM modulation technique. As shown in Fig.16, these pulses
(with amplitude of 3.3 volt) have to be amplified by buffer IC
74HC244P. Required pulses for turning IGBTs have to be 18
volts for on-state and 0 volts for off-state. Isolation is also
Fig.13. output voltage and current waveform in 50Hz frequency with R-L load
required between power and control circuit which is done by a
Driver/Optocoupler IC HCPL3120.
Fig.16. Switching of an IGBT
Fig.17 shows the waveform of the output voltage of the 9-

level inverter in 50Hz.Note that THD for proposed 9-level
inverter is 15.02% and the measured efficiency is 88.93%. It is
lower than calculated values in section IV. This is due to line
Fig.14. output voltage and current waveform in 500Hz frequency with R-L impedance and using IGBT12N60 in hardware which were
load available in our laboratory. Note that using 12N60 IGBTs
would decrease other topologies as well. Calculated As shown in Fig.20, the load is changed between RL=100Ω,
efficiencies are for IRF family MOSFETs which has lower 250Ω and 100KΩ. This result shows that the proposed
switching time and on state voltage. Fig.18 shows the output structure can function in any dynamic condition and keeps its
voltage waveform at 1 KHz. balancing states.
Fig.17. output voltage with R-load in 50Hz frequency (probe ×100)
VII. CONCLUSION
A boost multilevel inverter is presented in this paper with
the aim of reducing voltage stress on circuit components. A
multi-module switched-capacitor network is presented in
which by specific connection of the modules, a staircase
multilevel voltage is generated. A comprehensive
mathematical analysis of proposed system is conducted to
achieve capacitance values, calculation of losses, voltages of
each capacitor. Investigation of proposed nine-level SCMLI
topology indicates that charging and discharging states of the
proposed SCMLI topology is in a self-balanced manner.
Losses calculation of proposed SCMLI shows that the
efficiency of proposed converter is an acceptable value for this
type of converters. A comparison between the proposed
Fig.18. output voltage in R-load in 1 KHz frequency (probe ×100) inverter and well-known circuits indicates that the proposed
inverter has very low amount of TSV and PIV and all
Moreover, voltage waveform and current waveform of the components tolerate the same voltage of 1Vdc. Comprehensive
output in R-L load is shown in Fig.19 which confirms simulation study and experimental results are presented to
application of proposed structure and its mentioned control verify the analysis.
strategy in different operating conditions.
REFERENCES
[1] A. Emadi, S. S. Williamson, and A. Khaligh, “Power electronics
intensive solutions for advanced electric, hybrid electric, and fuel cell
vehicular power systems,” IEEE Trans. Power Electron., vol. 21, no.
3,pp. 567–577, May 2006.
[2] J. Rodriguez, J. S. Lai and F. Z. Peng, “Multilevel inverters: A survey of
topologies, control, and applications,” IEEE Trans. Ind. Electron., vol.
49, no. 4, pp. 724–738, Dec. 2002.
[3] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M.
A. M. Prats, “The age of multilevel converters arrives,” IEEE
Ind.Electron. Mag., vol. 2, no. 2, pp. 28–39, Jun. 2008.
[4] V. Dargahi, A. K. Sadigh, M. Abarzadeh, S. Eskandari and K. Corzine,
“A new family of modular multilevel converter based on modified flying
capacitor multicell converters,” IEEE Trans. Power Electron. , vol. 30,
no. 1, pp. 138-147, Jan. 2015.
[5] E. Ozdemir, S. Ozdemir, L and M. Tolbert, “Fundamental-frequency
modulated six-level diode-clamped multilevel inverter for three-phase
stand-alone photovoltaic system” IEEE Trans. Ind. Electron. Vol. 56, No
Fig.19. waveform of the output voltage and current in R-L load in 50Hz 11, pp. 4407–4415, Nov 2009.
frequency (voltage probe ×100 and current probe 100mv/A)
[6] A. Mokhberdoran and A. Ajami, “Symmetric and Asymmetric Design Amir Taghvaie was born in Sari, Iran, 1990. He
and Implementation of New Cascaded Multilevel Inverter Topology,” received the BEng in electrical engineering from
IEEE Trans. Power Electron. Vol 29, No 12, pp. 6712-6724, Dec 2014. Islamic Azad University of Aliabad, Aliabad, Iran,
[7] N. A. Rahim, K. Chaniago, and J. Selvaraj, “Single-phase seven-level in 2012. He is currently working towards the MEng
grid-connected inverter for photovoltaic system,” IEEE Trans. Ind. degree in Babol Noshirvani University of
Electron., vol. 58, no. 6, pp. 2435–2443, Jun. 2011. Technology, Babol, Iran. His research interests
[8] L. M. Tolbert, F. Z. Peng, and T. G. Habetler, “Multilevel Converters for include Switched-Capacitors circuits, high-voltage
large Electric Drives,” IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 36- high-power multilevel converters, power converters
44,Jan./Feb. 1999. and its applications in renewable energy.
[9] M. Jang, M, Ciobotaru,, and V,G, Agelidis “A Single-Phase Grid
Connected Fuel Cell System Based on a Boost-Inverter” IEEE Trans.
Power electronic. Vol. 28, No. 1, Jan 2013.
[10] K. C. Tseng, C.C. Huang, and W.Y. Shih “A High Step-Up Converter Jafar Adabi was born in 1981. He received his
with a Voltage Multiplier Module for a Photovoltaic System.” IEEE BEng and MEng degrees from Mazandaran
Trans. Power electronic, Vol. 28, No. 6, June 2013. University, Babol, Iran, in 2004 and 2006,
[11] O. C. Mak, Y. C. Wong, and A. Ioinovici, “ Step-up DC power supply respectively. He finished his PhD degree in the
based on a switched-capacitor circuit,” IEEE Trans. Ind. Electron., vol. School of Engineering Systems at the Queensland
42, pp. 90–97, Feb. 1995. University of Technology, Brisbane, Queensland,
[12] J. Liu, K. W. E, Cheng and Y. Ye, “A cascaded multilevel inverter based Australia at 2010. Currently, he is an assistant
on switched-capacitor for high frequency ac Power distribution System,” professor at Noshirvani University of Technology,
IEEE Trans Power Electron. Vol 22, No 8, pp. 4219-4230, Aug 2014. Babol, Iran. His research interests are the optimal
[13] E. Babaei and S. S. Gowgani, “Hybrid multilevel inverter using design and high frequency modelling of power
switched-capacitor units” IEEE Trans. Ind. Electron. Vol 61, No 9, pp. electronics and motor drive systems for EMI
4614-4621, Sep 2014. analysis.
[14] Y. H. Chang, “Design and Analysis of Multistage Multiphase Switched-
Capacitor Boost DC–AC Inverter” IEEE Trans. Circuits Syst. I, Vol. 58,
No. 1, Jan 2011. Mohammad Rezanejad was born in Babol, Iran in
[15] F. Z. Peng, “A Generalized Multilevel Inverter Topology with Self 1983. He received the B.Sc., M.Sc. and PhD.
Voltage Balancing” IEEE Trans. Industry Application, Vol. 37, No. 2, degrees in power engineering from Mazandaran
MARCH/APRIL 2001. University (Babol Noshirvani University of Tech.),
[16] J. I. Rodriguez and S. B. Leeb, “A multilevel inverter topology for Babol, Iran, in 2006, 2009 and 2014, respectively.
inductively coupled power transfer,” IEEE Trans. Power Electron., vol. Currently he is an assistant professor at Mazandaran
21, no. 6, pp. 1607–1617, Nov. 2006. University of Science and Technology. His current
[17] Y. Hinago, and H. Koizumi, “A Switched-Capacitor Inverter Using research interests are multilevel converters, pulsed
Series/Parallel Conversion With Inductive Load” IEEE Trans. Ind. power, high-voltage power electronics converters
Electron, Vol. 59, No. 2, Feb 2012. and FACTS.
[18] Y. Ye, K.W. E. Cheng, J. Liu, and K. Ding. “A Step-Up Switched-
Capacitor Multilevel Inverter with Self Voltage Balancing” IEEE Trans.
Ind. Electron. VOL. 61, issue. 12 March 2014.
[19] R.S. Alishah, S.H Hosseini, E. Babaei, and M. Sabahi, “A new general
multilevel converter topology based on cascaded connection of sub-
multilevel units with reduced switching components, dc sources and
blocked voltage by switches,” IEEE Trans. Ind. Electron., vol. PP, DOI
10.1109/TIE.2016.2592460, no. 99, pp. 1–1, 2016.
[20] Y. Liu, F.L. Luo. „Multilevel inverter with the ability of self-voltage
balancing,‟ IEE Proc.-Electr. Power Appl., Vol. 153, No. 1, Jan 2006.
[21] B. Axelrod, Y. Berkovich, and A. Ioinovici, “A cascade boost-switched-
capacitor converter-two level inverter with an optimized multilevel
output waveform,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52,
no. 12, pp. 2763–2770, Dec. 2005.
[22] M. S. W. Chan and K. T. Chau, “A new switched-capacitor boost
multilevel inverter using partial charging,” IEEE Trans. Circuits Syst. II,
Exp. Briefs. Vol 54, No 12, pp. 1145–1149, Dec 2007.
[23] K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu and S. Jain,
“Multilevel Inverter Topologies with Reduced Device Count: A
Review” IEEE Trans. Power Electron., vol. 31, no. 1, pp. 135–151,
February, 2015.
[24] O. C. Mak and A. Ioinovici, “Switched-capacitor inverter with high
power density and enhanced regulation capability” IEEE Trans. Circuits
Syst. I, Fundam. Theory Appl., vol. 45, no. 4, pp. 336–347, Apr. 1998.
[25] A. K. Sadigh, V. Dargahi, K. A. Corzine, “Analytical Determination of
Conduction and Switching Power Losses in Flying-Capacitor-Based
Active Neutral-Point-Clamped Multilevel Converter, ”IEEE Trans.
Power Electron., vol. 31, no. 8, pp. 5473–5494, August, 2016.
[26] R. Barzegarkhoo, H. M. Kojabadi1, E. Zamiry, N. Vosooghi and L.
Chang, “Generalized Structure for a Single Phase Switched-Capacitor
Multilevel Inverter Using a New Multiple DC Link Producer with
Reduced Number of Switches,” IEEE Trans. Power Electron., vol. 31,
no. 8, pp. 5604–5617, August, 2016.
[27] A. Ioinovici, “Power electronics and energy conversion systems", first
edition, John Wiley & Sons.

A Self-Balanced Step-Up Multilevel Inverter Based On Switched-Capacitor Structure

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A Self-Balanced Step-Up Multilevel Inverter Based On Switched-Capacitor Structure

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This article has been accepted for publication in a future issue of this journal, but has not been

A Self-balanced Step-up Multilevel Inverter

M ultilevel inverters (MLIs) play important role in energy

Vdc S3 Vdc S3 Vdc S3

By cascading mentioned modules, a unipolar multilevel

Fig.5. Charging mode of the proposed SCMLI

In start-up mode, Smi2, Smi4 and Smi5 switches are in ON-

where V inputC is the input voltage of capacitors and C n is

time constant of each capacitor. It is worth mentioning that the

where Ron, sw represents collector-emitter on-state

IV. CALCULATION OF CAPACITANCE, LOSSES AND

The longest discharging times (tx,i, tyi) for each capacitor

The capacitor‟s capacity depends on the maximum flowing

Pcond , D (t ) V on ,D .i D , avg  Ron , D .i D ,rms 2

Fig. 8 Transient process of a power switch [27]

Pcon , (2 V dc )  (6V on ,sw .i load , avg  6Ron ,sw .i load , rms 2 )

Finally, the efficiency can be achieved as:

Generation of bipolar voltage levels is one of the advantages

A. The simulation results

B. The experimental results

At the implementation stage, features of table IV are used

Fig.15.Experimental test setup

To control IGBTs (12n60a4), pulses are created by

Fig.16. Switching of an IGBT

Fig.17 shows the waveform of the output voltage of the 9-

Fig.17. output voltage with R-load in 50Hz frequency (probe ×100)

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