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Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS
A DC-DC Transformerless High Voltage Gain
Converter with Low Voltage Stresses on Switches
and diodes
Zahra Saadatizadeh, Pedram Chavoshipour Heris, Mehran Sabahi and Ebrahim Babaei, Senior Member
Abstract—In this paper, a new DC-DC high voltage gain
converter with low voltage stresses on switches and diodes is
proposed. Even though, in the topology of the proposed
converter there are not any coupled inductors and
transformer utilized, the voltage conversion ratio of the
proposed converter is considerable in comparison to its
conventional types. Also, two switches of proposed converter
provide longer charge time for two inductors which make the
proposed converter capable of providing high voltage gain
without preselecting extremely large duty cycles. In addition,
the number of power circuit components of the proposed
structure are few and the voltage stresses on semiconductor
elements are low. In this study, theoretical analysis of the
proposed converter for each operating mode is presented and
the voltage gain, voltage and average current stresses of
elements, maximum input current ripple, efficiency and
equations of critical inductances are calculated. Moreover, to
verify the capability of the proposed converter, it is
comprehensively compared with other similar recently
presented high voltage gain boost converters. Finally, an
approximately 12V/380V and 520-W prototype of the
proposed converter is implemented in laboratory to
demonstrate its practical performance, then, the experimental
results reconfirm each other and theoretical analysis.
Index Terms— DC-DC converter; high voltage gain; low
voltage stresses on switches and diodes.
I. INT RODUCT ION
Generally, a high voltage gain step-up DC-DC converter
can be utilized in any energy conversion applications of
renewable energy sources, such as solar photovoltaic (PV)
modules, fuel cells and hybrid systems [1]-[4].
Conventional boost DC-DC converters have to apply
extremely wide duty cycles to obtain higher voltage gains
[5]. Large voltage spikes on active switches would occur in
wider duty cycles which may force the designer to
implement switches with higher voltage characteristics,
Manuscript received March 6, 2018; first revised July 2, 2018; second
revised Oct. 15, 2018; accepted Jan. 26, 2019.
Zahra Saadatizadeh is with Faculty of Electrical and Computer Engineering,
University of Tabriz, Tabriz, Iran (e-mail: zsaadatizadeh@tabrizu.ac.ir).
Pedram Chavoshipour Heris is with Faculty of Electrical and Computer
Engineering, University of Tabriz, Tabriz, Iran (e-mail:
chavoshipour.pedram@hotmail.com).
Mehran Sabahi is with Faculty of Electrical and Computer Engineering,
University of Tabriz, Tabriz, Iran, (e-mail: sabahi@tabrizu.ac.ir).
Ebrahim Babaei is with Faculty of Electrical and Computer Engineering,
University of Tabriz, Tabriz, Iran, and also with the Engineering Faculty, Near
East University, 99138 Nicosia, North Cyprus, Mersin 10, Turkey (e-mail: e-
babaei@tabrizu.ac.ir).
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1
consequently, the conduction losses would be increased.
Moreover, severe diode reverse recovery problems would
be resulted by selecting higher duty cycles for the active
switches [6]- [8].
Step-up coupled-inductor based converters can easily
achieve higher step-up voltage conversion ratios by adding
winding turn ratios of their coupled inductors. However,
obtaining higher voltage gains through increasing winding
turn ratios of the coupled inductors has several drawbacks,
such as high ripple of input current, high current stresses of
switches in the primary winding side of coupled inductor,
high leakage inductances and consequently, high voltage
spikes on switches [9]. A clamping circuit is proposed in
[10] to avoid voltage spikes on switches, active-clamping
circuit is implemented in [11] to clamp trapped energy
through leakage inductance and interleaved structure in [12]
is applied to decrease the input current ripple.
Flyback converter is another choice for voltage step-up
applications. Despite its simple isolated topology and
ability to achieve high voltage gains without choosing wide
duty cycles, its voltage stresses on active switches and the
related losses are considerable, also, the leakage inductance
and input current ripple is rather high. A soft-switching
technique is proposed in [13] to decrease switching losses.
An active-clamp flyback converter is introduced in [14] to
recycle the leakage inductance and in [15] a flyback
converter without input current ripple is presented.
In [16] and [17] topologies based on switched-capacitor
cells are presented. Furthermore, in [18] a family of high
gained structures based on switched-capacitor-inductor
modules is proposed and also, in [19] hybrid converters
with switched-inductor cells are introduced. In addition, in
[20] a high step-up DC-DC converter based on diode-
capacitor connection to improve the dynamic performance
of the converter in larger ranges of output voltage is
presented. In [21] and [22], other converters with
combinations of diode, capacitor and inductor voltage
increasing cells are presented. These types of structures
would become more complex and the number of power
circuit components and conduction losses would be
increased.
High step-up DC-DC converters with voltage multiplier
cells (VMC) in their structures are presented in [23] and
[24]. Also, an interleaved boost converter with voltage
doubling feature is presented in [25] which is suitable for
power factor correction (PFC) applications. Moreover, in
[26] a switched-capacitor combination is used to create
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Transactions on Power Electronics

IEEE TRANSACTIONS ON POWER ELECTRONICS 2

function of doubling the voltage with applied active clamp at frequency of 50/60 Hz to the grid which can present
in order to absorb leakage inductance energy. A multi input many applications of 220V ac in the grid. Moreover, in the
step-up converter is introduced in [27] which is switched- off grid systems, the 220Vac 50/60 Hz can supply the home
diode-capacitor based and is suitable for multi-input consumers. An other practical application of the
applications of step-up converters. However, the mentioned experimental prototype of proposed converter can be named
converters suffer from disadvantages caused by the as grid connected PV system, with input nominal voltage of
numerous number of components in their circuit structures. 12V extracted from 50W Photovoltaic module-450J.
In [28] and [29] high voltage step-up converters are Therefore, by using eleven parallel PV modules, the output
presented. Other transformerless topologies are introduced power of 550W can be extracted and transferred to the grid
in [30]-[33]. The voltage stress on semiconductor elements similar to a general battery power generation system.
of these converters are still considerable. First Operating Mode ( t0  t  t1 ): The equivalent circuit of
In this paper, a transformerless high step-up boost this mode is shown in Fig. 3(a). Referring to Fig. 3(a) and
converter is proposed. The proposed converter not only by considering Fig. 2, the corresponding equations for this
provides high voltage conversion ratio without selecting interval would be as follows:
extremely wide duty cycles but also it has low voltage
stresses on semiconductor components. Finally, to verify i L 1 = (V i / L1 )(t − t 0 ) + i L 1 t =t 0 (1)
the practical operation of the proposed converter and i L 2 = (V i / L2 )(t − t 0 ) + i L 2 t =t 0 (2)
truthfulness of the theoretical analysis, the circuit is
implemented in laboratory and experimental results are i L 3 = (V i +V C 1 −V C 2 )(t − t 0 ) / L3 + i L 3 t =t 0 (3)
presented. where iL1 , iL 2 and iL 3 are the values of iL1 ,
t =t 0 t =t 0 t =t 0

II. THE PROPOSED CONVERT ER iL 2 and iL 3 at t0 moment. Based on Fig. 3(a) the currents
As shown in Fig. 1, the proposed converter cons ists of of switches S 1 , S 2 and diode D2 are obtained as
three inductors. The capacitors C1 , C2 , Co1 and Co 2 are i S 1 = i L1 + i L 3 − iC 2 , i S 2 = i L 2 + iC 2 and iD 2 = iL3 ,
assumed to be large enough, also, the voltages across them respectively .
are considered to be constant and equal to VC1 , VC 2 , VCo1 Second Operating Mode ( t1  t  t2 ): According to Fig.
and VCo 2 , respectively. Moreover, the circuit elements in 3(b), the currents iL1 , iL 2 and iL 3 can be calculated from
theoretical analysis are assumed to be ideal to make the (1), (2) and (3), respectively.
process of analysis simple. The active switches of the Third Operating Mode ( t2  t  t3 ): From Fig. 3(c), the
proposed converter are operated by pulse width modulation
currents iL1 , iL 2 are the same as in (1) and (2), respectively.
(PWM) with 120 shift phases, therefore, the proposed
The current iL 3 for this stage would be:
circuit has six operating modes during one switching period
(Ts ) . The voltage and current waveforms of the proposed i L 3 =V i (t − t 2 ) / L3 + i L 3 t =t 2 (4)
converter are illustrated in Fig. 2. The equivalent circuits where, iL 3 t =t 2 is the value of iL 3 at moment t2 . Based on
during one switching period are shown in Fig. 3. Note that,
Fig. 3(c) the currents of switches S 1 and S 3 is obtained as
from Figs. 3(a) and 3(d), it can be seen that VC 2 = VCo1 . and
i S 1 = i L 1 + i Co1 − i Co 2 and i S 3 = i L 3 , respectively.
VC1 = VCo 2 , respectively. The proposed converter is able to
provide higher voltage gain for duty cycle in the range of + + +

1/ 3  D  2 / 3 than other ranges of duty cycles. As a

L1 vL1 L2 vL 2 L3 vL3
− − −
iL1 iL 2 iL 3 iD1 iD 2
I PV
Low voltage Highvoltage

result, the proposed circuit is analyzed at the steady-state

iLm

C1 D1 D2 12V 15AH F 2 DC Bus Proposed DC Bus

DC / AC Inverters
ii + Lead Acid + High Step − Up (LS Starvert iS 7

mode for duty cycle values as in 1/ 3  D  2 / 3 inequality. −V +

Co1 VCo1 io DC − DC Converter
Vi + C2 Battery Inverter
− Pi = 3 180W
Vi
Po = 520W
− +
C1
PI −max = 2kVA
I i = 15A 12V in / 381V o
−VC 2 + −
A B Ro Vo V i = 12V G = 31.78 V i = 230 − 600V
12 − 24V 380V − 400V
The practical applications of experimental prototype of +
vS 1
+
vS 2
+
vS 3 +
−
L1 vL1
iL1
−
+ +
L2 vL 2
iL 2 −
+
L3 vL3
−
iL 3 iD1 iD 2
220V AC
f g = 50 − 60HZ
S1 S2 S3 Co 2 VCo 2 C1 D1 D2
iLm

−
proposed converter in section VIII is illustrated in Fig. 1(b). −
+

−
ii

− −V +
Co1 VCo1 io
Vi + C2 −
− +
C1

iS1 iS 2 iS 3 iD 3 A
+
vS 1
+
vS 2
+
vS 3
−VC 2 + B Ro Vo

+
−
S1 S2 S3 Co 2 VCo 2
− − − −
iS1 iS 2 iS 3 iD 3

Based on Fig. 1(b), the input voltage source is selected as a D3 D3

(a) (b)
12V battery (Universal Power Group 12V 15AH F2 Sealed Fig. 1. Proposed converter and practical application of experimented
Lead Acid AGM Deep-Cycle Rechargeable Battery). prototype of proposed converter; (a) proposed converter; (b) example of
Therefore, by using three parallel modules, the output practical application.
power of 540W can be extracted. By considering the high
Fourth Operating Mode ( t3  t  t4 ): Considering Fig. 3(d),
voltage gain of proposed converter (G=31.78), the output
voltage is calculated as V o = 381.4V . Consequently, based the corresponding equation for iL 3 is given as (10), and the
on Fig. 1(b), the obtained output voltage can be applied as other related equations would be as follows:
input voltage of DC/AC inverter (400 V inverters such as i L 1 = (V i −V C 1 )(t − t 3 ) / L1 + i L 1 t =t 3 (5)
LS Starvert iS7-0.75kW 400V - AC Inverter Drive Speed i L 2 = (V i −V C 1 )(t − t 3 ) / L2 + i L 2 t =t 3 (6)
Controller) to deliver the ac power and ac voltage of 220V

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IEEE TRANSACTIONS ON POWER ELECTRONICS 3

1 − DTs

vGS1 Ts
where iL1 t =t 3 and iL 2 t =t 3 are the values of iL1 and iL 2 at DTs (1 − D)Ts
t
vGS 2 yTs yTs
moment t3 . Based on Fig. 3(d) the current of switch S 3 is xTs xTs xTs
yTs
VD 2b

t
obtained as i S 3 = i L 3 + i C 1 . The current of diodes D1 and vGS 3

t
VS 2 ,VS1 1 − DTs

D3 are obtained as i D 1 = i C 1 and i D 2 = i L 1 + i L 2 − i C 1 , VC1

t
VS 3
respectively. VC 2 − VC1

Fifth Operating Mode ( t4  t  t5 ): Considering Fig. 3(e),

t
VD1
VC 2
VC1
the voltages vL1 , vL 2 and vL 3 are calculated as VD 2
t
VC 2
vL1 = vL 2 = vL3 = Vi . Hence, the related equations of iL1 , iL 2 , VC 2 − VC1
t
VD 3
VC1
iL 3 are similar to the ones in (1), (2), (4), respectively. Note v L 1,v L 2
t

that the primary initial value for the currents of iL1 and iL 2 Vi
t
V i −V C 1
would be at the moment of t4 for this interval. Based on v L3
Vi
t
Fig. 3(e) the currents of switches S 2 and S 3 are obtained as V i −V C 2 +V C 1
iL1
Vi − VC1
i S 2 = i L 2 + i L 1 and i S 3 = i L 3 , respectively. I h1 Vi
I 1 L1 L1
iL 2 t
Vi Vi − VC1
Sixth Operating Mode ( t5  t  t6 ): In Fig. 3(f) the
I h2
I 2 L2 L2 t
iL 3
I h3 Vi + VC1 − VC 2 Vi
corresponding equivalent circuit of this mode is shown. I 3 L3 L3 t
ii
Considering Fig. 3(f), the currents iL1 and iL 2 are calculated I h1 + I h 2 + I 3 + (xV iT s / L3 )
I +I +I + [(x + y )V iT s / L3 ]
from the ones in operating mode 5 and iL 3 can be 1 2 3

i D 1 ,i D 3 t
Io / y
calculated as (3), considering that the initial moment for the iD2 t
I h3
primary value of iL 3 would be at t5 . I 3
iS 1 t
I L1 + I L 2 + I L 3
I L1 + I L 2
Based on Fig. 3(f) the current of switch S 2 is obtained as I L 1 + I o + I Co1 mode1
t
i
I L1 + I L 2 + I L 3 S 2
i S 2 = i L 1 + i L 2 + i L 3 . The current of diode D2 is obtained as I L1 + I L 2
I L 2 + I C 2 mode1

iD 2 = iL3 . iS 3
t
I L 3 + I C 1 mode4
I L3
t
The voltage stress on switches S1 and S 2 are same and t0 t1 t 2 t3 t 4 t5 t6
Mode1 Mode2 Mode3 Mode4 Mode5 Mode6
have positive value when both of switches S1 and S 2 were Fig. 2. Waveforms of the proposed converter.
turned OFF ( S1 OFF and S 2 OFF) (vGS1 = 0 and vGS 2 = 0)
+ + + + +
+ L1 vL1
as mode 4. In other words, the voltage of two inductors L1 L1 vL1
iL1
−
L2 vL 2
iL 2 −
L3 vL3
−
iL 3 iD1
iL1
−
L2 vL 2
iL 2 −
L3 vL3
−
iL 3 iD1 iD 2
iD 2

and L2 are obtained as v L 2 = v L 1 =V i when one or two of

iLm

D2
iLm

C1 D1 D2 C1 D1
+ ii +
ii
Co1 VCo1 io −V +
Co1 VCo1 io
Vi + −V + C2 − Vi +
−
C1
C2 −
+
switches S1 or S 2 have received trigger pulses (modes −
C1

−VC 2 + Ro
+
Vo −VC 2 + Ro Vo
+ + − + + + −
+
vS 1 vS 2 +
1,2,3,5 and 6). when both of switches S1 and S 2 were S1
vS 1
−
S2
vS 2
−
S3 vS 3
−
Co 2
+
VCo 2
−
S1
−
S2
−
S3 vS 3
−
Co 2 VCo 2
−
iD 3 iS 2 iS 3 iD 3
iS1 iS 2 iS 3 iS1
turned OFF (mode 4) it can be obtained that D3 D3

v L 2 = v L 1 =V i −V C 1 . Consequently, the double switches S1 (a) (b)

+ + + + + +
and S 2 provide longer charge time for inductors L1 and iL1
L1 vL1
−
L2
iL 2
vL 2
−
L3
iL 3
vL 3
− iL1
L1 vL1
−
L2
iL 2
vL 2
−
L3
iL 3
vL 3
−
iD1 iD 2
iD1 iD 2

L 2 , without applying extreme duty cycle which is

iLm

iLm

D2 C1 D1 D2
C1 D1 +
ii + ii
Co1 VCo1 io −V +
Co1 VCo1 io
Vi + −V + C2 − V + C2 −
definitely one of the good features of the proposed −
C1

−VC 2 +
+ i −
Ro Vo
C1

−VC 2 +
+
Ro Vo
− −
converter. +
vS 1 S + + +
S1
+
vS 1
S2
+
vS 2
+
vS 3 Co 2
+
S1 vS 2 S 3 vS 3 Co 2 VCo 2 − − S3 − VCo 2
− 2
− −
− − iD 3
iS1 iS 2 iS 3 iD 3 iS1 iS 2 iS 3

III. A NALYSIS AT ST EADY-ST ATE M ODE D3 D3

(c) (d)
Based on the considered assumptions from the last L1
+
vL1 L2 vL 2
+
L3
+
vL 3
+
L1 vL1
+
L2 vL 2 L3 vL3
+
− − − − − −
section, the capability analysis of the proposed converter is iL1 iL 2 iL 3 iD1 iD 2
iLm
iL1 iL 2 iL 3 iD1 iD 2
iLm

C1 D1 D2 D2
C1 D1
presented as follows. ii
Co1
+
VCo1 io
ii
Co1
+
VCo1 io
−V +
Vi + C2 −V +
+ Vi +
− C2 −
−
C1
− +
C1

−VC 2 + Ro Vo
A. Voltage Gain Calculation + + + − + + +
−VC 2 + Ro Vo
−
vS 1 vS 2 vS 3 + vS 1 vS 2 +
S1 S2 S3 Co 2 VCo 2 S1 vS 3 Co 2
− − −
S2 S3 VCo 2
By applying the voltage balance law for the inductors L1 iS1 iS 2 iS 3 iD 3
−
iS1
−
iS 2
−
iS 3
−
iD 3
−

D3 D3
and L3 , the following equations can be written: (e) (f)
Vi (1 − y)Ts + (Vi − VC1 ) yTs = 0 (7) Fig. 3. Equivalent circuits of the proposed converter; (a) Mode 1; (b) Mode
2; (c) Mode 3; (d) Mode 4; (e) Mode 5; (f) Mode 6.
Vi DTs + (Vi + VC1 − VC 2 )(1 − D)Ts = 0 (8)

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where considering Fig. 2, the interval time of yTs is equal B. Voltage Stresses on Semiconductor Components
to [(2 / 3) − D]Ts [ y = (2 / 3) − D] . The interval time of xTs Considering Fig. 3, the voltage stresses on switches S1 ,
is equal to [ D − (1/ 3)]Ts [ x = D − (1/ 3)] . By simplifying S 2 and S3 and diodes D1 , D2 and D3 are summarized in
(7) and (8), the voltages across the capacitors are calculated Table II.
as follows equations: TABLE II
V C 1 =V Co 2 = (V i / y ) =V i / [(2 / 3) − D ] (9) VOLTAGE STRESSES ON SWITCHES AND D IODES FOR 1/ 3  D  2 / 3

V C 2 =V Co1 =V C 1 +V i / (1 − D ) (10) V S 1 =V S 2 =V i / (2 / 3 − D ) = [(1 − D ) / (8 / 3 − 3D )] V o during Mode 4

Considering Fig. 1, (9) and (10), the voltage gain is
concluded as follows:
G =V o /V i = [2 / (2 / 3 − D )] + [1/ (1 − D )] (11)
The voltage gain of proposed converter including
(Equivalent Series Resistance) ESRs of inductors, diodes
and switches can be calculated as follows:
GV =V o /V i = [2 / (2 / 3 − D ) + 1/ (1 − D )] / (1 + k ) (12)
where, the used parameters in (12) are defined as Table I.
where G is the inverse current gain G = I i / I o which is
always calculated from equation (11).
The voltage gain of proposed converter including ESRs of
inductors, diodes and switches can be plotted as Fig. 4(a).
The ESRs of components are
V S 3 =V i / (1 − D ) = (2 / 3 − D ) / (8 / 3 − 3D )V o during Modes 1, 2 and 6
V D 1 =V C 2 = [(5 − 6D ) / (8 − 9D )]V o during Modes 1, 2 and 6
V D 1 =V C 1 =V i / (2 / 3 − D ) = [(1 − D ) / (8 / 3 − 3D )]V o during Modes 3and 5
V D 2 =V i / (1 − D ) = (2 / 3 − D ) / (8 / 3 − 3D )V o during Modes 3 and 5
V D 2 =V C 2 = (5 − 6D ) / (8 − 9D )V o during Mode 4
V D 3 =V C 1 = [(1 − D ) / (8 / 3 − 3D )]V o during Modes 1, 2,3,5,6
C. Input Current Ripple Calculation
The input current is equal to sum of the currents iL1 , iL 2
and iL 3 . As a result, considering Fig. 2, the maximum input
current ripple can be calculated as follows:
as i i _ max = i L 1 t 4 −t 3 + i L 2 t 4 −t 3 + i L 3 t 4 −t 3

rS 1 = rS 2 = rS 3 = rS = 4 m  , rD 1 = rD 2 = rD 3 = rD = 2.9 m  , 2 / 3− D 1 1  (13)
rL 1 = rL 2 = rL 3 = rL = 5m  and the output load is selected − (1/ 3 + D )  +  V iT s
L3  L1 L 2 
as Ro = 840 , Ro = 580 and Ro = 280 for the curves
with color of red, blue, and green, respectively which have D. Average Inductors’ Currents
plotted based on equation (12). Fig. 4(b) shows the According to Fig. 3, the average values of capacitors ’
theoretical and extracted experimental voltage gain currents are calculated as Table III. Based on the topology
including ESRs of inductors, switches and diodes versus of the proposed converter shown in Fig. 1 and considering
output power for the constant duty cycle D = 0.6 . the voltage conversion ratio of the converter in (11), the
following equations would be obtained:
TABLE I PARAMETERS USED FOR EQUATION (12).
(1 / 3 − D )I L 1 − (2 / 3 − D )(I L 1 + I L 3 ) + (1 − D )I L 2
I L 1 = (5 / 4)I o / [(2 / 3) − D ] (14)
b=
(D − 1 / 3)I o I L 2 = (3 / 4)I o / [(2 / 3) − D ] (15)
−(2 / 3 − D )I L 3 + (1 / 3)(I L 1 + I o ) − (1 − D )(I L 2 − I o )
a=
(D − 1 / 3)I o
I L 3 = I o / (1 − D ) (16)
m = rS 2 (i L 2 + bi o ) − rS 1 (i L1 + i L 3 − bi o ) where I L1 , I L 2 and I L 3 are the dc values of iL1 , iL 2 and iL 3 .

A=
1
rS [3xI L1 + (1 + a)xI o + 2GyI o + 2xI L 2 ] + rL I L 1 + rD I o − mI o / 3
The maximum ( I h ) and minimum ( I ( values of inductors
yI o
currents from their waveforms in Fig. 2, input current ripple
B = (rS + rD )(1 − D ) − rD (D + 1 / 3) / y − rD + (rS I L 3 + A ) / I o
and maximum input current ripple under the condition of

 2  mI o x [(1 + a )I o + I L 1 ] + 3GyI o + xI L 3 
  using minimum value of inductors (minimum value of
 rL + rD  I L 3 + + rS  
 3  3 −[1 + (1 / 3 + D ) / (2 / 3 − D )] yI o 
 
C =  inductors in section VII are calculated to achieve x%=(10-
yI o
15)% of the average inductor currents) are obtained as
k = (A + B + C − m ) / Ro
equations in Table IV.
TABLE III
K =0

Ro = 840
A VERAGE CAP ACITORS’ CURRENTS DURING OP ERATING MODES
Vo
Vi Ro = 580
Vo I L 2 − I o during Modes 3 and 4  , I L 2 + I L 3 − I o during Mode 2 
Vi
Ro = 280
I Co1 −(I L 1 + I o ) during Modes 5 and 6 ,
Analytical [(1 / 3)(I L 1 + I o ) − (2 / 3 − D )I L 3 − (1 − D )(I L 2 − I o )] / (D − 1 / 3) during Mode 1
Experimental
I C1 −I L 3 during Modes 1,2 and 6 ,[(1 − D ) / (2 / 3 − D )]I L 3 during Mode 4 

D Po [W ] I Co 2 −I o during Modes 1,2,3,5 and 6 , [(D + 1 / 3) / (2 / 3 − D )]I o during Mode 4 
(a) (b) −I L 2 during Modes 2,3 and 4 ,I L 1 + I L 3 during Mode 6 ,I L 1 during Modes 5
Fig. 4. (a) Voltage gain including ESRs of inductors, switches and diodes
IC 2 [(1 / 3 − D )I L 1 − (2 / 3 − D )(I L 1 + I L 3 ) + (1 − D )I L 2 ] / (D − 1 / 3) during Mode 1
versus R o and D ; (b) voltage gain including ESRs of inductors, switches
and diodes versus Po for D = 0.6 .

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TABLE IV voltage stresses on switches (VS _ max / Vo ) and diodes

MAXIMUM AND MINIMUM VALUES OF INDUCTORS CURRENTS, INP UT
CURRENT RIP P LE AND MAXIMUM INP UT CURRENT RIP P LE . (VD _ max / Vo ) , the normalized average current stresses on
I 1 = (5 / 4)I o / [(2 / 3) − D ] − [V i (1/ 3 + D )T s ] / 2L1 switches during the conducting mode of switch (I S _ on / I i ) ,
I 1 , I h1
I h1 = (5 / 4)I o / [(2 / 3) − D ] + [V i (1/ 3 + D )T s ] / 2L1 the normalized average current stresses on diodes
I 2 = (3 / 4)I o / [(2 / 3) − D ] − [V i (1/ 3 + D )T s ] / 2L2 (I D −on / I i ) and number of switches ( N S ) , diodes ( N D ) ,
I 2 , I h2
I h 2 = (3 / 4)I o / [(2 / 3) − D ] + [V i (1/ 3 + D )T s ] / 2L2 inductors ( N I ) , capacitors ( NC ) and whole number of
I 3 = I o / (1 − D ) −V i DT s / (2L3 ) , components (N Component ) . The presented dc-dc converters in
I 3 , I h3
I h 3 = I o / (1 − D ) +V i DT s / (2L3 ) Table VI are high voltage gain converters. In these
 (1/ 3) + D (1/ 3) + D (2 / 3) − D  converters by using diode-capacitor circuits the voltage gain
i i i i =  + − V iT s
 L1 L2 L3  is increased. Between the high voltage gain converters ,
x %I i  (2 / 3) − D 2  there is an important characteristic as ratio of voltage gain
i i −max under i i −max = +
2 1  D (1 − D ) (2 / 3) − D  to whole components number ( G / NComponent ) which can be
using (48)-(50) +
(2 / 3) − D 1 − D
a reasonable criterion for evaluating the performance of the
converters considering voltage gain (high) and components
IV. PROPOSED DEVELOPED CONVERT ER number (low). Therefore, the converter which has higher
In this part, the developed multidevice converter in Fig. 5 is value of G / NComponent would have better performance than
proposed based on multidevice converter idea [35]. The other converters. Fig. 6(a), illustrates the G / NComponent
switches of the proposed multidevice converter (PMDC) are
same as proposed converter. The voltage and current versus duty cycle. This figure shows that the proposed
waveforms of PMDC are same as the illustrated in Fig. 2. converters has the highest value of G / NComponent in
DC characteristics of PMDC is given in Table V. comparison to other conventional converters and converters
Accordingly, the proposed developed converter, has the A, B, C specially during duty cycle range of
same voltage gain and voltage stresses on switches and 1/ 3  D  2 / 3 . Considering Fig. 6(b), it can be seen that
diodes as the main proposed converter by using decreased V S − max /V o in the proposed converters is lower than all the
components number.
+
compared conventional converters in the literature and
+
L1 vL1 L3 vL3
iL1
− −
iL 3 iD1 iD 2 converters A, B, C. Moreover, V D − max /V o curves are
iLm

C1 D1 D2
ii
−V +
Co1
+
VCo1 io plotted for the given converters in Fig. 6(c). I S _ on / I i
Vi + −
− +
C1

Ro Vo
+
vS 1
+
vS 2
+
vS 3 +
− curves are plotted for the given converters in Fig. 6(d).
S1 S2 S3 Co 2 VCo 2
iS1
− −
iS 2 iS 3
−
iD 3
−
PMDC can provide a considerable high voltage gain by
D3
applying less number of components in comparison to the
Fig. 5. Proposed multidevice converter all presented converters expect the converters in [21], [29],
[30], [32] and converter C.
TABLE V
[31] [18] [6] , [28] [21]
DC CHARACTERISTICS OF P ROP OSED MULTIDEVICE CONVERTER Proposod Converters [22] [30] [29],[33] [24]
Converters[A], [B]
I L1 , I L 3 I L 1 = 2I o / [(2 / 3) − D ] , I L 3 = I o / (1 − D ) Converter [C]
[33]
[31] V S − max
IS1 , IS 2 , IS 3 I S 1 = I S 2 = [(D + 1/ 3) / (2 / 3 − D )]I o , I S 3 = I o / (1 − D ) G [22]
[18] Vo
N Component
[30]
L1−min and Ro (1 / 3 + D )(2 / 3 − D ) R D (1 − D ) [29]
L1−min = , L3−min = o [21]
[6] , [28]
L3−min 2x %f sG x %f sG [24]
[A ],[B ],[C ]
Proposod Converters

i i −max i i −max = [(2 / 3 − D ) / L3−min − (1/ 3 + D ) / L1−min ]V iT s D D

(a) (b)
[29] Proposod Converter
PMD C
V. COM PARISON RESULTS [22]
[24]
[31]
Proposod Converters
[A ],[B ],[C ]
[21]
[6] , [28]
[24]
Converters[A]
Converter [B]
[29],[33]
[30] [18]
Converter [C]
The characteristics of the proposed converter, proposed [21]
[6],[26],[18] I S − max
[30] [33]
[31]
V D −max Ii
multidevice converter (PMDC), presented high voltage gain Vo
[22]

converters in [6], [28], [18], [21], [22], [24], [29], [30],

[31], [32] and [33], the converters utilizing three inductors
include a cascade of 3 boost converters (Converter A), the
D D
quadratic converter to an equivalent of 3 inductors stage (c) (d)
(converter B) and conventional three phase converter Fig. 6. (a) Ratio of voltage gain to components number curve versus duty
(Converter C) are summarized in Table VI. DC cycle; (b) normalized maximum voltage stress on switch; (c) normalized
maximum voltage stresses on diode; (d) normalized maximum current
characteristics include the voltage gain, the normalized stress on switch.

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TABLE VI COMP ARING RESULTS OF DIODE -CAP ACITOR BASED H IGH VOLTAGE GAIN CONVERTERS
DC- Vo
DC VS VD I S _ ON ID NComponent
Conv Vi NS ND NI NC
Vo Vo Ii Ii
erters
[6]
4 1 D1 , D2 , D3 : 0.5 , D4 : 1+ D 1
and S1 , S 2 : S1 : , S2 : 0.25 2 4 2 4 12
[28] 1− D 4 0.25 4D 2D
4 1 1 1 2+D 1 + 2D
[18] S1 : , S2 : Max: Max: 2 6 1 5 14
1− D 4 2 2 4D 4D
1 − 2D
1 D1 :
2(1 − 3D + 2D 2 )(1 − D )
S1 : 1  D  ,
1
2(1 − D ) D1 , D2 , Do : , S1 :
1− D
2 1− D 
[21] 1 − 2D
2
1 − 2D 2 2 4 1 3 10
D2 : , D3 :
S2 :
1 D3 : 1  D  1 2(1 − D )2 1− D
2 1− D  S2 :
2
2D (1 − D )
Do :(1 − 2D ) / [2D (1 − D )]
1 + 3D 1+ D 1+ D 3D − 1 1
[22] S1 , S2 : vD max : 2 8 4 2 16
1− D 1 + 3D 1 + 3D 3D + 1 3D + 1
5 D1 , D2 , D3 , D4 : 0.4 I S 1 = (2 + D ) / 5D ,
[24] S1 , S 2 : 0.2 0.2 2 5 2 5 14
1− D D5 : 0.2 I S 2 = 0.4 / D

3+ D 1 2 1+ D D1 , D 3 : 1/ (3 + D )
[29] S1 , S 2 ; D1 , D2 , D3 : 2 3 2 3 10
1− D 3+ D 3+ D (3 + D )D D2 : (1 − D ) / [D (3 + D )]

3− D 1 2 1 1 D3 :1/ (3 − D )
[30] S1 , S2 : Do : , D1 , D2 : 2 3 2 3 10
1− D 3− D 3− D 3− D D (3 − D ) D1 , D2 : (1 − D ) / [D (3 − D )]
1 + 2D
S' : ,
1 + 3D 2(1 + D)
Do : , D11 , D21 :
1 + 3D 1 1 + 3D 1 1
[31]
1− D
S , S1
1 + 3D
, S: Do : 4 5 3 1 14
1− D
, D22 , D12 :
D 1 + 3D 1 + 3D
1+ D 1 + 3D 1 + 3D
S2 :
1 + 3D

1
D1 , D2 , D3 : Max:
3+ D 1 3+ D 7 + 9D 6
[33] Max: 6 14 6 8 34
1− D 3+ D 2 10(3 + D ) 5(3 + D )
8 diodes:
3+ D
S1 : (1 − D )
2

1 D1 (1 − D )
2
S 1 :1 , S 2 :(1 − D ) D1 :1 , D 2 :(1 − D ) ,
[A]
S 2 : (1 − D ) , 3 3 3 3 12
(1 − D )3 D2 : (1 − D ) , D3 : 1 S 3 :(1 − D ) 2
D3 :(1 − D )2
S3 : 1
(4D − 2D 2 )(1 − D ) + D
D1 (1 − D )
2 D1 :
1 − (1 − D ) (2 − D )
2
1− D
1 S1 : (1 − D ) S1 :
[B]
D2 : D (1 − D ) D Do1 :(1 − D ) , Do 2 : (1 − D )2 2 4 3 3 12
(1 − D )3 S2 : 1
D3 : (1 − D ) , D : 1 S 2 : (1 − D ) 2
(2D 2 − 4D + 1)(1 − D )
D2 :
D

1 1 1
[C] S1 , S 2 , S3 : 1 D1 , D2 , D3 : 1 S: 3 3 3 1 10
1− D 3 3(1 − D )

(7 / 12) + D 1 − D
2 S1 , S 2 : S1 :
5 − 6D (8 / 3) − 3D D 1− D
P rop (2 / 3) − D 1− D D1 , D2 : D1 , D3 :
osed 8 − 9D 0.75 1− D 8 / 3 − 3D
1 8 / 3 − 3D 1− D
S2 :
(2 / 3) − D
3 3 3 4 13
conv + D3 : (8 / 3) − 3D D D2 :
erter 1− D 2/ 3− D 8 / 3 − 3D (8 / 3) − 3D
S3 : 2 / 3− D 1
8 / 3 − 3D S3 :
8 / 3 − 3D D
S1 , S 2 : S 1, S 2 :
2
5 − 6D 1− D
2 / 3− D 1− D D1 , D2 : [(1/ 3) + D ](1 − D ) D1 , D3 :
P MD 8 − 9D 8 / 3 − 3D
1 8 / 3 − 3D [(8 / 3) − 3D ]D 3 3 2 3 11
C + 1− D (2 / 3) − D
1− D 2/ 3− D D3 : D2 :
8 / 3 − 3D (2 / 3) − D (8 / 3) − 3D
S3 : S3 :
8 / 3 − 3D [(8 / 3) − 3D ]D

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(600V, 47A). and the switch S3 is considered as

VI. Calculations of Losses NDPL180N10B (100V, 180A). The used diodes D1 , D2
In this section, the conduction and switching losses of and D3 are considered as MUR1560.
proposed converter are calculated to obtain the efficiency.
As a result, the internal resistors of diodes (rD ) , switches TABLE VII POWER LOSS CALCULATION FOR ALL COMP ONENTS OF
(rS ) , inductors (rL ) , capacitors (rC ) , forward drop voltage PROP OSED CONVERTER
PCond ,S 1 = (V FS 1 + rS 1I S 1 / D )I S 1 , PCond ,S 2 = (V FS 2 + rS 2 I S 2 / D )I S 2
of diodes (VFD ) and forward drop voltage of switches
PCond
PCond ,S 3 = (V FS 3 + rS 3I S 3 / D )I S 3 , PCond ,D 2 = [V FD 2 + rD 2 I o / (1 − D )]I o
(VFS ) are considered for calculating power los ses.
PCond ,D 1 = PCond ,D 3 = [V FD + rD I o / [(2 / 3) − D ]]I o ,
The average values of currents of switches and diodes are
Psw ,S 1 = f SV S 1 (I L1 + I L 2 )t f −S 1 / 6 , Psw ,S 2 = f SV S 2 (I L 1 + I L 2 )t r −S 2 / 6
concluded as I S 1 = I L 1 − I o = [(7 /12) + D ] / [(2 / 3) − D ]I o ,
Psw Psw ,S 3 = f SV S 3I L 3 (t r −S 3 + t f −S 3 ) / 6 , Psw ,D 2 = f SV i I rrt b / [6(1 − D )]
I S 2 = I L 2 , I S 3 = I L3 and I D1 = I D 2 = I D3 = I o .
Psw ,D 1 = Psw ,D 3 = f SV i I rrt b / [(2 / 3 − D )6]
According to Ref [34] and (14)-(16), conduction losses of
PS ,Tot PS ,Tot = PCond ,S1 + PCond ,S 2 + PCond ,S 3 + Psw,S1 + Psw,S 2 + Psw,S 3
switches ( PCond , S1 , PCond , S 2 and PCond , S 3 ) and diodes
( PCond , D1 , PCond , D 2 and PCond , D3 ), the switching losses for the PD ,Tot
PD,Tot = PCond ,D1 + PCond ,D2 + PCond ,D3 + Psw,D1 + Psw,D 2 + Psw,D3
switches ( Psw, S1 , Psw, S 2 and Psw, S 3 ) and diodes ( Psw, D1 ,
PCond ,L
PCond ,L = rL 1I L 12 + rL 2 I L 22 + rL 3I L 32
Psw, D 2 and Psw, D 3 ), total power loss of switches ( PS ,Tot ) ,
total power loss of diodes ( PD ,Tot ) , total conduction loss of PCore _ total = (PC 1 + PC 2 + PC 3 )V e ,

inductors ( PCond , L ) , total core loss of inductors ( PCore _ total ), PCore B L 1 = [V i (1 − y )T s ] / 2N 1Ac so, PC 1 in [kW/m3] from datasheet
B L 2 =V i (1 − y )T s / N 2Ac , so, PC 2 in [kW/m3] from datasheet
total conduction loss of capacitors ( PCond ,C ) and total power
B L 3 =V i DT s / N 3Ac , so, PC 3 in [kW/m3] from datasheet
loss ( PLoss ) are calculated as shown in Table VII. Fig. 7(a)
PC 1 = rC I o 2 (5 / 3 − 2D ) / [(1 − D )(2 / 3 − D )]
illustrates the comparing results of extracted efficiency of
(D − 1/ 3)I L 12 + (2 / 3 − D )(I L 1 + I L 3 )2 + (1 − D )I L 2 2 
 
proposed converter for three input voltages of V i = 12V , PC 2 = rC 2  

 +[(1 − D ) I − (2 / 3 − D )( I ) − I / 3]2
/ ( D − 1/ 3) 

V i = 24V and V i = 30V , three presented converters in
L2 L3 L1
PCond ,C
[(I L 2 − I o )2 + (I L 2 − I o + I L 3 )2 (2 / 3 − D ) + (I L 1 + I o ) 2 ] / 3 
 
[24], [28] and converter C versus output power. Fig. 7(b) PCo 1 = rCo 1  

 +[( D − 1) I L2 − I L1 / 3 − [(2 / 3) − D ]( I L3 − I o )]2
/ ( D − 1/ 3) 

shows the efficiency versus output load for three input
voltages. Efficiency curves of proposed converter in Figs. PCo 2 = rCo 2 I o 2 [D + (1/ 3)] / [(2 / 3) − D ]
7(a) and 7(b) are plotted. The used duty cycle to plot Fig. 7 PCond ,C = PC 1 + PC 2 + PCo1 + PCo 2
is D = 0.6 . PLoss
PLoss = PS ,Tot + PD,Tot + PCond ,C + PCond ,L , Efficiency = Po / (Po + PLoss )
For input voltage V i = 12V , the switches S1 , S 2 are
considered as IRFP4668PbF (200V, 130A) and S3 is Conventional ThreePhaseConverter
[24] [28]
considered as NDPL180N10B (100V, 180A). Therefore, Efficiency
the parameters of switches are as V FS 2 =V FS 1 = 0.7V , Efficiency

V FS 3 = 0.75V , rS 1 = rS 2 = 4 m  , rS 3 = 2.7 m  , Efficiency

(V i = 30V )
tf _S1 = 74ns , t r _ S 2 = 105ns and Proposed Converter (V i = 30V )
Proposed Converter (V i = 24V ) (V i = 24V )
Proposed Converter  Analytical  Analytical
tr _S 3 +tf _S 3 = (320 + 130) ns . The used diodes D1 , D2 and (V i = 12V ) 
 Experimental
(V i = 12V )  Experimental


D3 are considered as DPG60I300HA (300V, 60A). Po [W ] I o [ pu ]

(a) (b)
Accordingly, the diodes parameters are as Fig. 7. (a) Efficiency of proposed converter and conventional converters
V FD 1 =V FD 3 = 1.1V , V FD 2 = 0.75V , versus output power; (b) Efficiency of proposed converter versus output
load.
rD 1 = rD 2 = rD 3 = 2.9 m  , t b −D 1 = t b −D 2 = t b −D 3 = 35ns ,
I rr 1 = I rr 2 = I rr 3 = 1 A . Moreover, the internal resistors of VII. Design Considerations
capacitors inductors are considered as A Inductor Selection
rC 1 = rC 2 = rCo1 = rCo 2 = 2m  and rL 1 = rL 2 = rL 3 = 5 m  , Based on [37], the inductors L1 , L 2 and L 3 are designed
respectively. In Table VII, power loss calculation for all such that the ripple in the inductors currents is around
components of the proposed converter is presented.
x%=(10-15)% of the average value of these inductor’s
Moreover, for input voltages of V i = 24V and V i = 30V ,
currents. Under this condition the losses and input current
the switches S1 , S 2 are considered as IXKH47N60C ripple can be decreased. As a result, the minimum values of

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the inductances of three inductors has to be as following V S 3 = 30V which are verified by Fig. 8(a). Considering
equations: the fact that the efficiency of the proposed converter for
L1−min = Ro (1/ 3 + D )(2 / 3 − D ) / [x %(5 / 4)f sG ] (17) 520W is approximately near to 90.77 % the extracted
L2−min = Ro (1/ 3 + D )(2 / 3 − D ) / [x %(3 / 4)f S G ] (18) results of experimental waveforms are acceptable. The
L3−min = Ro D (1 − D ) / [x %f S G ] (19) maximum and minimum voltage stresses on diodes from
Considering (17)-(19), and the parameters as f S = 50kHz , Table II are calculated as V D 1_ max = 210V and

Ro = 280 and D = 0.6 , x % = 15% , the inductances V D 1_ min = 180V , V D 2 _ max = 210V and V D 2 _ min = 30V ,
values are calculated as L1− min = 71.33 H , V D 3 = 180V which almost are equal to the presented
L2− min = 118 H and L3− min = 276 H . where G is replaced results in Fig. 8(b) and left figure of Fig. 8(c). According to
(9), (10), (12), the capacitors’ voltages and the output
as G = 32.5 from (11) in (17)-(19).
voltage are calculated as V C 1 =V Co 2 = 180V ,
B. Capacitor Selection
Considering Refs [37] and [38], to obtain the more V C 2 =V Co1 = 210V , V o = 381.4V which verify Fig. 8(c)
accurate designing of capacitors, then, the total peak-to- and left figure of Fig. 8(d), respectively.
peak value of the voltage ripple of each capacitor is equal to TABLE IX Experimental Parameters
sum of the voltage ripple across each capacitor (V C ) and
L1 = 80 [ H ] , L2 = 120 [ H ] ,
voltage ripple caused by the ESR of each capacitor V i = 12[V ] / V o = 381[V ]
L3 = 280 [  H ] TDK P C40EE30-Z core
(V C − ESR = rC I C ) . An important condition in the design
f s = 50[kHz ] C1 = C 2 = 50[F ] , C o1 = C o 2 = 200 [ F ]
of the output capacitors is the hold-up time requirement for
D = 0.6 S 1 , S 2 : IRFP 4668P bF, S 3 : NDPL180N10B
step-load response [38]. As a result, the minimum value of
Ro = 280[] D1 , D 2 and D 3 : DP G60I300HA
capacitors is calculated as Table VIII.
ESR of parasitic elements:
Po = 520[W ]
TABLE VIII M INIMUM VALUES OF CAP ACITORS. Capacitors = 2[m ], Inductors = 5[m ]
 2/ 3−D 
[(1 / 3) + D ][(2 / 3) − D ] 2 + 
1− D 
C o 2 m _ ESR = , C o 2 _Th = 
C o 2 _ min  0.01 1  (0.01)Ro (0.1f s )
Ro 2  − rCo 2 f s
 G Ro 2 


C o 2  max C o 2 _ min ESR and C o 2 _ min transient holding time  V S 1 ,V S 2 [100 V /div ] V S 3 [25 V /div ]
Time / div = 5 s Time / div = 5 s
1 + (1.25 / y )
C o1m −ESR =
0.01Ro [1 / y + 1 / (1 − D )] / G − rCo1G 3f s (a)
C o 1_ min G
C o1_Th =
0.01Ro (0.1f s )[1 / y + 1 / (1 − D )]

C o 1  max C o 1_ min ESR and C o 1_ min transient holding time 
C 1_ min 2/ 3−D
C1_ min = V D 1 [100 V /div ] V D 2 [100 V /div ]
ESR
0.01Ro / G − rC 1 (5 / 3 − 2D ) / (1 − D )f s Time / div = 5 s Time / div = 5 s

C 2 _ min (5 / 4) / (2 / 3 − D ) / 3 + (2 / 3 − D ) / (1 − D )
C 2 _ min = (b)
ESR
0.01Ro [(1 / 1 − D ) + 1 / (2 / 3 − D )] / G − rC 2G 3f s
Considering Table VIII and the parameters as f S = 50kHz ,
rC 1 = rC 2 = rCo1 = rCo 2 = rC = 2m  , Ro = 280 and
V D 3 [100 V /div ] V C 1 ,V Co 2 [100V /div ]
D = 0.6 , the capacitors values are calculated as Time / div = 5 s Time / div = 5 s

C o 2−min = 154.7 F C o1− min = 132 F , C1− min = 15.54 F , (c)

C 2− min = 28.93 F . As a result, the capacitors can be
selected as C o1 = C o 2 = 200 F , and C1 = C 2 = 50 F in
Table IX section VIII. V C 2 ,V Co 1 [100V /div ] V o [200 V /div ]
Time / div = 5 s Time / div = 5 s

VIII. EXPERIM ENTAL RESULTS (d)

Fig. 8. Experimental results; (a) VS 1 or VS 2 (left) and VS 3 (right); (b)
In order to verify the theoretical analysis, the
experimental results are extracted. The values of utilized VD1 (left) and VD 2 (right); (c) VD 3 (left) and VC1 (right); (d) VC 2 .(left)
elements are summarized in Table IX. Fig. 8 illustrates the and V o (right)
experimental results of voltage stresses on switches and Fig. 9 shows the experimental results of inductors’,
diodes, voltages across the capacitors and the output switches’, diodes’ currents and also input current.
voltage. Considering Table II, the voltage stresses on The theoretical value of output current for the calculated
switches are calculated as V S 1 =V S 2 = 180V and output voltage as V o = 381.4V and output power of

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Po = 520W is calculated as I o = 1.36A . As a result, based

Losses of
Capacitors
2.97W (5%)
on (14)-(16) the average inductor’s currents of iL1 , iL 2 and
Losses of Inductors
4.7W (8%)
Losses of Diodes

iL 3 are calculated as I L 1 = 25.56A , I L 2 = 15.31A and 4.1W (7%)

Losses of Switches

I L 3 = 3.4A . Consequently, according to Table IV, the 45.96W (80%)

maximum and minimum values of current iL1 , iL 2 , iL 3 are

calculated as I h 1 = 27A and I 1 = 24.07A , I h 2 = 16.24A (a) (b)
Fig. 10. (a) T he power distribution among the components at the rated load
and I 2 = 14.37A , I h 3 = 3.65A and I 3 = 3.14A which are condition; (b) Implemented prototype of the proposed converter.
same as obtained values in Figs. 9(a), 9(b) and 9(c),
respectively. The average currents of diodes D1 and D3 IX. CONCLUSION
during yT S = 1.33 sec is calculated as In this study, a DC-DC converter with merits of high step-
I D1 =I D3 = (I o / y ) = 20.4A which is close to the up voltage conversion ratio and low voltage stresses on
yT s yT s
switches is proposed. The proposed converter is capable of
obtained value from Fig. 9(h). Considering Fig. 3, the providing a high voltage gain without utilizing transformer
maximum and minimum currents of diode D 2 is calculated or coupled inductor or adopting a wide range of duty cycle.
as i D 2− max = i L 3−max = I h 3 = 3.65A and Due to the low voltage stresses on components, the power
i D 2− min = i L 3−min = I 3 = 3.14A , respectively which are the circuit elements can be selected to be low voltage rated,
consequently, the related costs and losses would be
same values in Fig. 9(i). The power distribution among the
reduced. According to the comparison results section, the
components at the rated load condition ( Po = 520 [W ] ) is proposed converter has better performance on voltage
given in Fig. 10(a). The implemented prototype of the conversion ratio with acceptable number of components in
proposed converter is presented in Fig. 10 (b). comparison to the other circuits of the same type. To
demonstrate the practical capability of the proposed
converter, a primary prototype is implemented and the
results are extracted for 520-W and compared with
theoretical results.
i L 1 [10 A /div ] i L 2 [5 A /div ]
Time / div = 5 s Time / div = 5 s

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IEEE TRANSACTIONS ON POWER ELECTRONICS
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Zahra Saadatizadeh was born in Tabriz, Iran, in 1991. She
received the B.S. degree in P ower Electronic Engineering
from Azarbaijan Shahid Madani University, Tabriz, Iran, i n
2013 and the M.S. degree from University of Tabriz, Tabriz,
Iran, in 2015. She is currently working toward the P h.D.
degree in P ower Electronic Engineering at the Department of
Electrical and Computer Engineering, University of Tabriz,
Tabriz, Iran. Her major fields of interest include renewable
energy sources, the analysis, modelling, design and
implementation of power electronic converters and their applications.
Pedram Chavoshipour Heris was born in Tabriz, Iran, in
1988. He received the B.S. degree in P ower E lectronic
Engineering from Azad university of Tabriz, Iran, in 2011 and
the M.S. degree from Science and Research branch university
of Tehran, Iran, in 2016. He is currently the research assistant
in power electronic lab at the Department of Electrical and
Computer Engineering, University of Tabriz, Tabriz, Iran. His
major fields of interest include the analysis, modell ing, design
and implementation of power electronic converters and their
applications such as in renewable energy sources.
Mehran Sabahi was born in Tabriz, Iran, in 1968. He
received the B.S. degree in electronic engineering from the
University of Tabriz, Tabriz, Iran, the M.S. degree in
electrical engineering from Tehran University, Tehran, Iran,
and the P h.D. degree in electrical engineering from the
University of Tabriz, in 1991, 1994, and 2009, respectively.
In 2009, he joined the Faculty of Electri cal and Computer
Engineering, University of Tabriz. He was an Assistant
P rofessor from 2009 to 2013 and has been Associate P rofessor since 2014. His
current research interests include the power electronic converters/inverters and the
applications of power electronics in renewable energy
systems.
Ebrahim B abaei (M’10, SM’16) received the P h.D. degree
in Electrical Engineering from University of Tabriz, in 2007.
He is the author and co-author of more than 440 journal and
conference papers. He also holds 23 patents in the area of
power electronics. His current research interests include the
analysis, modelling, design, and control of P ower Electronic
Converters and their applications, Renewable Energy
Sources, and FACTS Devices.
P rof. Babaei has been the Editor-in-Chief of the Journal of Electrical Engineering of
the University of Tabriz, since 2013. He is also currently an Associate Edit or of the
IEEE Transactions on Industrial Electronics and IEEE Transactions on P ower
Electronics. He has been the Corresponding Guest Editor for different special issues
in the IEEE Transactions on Industrial Electronics. In addition, P rof. Babaei has been
the Track Chair, organizer of different special sessions and Technical Committee
member in most important international con ferences organized in the field of P ower
Electronics. Several times, he was the recipient of the Best Researcher Award from
the University of Tabriz. P rof. Babaei has been included in the Top One P ercent of
the World’ s Scientists and Academics according to Thomson Reuters' list in 2015,
2016 and 2017. From Oct. 1 st until Dec. 30th 2016, he has been a Visiting P rofessor
at the University of L’ Aquila, Italy.