www.ietdl.

org
Published in IET Power Electronics
Received on 14th November 2012
Revised on 23rd September 2013
Accepted on 14th October 2013
doi: 10.1049/iet-pel.2013.0205

ISSN 1755-4535

Quadratic boost converter with low buffer capacitor

stress
Yuan-mao Ye, Ka Wai Eric Cheng
Department of Electrical Engineering, The Hong Kong Polytechnic University, Kowloon, Hong Kong
E-mail: eeecheng@polyu.edu.hk

Abstract: A new quadratic boost converter is presented in this study. Compared with the conventional quadratic boost converter,
the proposed converter has the feature of lower buffer capacitor voltage stress. This advantage is very valuable for high voltage
and high-voltage gain applications. The proposed converter also employed only one active switch and two LC (inductor-
capacitor) filters. Detailed analysis for its continuous current mode operation and discontinuous current mode operation both
are presented. In addition, modelling for the proposed converter is also developed in this study. A prototype circuit is built
and the experimental results confirm the feasibility and performance of the high step-up converter.

1 Introduction capacitor is therefore the same as the output voltage level of

Switched-mode DC–DC converters with high-voltage
conversion ratio have been extensively applied in many
industrial applications [1–3]. In theory, classical boost and
buck–boost converters can produce high step-up voltage
gain with extremely high duty ratio. In practice, however,
the voltage conversion ratio is limited by the power loss of
switches and the parasitic resistance of inductors and
capacitors [4], as well as the component stresses that
increase at the extreme duty cycle and the voltage
conversion ratio is usually limited to below 8–10 [5]. The
resonant converters have also been popular in
high-frequency lower loss power conversion [3–4], but it is
not especially suitable for high-voltage conversion unless a
power transformer is employed.
During the past couple of decades, many topologies have
been proposed to achieve wider voltage gain with new
conversion features [6–16]. The typical methods to obtain
high-voltage gain include clamped-inductor [8, 9] and
charge-pump techniques [10–12]. Another branch of these
developments is quadratic converters, which employ a
single active switch, whereas the voltage gains are the
quadratic of classical converters [13–16]. For instance, the
voltage gain of classical buck converter is the same as its
duty ratio, whereas the voltage gain of the quadratic buck
converter is the quadratic function of its duty ratio [14, 15].
A quadratic boost converter has been developed in [16]. It
has attracted many researchers’ attention because it can
provide higher voltage transfer ratio. The corresponding
modelling and control strategies are presented in [17, 18]
and its quasi-resonant version has also been developed in
[19] that is more advanced performance than the
conventional quasi-resonant converter [20]. However, this
quadratic boost converter configuration is actually a cascade
of two boost converters. The voltage across its buffer
the classical boost. It means the buffer capacitor voltage
stress is always higher than its input voltage.
In this paper, a new quadratic boost topology is developed.
Its voltage transfer characteristic is exactly the same as the
conventional quadratic boost converter aforementioned and
both are the quadratic of that of the classical boost
converter. However, the present quadratic boost converter is
actually developed by a cascade of one buck–boost and one
boost converters. Because of this unique structure, its buffer
capacitor voltage can be either lower or higher than input
voltage, and always lower than that of conventional
quadratic boost converter at any same duty ratio. Therefore
the proposed topology is more suitable for high-voltage
conversion applications. The continuous current mode
(CCM) and discontinuous current mode (DCM) of the
proposed converter both are analysed in detail and its
mathematical model is also derived in this paper.
This paper is therefore organised as follows: the circuit
configuration and its operation analysis in CCM are
presented in Section 2. In Section 3, modelling of the
proposed converter is given. The features of its higher
voltage transfer ratio and lower buffer capacitor stress are
discussed in Section 4. The performance of its DCM
operation is explained in Section 5. Experimental validation
is presented in Section 6. Finally, the paper is concluded in
Section 7.
2 Analysis of the proposed converter
2.1 Converter topology
The topology of the proposed converter is shown in Fig. 1,
where Vin is the input source voltage, VO is the output
voltage and VC1 is the voltage across the buffer capacitor
C1. This converter employs only one active switch Q, three

1162 IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1162–1170

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0205
 www.ietdl.org

Fig. 1 Proposed quadratic boost converter

diodes and two LC filters sharing a common duty ratio.

Without loss of generality, the following assumptions have
been made for the theoretical analysis:

(1) The converter operates in CCM

(2) All components including input power source are ideal,
that is, no voltage drop and on-resistance.
(3) Filter capacitors C1 and C2 both are large enough and their
voltages are constant.

There are two working states according to the switch Q Fig. 3 Some idealised waveforms of the proposed converter in
being turned on and off as shown in Figs. 2a and b. Fig. 3 CCM
shows some idealised waveforms of this converter
configuration and its detailed analysis is presented as follows.
can be expressed as (1)
⎧
2.2 Transistor on state (t0–t1) ⎪
⎪ V
⎪
⎪ iL1 = IL1 t0 + in t
⎪
⎪ L1
When the active switch Q is turned on, diodes D1 and D2 both ⎪
⎨ Vin + VC1
are reverse-biased. Vin, L1, D3 and the switch Q form a iL2 = IL2 t0 + t (1)
⎪
⎪ L2
closed-loop. The input voltage Vin is developed across the ⎪
⎪
⎪
⎪ iQ = iL + iL2
inductor L1 that causes the inductor current iL1 to increase ⎪
⎩i = i 1
linearly and in another closed-loop formed by Vin, C1, L2 in Q
and Q, the voltage (Vin + VC1 ) is developed across the
inductor L2 causing a linear increase in current iL2 . The where IL1 t0 and IL2 t0 are the initial values of iL1 and iL2 when
state circuit is shown in Fig. 2a and the currents flowing the switch is turned on, and they are also the minimum
through the two inductors both rise from their minimum values of the currents flowing through L1 and L2,
values, respectively, as shown in Fig. 3 (time: t0–t1) and respectively; iQ is the current flowing through the switch Q
and iin is the input current. During this period, diodes D1
and D2 are reverse-biased hence their currents both are zero
consistently. The two closed loops aforementioned share the
common active switch Q. The current flowing through Q is
therefore the sum of iL1 and iL2 . In addition, the switch Q is
connected in series with input power source, the current
flowing through the two of them therefore are the same and
both equal to the sum of iL1 and iL2 . At the end of this
period, the currents flowing through L1 and L2 both reach
their peaks IL1 t1 and IL2 t1 as given by (2)
⎧
⎪ Vin
⎪
⎨ IL1 t1 = IL1 t0 + UTS
L1
Vin + VC1 (2)
⎪
⎪
⎩ IL2 t1 = IL2 t0 + UTS
L2

where TS is the switching cycle of the converter and U = ton/

TS is its duty ratio, ton is the conduction duration of the switch
Q, that is, t1–t0.

2.3 Transistor off-state (t1–t2)

Fig. 2 State circuits of the proposed converter
a Q switch-on state When Q is turned off, the diode D3 is reverse-biased. The
b Q switch-off state inductor current iL1 diverts from Q to D1 and decreases

IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1162–1170 1163

doi: 10.1049/iet-pel.2013.0205 & The Institution of Engineering and Technology 2014
www.ietdl.org
linearly because the voltage across L1 becomes negative of
the value VC1 . At the same time, a reverse voltage
(VO − Vin − VC1 ) is then developed across L2 causing a
linear decrease in current iL2 . The state circuit is shown in
Fig. 2b. During the period of off-state as shown in Fig. 3,
time from t1 to t2, the currents flowing through the
components are expressed in (3)
⎧
⎪ VC1
⎪
⎪ iL1 = IL1 − t
⎪
⎪ t1
⎪
⎪
L1
⎨ VO − Vin − VC1
Fig. 4 Average equivalent circuit of the proposed converter
iL2 = IL2 − t (3)
⎪
⎪
t1
L2
⎪
⎪
⎪
⎪ i =0
⎪
⎩ iQ = i flowing through the inductor L1 and equal to IL1 , and the
in L2
current through Q is the sum of IL1 and IL2 . Diodes D1
and D2 are off and the voltages across them are
During this period, Q maintains off-state and D3 is
(E + VC1 ) and VC2 , respectively. Therefore the switches
reverse-biased, their currents hence are zero. D1 is
Q and D3 can be replaced by the corresponding current
connected in series with L1; its current is therefore the
sources, D1 and D2 by voltage sources, respectively and
same as the current flowing through L1. Diode D2 and the
the equivalent circuit therefore can be derived as shown
input power source Vin are connected in series with L2 and
in Fig. 4.
there is the same current flowing through the three
Using the circuit theory in the equivalent circuit to obtain
components. From t1 to t2, inductors L1 and L2 both are
the averaged state-space description, the corresponding
discharged. The off-state is end at t2 and the currents iL1
state-space model for the proposed quadratic boost
and iL2 both reach to their minimum valuesIL1 t2 and IL2 t2
converter is therefore derived as (7)
as given by (4)
⎧ VC1 ⎡ ⎤
⎪
⎪ = IL1 = IL1 − (1 − U )TS 1−u
⎨ IL 1 t2 t0 t1
⎡ ⎤ 0 0 − 0
L1 † ⎢ L1 ⎥
⎪ VO − Vin − VC1
(4) iL1 ⎢ ⎥⎡ ⎤
⎪
⎩ IL = IL2 = IL2 − (1 − U )TS ⎢ ⎥ ⎢ 1 1 − u⎥ iL1
⎢ † ⎥ ⎢ 0 − ⎥
⎢ iL ⎥ ⎢ L2 ⎥ ⎢ ⎥
2 t2 t0 t1
L2 0
⎢ 2 ⎥=⎢ L2 ⎥⎢ iL2 ⎥
⎢
⎢ † ⎥ ⎢1 − u ⎥⎢ ⎥
⎢ vC ⎥ ⎢ 1 ⎥⎣ vC1 ⎦
The voltage across C1 and the output voltage hence can be ⎣ 1⎦ ⎢ C − 0 0 ⎥
C1 ⎥ v
derived from (2) and (4) as given by (5) † ⎢ 1 ⎥ C2
vC2 ⎣ 1−u 1 ⎦
⎧ 0 0 −
⎪ U C2 RL C2
⎪
⎨ VC1 = V
1 − U in ⎡u⎤
Vin + VC1 (5)
⎪
⎪ 1 ⎢ L1 ⎥
⎩ VO = = Vin ⎢1⎥
1−U (1 − U )2 ⎢ ⎥
+⎢ ⎥
⎢ L2 ⎥e(t) (7)
And the voltage transfer ratio of the proposed converter is ⎢ ⎥
⎣0⎦
then
0
V 1
G= O= (6)
Vin (1 − U )2
Without loss of generality, the above description can be
It can be seen that the voltage conversion ratio of the generalised as (8)
proposed converter is the quadratic of the classical boost
converter. Therefore it has the ability to provide high †
step-up voltage gain and more suitable for high-voltage x(t) = A(u)x(t) + B(u)e(t) (8)
conversion ratio applications.

3 Modelling of the proposed converter
In the following discussion, for simplicity, we assume that the
AC ripples in the inductor currents and capacitor voltages are
small and symbol E represents the input voltage. IL1 and IL2
represent the currents flowing through inductors L1 and L2.
VC1 and VC2 are the voltages across the capacitor C1 and
C2. The detailed analysis of the proposed converter using
separated pulse width modulation (PWM) switches
approach [21] is given as follows.
As previously analysed, during the switch Q on-time,
the current flowing through D3 is the same as the current
where x(t) = [iL1 iL2 vC1 vC2 ]T [ R4 is the average
values of the state vector; A(u) is a matrix in R 4 × 4 and
B(u) is a vector in R 4; e(t) ∈ R is the input voltage; RL is a
pure resistance load; and u is a switching function with
binary value [0, 1]. The value of u is 1 when switch Q is
turned on and 0 when Q is turned off.
The above representation is non-linear as the matrices A(u)
and B(u) depend on the control signal u(t) ∈ R. The
linearisation process describes the converter behaviour to
small perturbations around an operation point [22]. The
nominal steady-state operating point of the converter can be
derived by setting (8) as AX + BE = 0, and it therefore can

1164 IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1162–1170

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0205
 www.ietdl.org
be described by (9) When the perturbation of the input voltage e(t) is
negligible, that is, ẽ = 0, the second column of the matrix
⎧
⎪ U B can be deleted and the small signal state-space model is
⎪
⎪ VC1 = E
⎪
⎪ 1 − U then expressed as (14)
⎪
⎪
⎪
⎪ 1 ⎡ ⎤
⎪
⎨ VC2 = (1 − U )2 E
⎪
⎡ · ⎤ −
1−U
(9) ⎢ 0 0
L1
0 ⎥⎡ ⎤
⎪ E ĩ ⎢ ⎥
⎪
⎪ IL1 = ⎢ 1⎥ ⎢L
1 1 − U ⎥ ĩL1
⎪
⎪ (1 − U )4 RL ⎢ · ⎥ ⎢ 0 − ⎥ ⎢ ⎥
⎪ ⎢ ĩ ⎥ ⎢ 0
L2 ⎥
⎪
⎪
⎪ ⎢ L2 ⎥ ⎢ L2 ⎥⎢⎢
ĩL2 ⎥
⎥
⎪ E =
⎢ · ⎥ ⎢1 − U ⎥⎢
⎪
⎩ IL2 = ⎢ ⎥ ⎢ 1 ⎥⎣ ṽC ⎥ ⎦
(1 − U )3 RL ⎢ ṽC1 ⎥ ⎢ − 0 0 ⎥ 1
⎣ · ⎦ ⎢ C1 C1 ⎥ ṽ
⎢ ⎥ C2
ṽC2 ⎣ 1−U 1 ⎦
where E is the DC input voltage and U is the duty ratio of the 0 0 −
switch. C2 RL C2
By adding small signal perturbations ũ to the nominal duty ⎡ ⎤
UE
ratio U and ẽ to the nominal input voltage E, the input voltage ⎢ ⎥
⎢ (1 − U )L1 ⎥
and the duty ratio of the converter can be expressed as (10) ⎢ ⎥
⎢ UE ⎥
 ⎢ (1 − U )2 L ⎥
e(t) = E + ẽ ⎢ ⎥
(10) +⎢ 2
⎥ũ (14)
u(t) = U + ũ ⎢ UE ⎥
⎢− ⎥
⎢ (1 − U ) RL C1 ⎥
4
⎢ ⎥
where ẽ is far less than its DC average value E, that is, ẽ ≪ E; ⎣ UE ⎦
−
and ũ ≪ U . The state variables and the output voltage can (1 − U ) RL C2
3
also be derived as (11)
 4 High-voltage gain and lower buffer
x(t) = X + x̃
(11) capacitor stress
vO (t) = VO + ṽO
According to the analysis in former sections, in theory, the
When expressions (9) and (10) are substituted into (7), a voltage transfer ratio of the proposed converter is the
linear mode therefore can be derived by assuming that the quadratic of the classical boost converter at the same duty
perturbations are sufficiently small such that non-linear ratio. This relationship also can be indicated by Fig. 5,
terms can be neglected and the linear small signal which is the voltage gain against the duty ratio of the
state-space model is obtained as given by (12) classical boost and the quadratic boost converters with ideal
⎡ ⎤ components. Considering the parasitic series resistance of
1−U
⎡ · ⎤ 0 0 − 0 inductors, the curves of the voltage gain against the duty
⎢ L1 ⎥⎡ ⎤ ratio are depicted in Fig. 6, where r is the parasitic
⎢ ⎥
⎢ ĩL1 ⎥ ⎢ 1 1−U⎥ ĩL1 resistance of the inductor in the boost converter; r1 and r2
⎢ · ⎥ ⎢ 0 − ⎥⎢ ⎥
⎢ ĩ ⎥ ⎢ 0
L2 ⎥
⎢ L2 ⎥ ⎢ L2 ⎥⎢ ĩL2 ⎥ are the parasitic resistance of the inductors L1 and L2 in the
⎢ · ⎥ = ⎢1 − U ⎥⎢ ⎥ quadratic boost converter, respectively, and assuming they
⎢ ⎥ ⎢ 1 ⎥⎢ ṽ ⎥
⎢ ṽC1 ⎥ ⎢ − 0 0 ⎥⎣ C1 ⎦
⎣ · ⎦ ⎢ C1 C1 ⎥ ṽ
⎢ ⎥ C2
ṽC2 ⎣ 1−U 1 ⎦
0 0 −
C2 RL C2
⎡ ⎤
UE U
⎢ (1 − U )L1 L1 ⎥
⎢ ⎥
⎢ UE 1⎥
⎢ ⎥ 
⎢ (1 − U )2 L L2 ⎥
⎢ ⎥ ũ
+⎢ 2
⎥ (12)
⎢ UE ⎥
⎢− 0 ⎥ ẽ
⎢ (1 − U )4 RL C1 ⎥
⎢ ⎥
⎣ UE ⎦
− 0
(1 − U )3 RL C2

The above model describes approximately the behaviour of

the quadratic boost converter and can be further expressed
as (13)

†
x(t) = Ax(t) + Bv(t) (13)

where x(t) ∈ R 4 is the state vector; A ∈ R 4 × 4 is a constant

matrix; B is also a constant matrix in R 4 × 2 and Fig. 5 Voltage gain against duty ratio of the traditional boost and
v(t) = [ ũ ẽ ]T [ R2 is the vector of inputs. quadratic boost converters with ideal inductors

IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1162–1170 1165

doi: 10.1049/iet-pel.2013.0205 & The Institution of Engineering and Technology 2014
www.ietdl.org
Fig. 6 Voltage gain against duty ratio of the traditional boost and
quadratic boost converters with non-ideal inductors
have the same value; RL is the load. It could be seen that the
quadratic boost and the classical boost converters both are not
capable of obtaining an extremely high-voltage gain by an
infinite increase in duty ratio owing to the power loss
caused by the parasitic resistance. However, the higher
voltage gain is easier to be obtained in quadratic boost
converter than the classical boost converter by the
reasonable increase in duty ratio.
To acquire the voltage conversion ratio which is the
quadratic of the classical boost converter, there is a
fourth-order boost converter that has been presented in
literature [16] as shown in Fig. 7. It also employed only
one active switch, three diodes and two LC filters. It is
actually a cascade of two boost converters, and named the
conventional quadratic boost converter in this paper. Its
voltage conversion characteristic is exactly the same as the
proposed converter in our paper.
Comparing the circuit configurations shown in Figs. 1 and
7, the average currents flowing through two inductors L1 and
L2 in the two configurations are the same, respectively, both
can be described as (15)
⎧
⎪ Vin
⎪
⎨ IL1 = (1 − U )4 R
L
(15)
⎪
⎪ Vin
⎩ IL2 =
(1 − U )3 RL
The switch stresses of Q in the two configurations both are
equal to the output voltage and when it is turned on, its
current in the two configurations both are the sum of iL1
and iL2 . These common features can be extended to the
three passive switches D1, D2 and D3. Additionally, the
current flowing through the inductor L2 in Figs. 1 and 7
Fig. 7 Conventional quadratic boost converter
1166
& The Institution of Engineering and Technology 2014
both are directly provided by the buffer capacitor C1 during
the on-state of Q, that is, IC1 = IL2 . In the off-state of Q, the
current flowing through C1 is the difference of that for two
inductors in both circuit configurations, that is,
IC1 = IL1 − IL2 . The current flowing through C1 in the two
topologies of quadratic boost converter is therefore totally
the same.
Therefore the power loss caused by inductors and switches
in the proposed converter is the same as that of the
conventional quadratic boost converter.
The voltage across the buffer capacitor C1, in the
configuration of Fig. 7 is given by (16)
1
VC1 = V (16)
1 − U in
whereas the buffer capacitor voltage in Fig. 1 is then
U
VC1 = V (17)
1 − U in
It can be seen from (16) and (17) that the buffer capacitor
voltage stress for the conventional converter (Fig. 7) is
always higher than the input voltage. In contrast, the buffer
capacitor voltage stress in our proposed converter can be
either higher or lower than input voltage and is always
lower than that in the conventional converter. This
difference can also be clearly indicated in Fig. 8 which
shows VC1 /Vin against the duty ratio in the two different
structures and with the same function converter. Therefore
the smaller size of buffer capacitor could be selected for the
proposed quadratic boost converter. It means that the
smaller parasitic resistance of the buffer capacitor will cause
less power loss than that of the conventional quadratic
boost converter.
Thus, the proposed quadratic boost converter is capable of
converting the input voltage level in higher output voltage
level than the traditional boost converter. In addition, its
buffer capacitor voltage stress is lower than the
conventional quadratic boost converter with the same
function. Therefore it could be designed with smaller and
higher efficiency.
Fig. 8 VC1 /Vin against duty ratio of the proposed converter and
the conventional converter
IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1162–1170
doi: 10.1049/iet-pel.2013.0205
 www.ietdl.org
5 Circuit analysis in DCM operation
Defining the DCM of the proposed converter as the current iL1
or iL2 reduces to zero during Q switch-off state. There are
therefore three DCMs for this converter: DCM-1, iL1
reduces to zero, but iL2 is continuous as shown in Fig. 9;
DCM-2, iL2 reduces to zero, but iL1 is continuous as shown
in Fig. 10; and DCM-3, iL1 and iL2 both are discontinuous
as shown in Fig. 11.

5.1 Circuit analysis in DCM-1 (Fig. 9)

It means that the current iL1 flowing through the inductor L1
increases from zero when Q is turned on at time t0, and the
inductor current reaches to the peak iL1 max at time t1
because the switch Q being off. This maximum value is
given as

Vin
iL1 max = UTS (18)
L1

And then, Q maintains off and the inductor current iL1 begins
to fall because the voltage across L1 becomes negative of the
value VC1 . The current iL1 reduces to zero at time t2 before Q
is turned on again and another expression of the current peak
iL1 _max is then

VC1
iL1 max = U T (19) Fig. 10 Typical waveforms of the proposed converter in DCM-2
L1 1L S

where U1L is the discharging time coefficient of inductor L1

and equal to U1L = (t2–t1)/TS as shown in Fig. 9.

Fig. 9 Typical waveforms of the proposed converter in DCM-1 Fig. 11 Typical waveforms of the proposed converter in DCM-3

IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1162–1170 1167

doi: 10.1049/iet-pel.2013.0205 & The Institution of Engineering and Technology 2014
www.ietdl.org
The capacitor voltage VC1 is therefore can be derived from (24) and given by (27)
(18) and (19) as given by (20)
U + U2L  
VC1 =
U
V (20) VO = Vin + VC1
U1L in U2L
  
U + U1L U + U2L
= Vin (27)
For the inductor L2, its current iL2 is continuous as described U1L U2L
in Section 2. The output voltage VO therefore can be derived
as given by (21)
And then the voltage gain for the DCM-3 operation is
1   U + U1L expressed in (28)
VO = Vin + VC1 = V (21)
1−U (1 − U )U1L in
  
And the voltage transfer ratio is then U + U1L U + U2L
G3 = (28)
U1L U2L
U + U1L
G1 = (22)
(1 − U )U1L

5.2 Circuit analysis in DCM-2 (Fig. 10)

The inductor current iL2 reduces to zero during switch-off

state. It means it will increase linearly from time t0, and
reaches to its peak iL2 _max at the end of the switch-on state
(t1). The maximum current is given in (23)

Vin + VC1
iL2 max = UTS (23)
L2

And then the inductor current iL2 decreases linearly from the
peak because there is a reverse voltage (VO − Vin − VC1 )
developed across L2. Before the switch Q is turned on
again, the current drops to zero at time t2 as shown in
Fig. 10. The current peak iL2 _max is also can be expressed
as (24)

VO − Vin − VC1
iL2 max = U2L TS (24)
L2

where U1L = (t2–t1)/TS is the discharging time coefficient of

inductor L2 as shown in Fig. 10.
For the inductor current flowing through L1 is continuous,
the capacitor voltage VC1 is the same as it in CCM operation
as mentioned in Section 2. The output voltage VO therefore
can be derived from (23) and (24) and given by (25)

U + U2 L   U + U2L
VO = Vin + VC1 = V (25)
U2 L (1 − U )U2L in

And the voltage transfer ratio for DCM-2 operation is

therefore expressed in (26)

U + U2 L
G2 = (26)
(1 − U)U2 L

5.3 Circuit analysis in DCM-3 (Fig. 11)

The two inductor currents iL1 and iL2 both are discontinuous.
It means iL1 and iL2 both reduce to zero during Q switch-off
state as shown in Fig. 11. The voltage across capacitor C1
therefore can be derived from (18) and (19) and is the same Fig. 12 Experimental waveforms under 50 V input to 200 V output
as (20). The output voltage can be derived from (23) and with 600 Ω load

1168 IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1162–1170

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0205

Fig. 13 Measured results of voltage transfer ratio under different
duty ratio
6 Experimental verification
A prototype circuit of the proposed new quadratic boost
converter shown in Fig. 1 has been built to confirm the
theoretical analysis. The converter is switched at 70 kHz
and with the circuit parameters: C1 = 1000 μF, C2 = 330 μF,
L1 = 750 μ and L2 = 2.1 mH. One STF26NM60N MOSFET
and three VS-15ETL06PBF fast recovery diodes are
selected as the switch Q and diodes D1, D2 and D3. When a
50 V DC power was used as the input and a 600 Ω pure
resistor as the load of the prototype, the duty ratio is fixed
at about 0.52, the measured output voltage is 200 V. The
voltage across the buffer capacitor is also measured and is
about 50.5 V. The measured results both are just lower
slightly than their theoretical values which are 217 and
54 V, respectively. In addition, some practical waveforms
are shown in Fig. 12, which include the inductor currents
iL1 and iL2 , the currents flowing through the switch Q and
diodes D1–D3, the buffer capacitor voltage and the output
voltage. They all agree with the theoretical prediction.
Fig. 13 shows the measured results of voltage transfer
ratios VO/Vin and VC1 /Vin against the duty ratio. It can be
Fig. 14 Practical efficiency against the output current
IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1162–1170
doi: 10.1049/iet-pel.2013.0205
www.ietdl.org
clearly seen from the figure that the voltage gain (VO/Vin)
will increase rapidly with increasing of the duty ratio,
especially when the duty ratio is larger than 0.5. This is
because there is a quadratic function between the two
elements. In contrast, the buffer capacitor voltage VC1 rises
steadily along with increasing of the duty ratio and its value
even lower than input voltage when the duty ratio is below
0.5.
When the duty ratio is fixed at 0.5, the measured efficiency
of the prototype circuit with different input voltages and
different output currents is shown in Fig. 14. It can be seen
that the maximum 96.2% efficiency is achieved at 60 V
input and 0.5–0.6 A output operating condition. Another
important tendency can be obtained from the figure is that
there is a rise trend in efficiency when input voltage
increases. This phenomenon can be explained as follows:
when the duty ratio and output current both are constant,
the power loss caused by the voltage drops of diodes
D1–D3 and the on-resistance of the switch Q is also basically
constant, and input current is always the same and then, the
greater the input voltage means the higher the throughput
power, but also means that the efficiency will be higher.
Finally, the dynamical performances of the prototype
converter with closed-loop voltage-mode PI-controller are
shown in Fig. 15. The controller is designed based on the
pulse width modulator TL5001 which is capable of
soft-start function [23]. The proportional gain KP and
integrative time Ti are designed as 0.68 and 1.5 × 10−3,
respectively. Fig. 15a gives its transient response for step
changes in load current from 0.4 to 0.8 A and the
dynamical performance with changed input voltage is given
in Fig. 15b. When both load current and input voltage are
changed, the dynamical performance is given in Fig. 15c. It
could be seen that the prototype converter has good load
regulation and excellent ability of anti-disturbance.
7 Conclusions
A new quadratic boost converter with reduced buffer
capacitor stress is presented in this paper, which consists of
one active switch, three passive switches and two LC filters.
The operation and voltage transfer features of the proposed
converter were analysed for a continuous mode and three
different discontinuous modes. Its small signal state-space
model was also derived and given in this paper.
Comparisons are made between the proposed circuit
1169
& The Institution of Engineering and Technology 2014
www.ietdl.org
Fig. 15 Transient response in closed-loop for the proposed
converter
a With step changes in load current from 0.4 to 0.8 A
b With changed input voltage from 50 to 85 V
c With both of changed input voltage from 70 to 80 V and load current from
0.4 to 0.8 A
configuration and the conventional quadratic boost converter
as well as the traditional boost converter. The main features of
the proposed converter include quadratic voltage gain of the
traditional boost converter and lower voltage stress on the
buffer capacitor. Finally, a prototype circuit of the proposed
converter is implemented in the laboratory. Experimental
results verify that high step-up voltage gain, low buffer
capacitor voltage stress and high efficiency can be achieved.
In the further works, the soft-switching technique and the
bidirectional version will be developed and derived for the
proposed converter and it is expected to show a good
performance for high step-up industrial applications.
1170
& The Institution of Engineering and Technology 2014
8 Acknowledgment
The authors gratefully acknowledge the financial support
from the Research Office, The Hong Kong Polytechnic
University under the project number G-YM11.
9 References
1 Zhao, Y., Li, W., Deng, Y., He, X.: ‘High step-up boost converter with
passive lossless clamp circuit for non-isolated high step-up applications’,
IET Power Electron., 2011, 4, (8), pp. 851–859
2 Jovcic, D.: ‘Step-up DC–DC converter for megawatt size applications’,
IET Power Electron., 2010, 3, (3), pp. 369–378
3 Chen, S.-M., Liang, T.-J., Yang, L.-S., Chen, J.-F.: ‘A cascaded high
step-up DC–DC converter with single switch for microsource
applications’, IEEE Trans. Power Electron., 2011, 26, (4),
pp. 1146–1153
4 Mohan, N., Undeland, T., Robbins, P.: ‘Power electronic: converters,
applications and design’ (John Wiley & Sons, New York, 1995, 2nd
edn.)
5 Cheng, H., Smedley, K.M., Abramovitz, A.: ‘A wide-input-wide-output
(WIWO) DC-DC convertor’, IEEE Trans. Power Electron., 2010, 25,
(2), pp. 280–289
6 Law, K.K., Eric Cheng, K.W.: ‘Examination of the frequency
modulation and lifting techniques for the generalized power factor
correction switched-capacitor resonant converter’, Int. J. Circuit
Theory Appl., 2008, 36, (7), pp. 839–855
7 Hui, S.Y.R., Cheng, K.W.E., Prakash, S.R.N.: ‘A fully soft-switched
extended-period quasi-resonant power-factor-correction circuits’, IEEE
Trans. Power Electron., 1997, 12, (5), pp. 922–930
8 Yang, L.-S., Liang, T.-J., Lee, H.-C., Chen, J.-F.: ‘Novel high step-up
DC–DC converter with coupled-inductor and voltage-doubler circuits’,
IEEE Trans. Ind. Electron., 2011, 58, (9), pp. 4196–4206
9 Park, K.-B., Moon, G.-W., Youn, M.-J.: ‘Nonisolated high step-up
stacked converter based on boost-integrated isolated converter’, IEEE
Trans. Power Electron., 2011, 26, (4), pp. 577–587
10 Fardoun, A.A., Ismail, E.H.: ‘Ultra step-up DC–DC converter with
reduced switch stress’, IEEE Trans. Ind. Appl., 2010, 46, (5),
pp. 2025–2034
11 Ismail, E.H., Al-Saffar, M.A., Sabzali, A.J., Fardoun, A.A.: ‘A family of
single-switch PWM converters with high step-up conversion ratio’,
IEEE Trans. Circuits Syst., 2008, 55, (4), pp. 1159–1171
12 Hwu, K.I., Yau, Y.T.: ‘High step-up converter based on charge pump
and boost converter’, IEEE Trans. Power Electron., 2012, 27, (5),
pp. 2484–2494
13 Wijeratne, D.S., Moschopoulos, G.: ‘Quadratic power conversion for
power electronics: principles and circuits’, IEEE Trans. Circuit Syst. I,
Regul. Pap., 2012, 59, (2), pp. 426–438
14 Maksimovic, D., Cuk, S.: ‘Switching converters with wide dc
conversion range’, IEEE Trans. Power Electron., 1991, 6, (1),
pp. 377–390
15 Pacheco, V.M., do Nascimento Jr., A.J., Farias, V.J., Batista Vieira Jr.,
J., de Freitas, L.C.: ‘A quadratic buck converter with lossless
commutation’, IEEE Trans. Ind. Electron., 2000, 47, (2), pp. 264–272
16 Luo, F.L., Ye, H.: ‘Positive output cascade boost converters’, IEE Proc.
Electr. Power Appl., 2005, 151, (5), pp. 590–606
17 Morales-Saldana, J.A., Galarza-Quirino, R., Leyva-Ramos, J.,
Carbajal-Gutierrez, E.E., Ortiz-Lopez, M.G.: ‘Multiloop controller
design for a quadratic boost converter’, IET Electr. Power Appl.,
2007, 1, (3), pp. 362–367
18 Leyva-Ramos, J., Ortiz-Lopez, M.G., Diaz-Saldierna, L.H.,
Morales-Saldana, J.A.: ‘Switching regulator using a quadratic boost
converter for wide DC conversion ratios’, IET Power Electron., 2009,
2, (5), pp. 605–613
19 Barreto, L.H.S.C., Coelho, E.A.A., Farias, V.J., de Oliveira, J.C., de
Freitas, L.C., Vieira Jr., J.B.: ‘A quasi-resonant quadratic boost
converter using a single resonant network’, IEEE Trans. Ind.
Electron., 2005, 52, (2), pp. 552–557
20 Cheng, K.W.E., Evans, P.D.: ‘Parallel-mode extended-period
quasi-resonnat converter’, IEE Proc., Electr. Power Appl., 1991, 138,
(5), pp. 243–251
21 Van Dijk, E., Spruijt, J.N., O’Sullivan, D.M., Klaassens, J.B.:
‘PWM-switch modeling of DC-DC converters’, IEEE Trans. Power
Electron., 1995, 10, (6), pp. 659–665
22 Carbajal-Gutierrez, E.E., Morales-Saldana, J.A., Leyva-Ramos, J.:
‘Modeling of a single-switch quadratic buck converter’, IEEE Trans.
Aerosp. Electron. Syst., 2005, 41, (4), pp. 1451–1457
23 Designing With the TL5001 PWM Controller, Texas Instruments, 1995
IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1162–1170
doi: 10.1049/iet-pel.2013.0205